CN103123915A - 调节封装组件的连接器的尺寸 - Google Patents

调节封装组件的连接器的尺寸 Download PDF

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Publication number
CN103123915A
CN103123915A CN2012101820901A CN201210182090A CN103123915A CN 103123915 A CN103123915 A CN 103123915A CN 2012101820901 A CN2012101820901 A CN 2012101820901A CN 201210182090 A CN201210182090 A CN 201210182090A CN 103123915 A CN103123915 A CN 103123915A
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connector
lateral dimension
connectors
density
package assembling
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CN103123915B (zh
Inventor
赖志维
何明哲
杨宗翰
汪青蓉
张家栋
郭宏瑞
刘重希
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
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Abstract

一种器件包括在封装组件(package component)的顶表面上的多个连接器。多个连接器包括具有第一横向尺寸的第一连接器、以及具有第二横向尺寸的第二连接器。第二横向尺寸大于第一横向尺寸。在平行于封装组件的主表面的方向上测量第一横向尺寸和第二横向尺寸。本发明还提供了一种调节封装组件的连接器的尺寸。

Description

调节封装组件的连接器的尺寸
技术领域
本发明涉及半导体领域，更具体地，本发明涉及一种调节封装组件的连接器的尺寸。
背景技术
集成电路由诸如晶体管和电容器的差不多几百万个有源器件制成。这些器件最初相互隔离，并且随后被互连以形成功能电路。典型互连结构包括诸如金属线(引线)的横向互连件、以及诸如通孔和接触件的垂直互连件。互连结构越来越多地确定性能限制和现代集成电路的密度。
在互连结构的顶部上，形成连接器结构。连接器结构可以包括在对应芯片的表面上暴露的焊料球或金属柱。通过焊料球或金属柱进行电连接，以将芯片连接至封装衬底或另一管芯。
发明内容
为了解决现有技术中所存在的问题，根据本发明的一个方面，提供了一种器件，包括：多个连接器，位于封装组件的顶表面上，其中，所述多个连接器包括：第一连接器，具有第一横向尺寸；以及第二连接器，具有第二横向尺寸，其中，所述第二横向尺寸大于所述第一横向尺寸，并且其中，在平行于所述封装组件的主表面的方向上测量所述第一横向尺寸和所述第二横向尺寸。
在该器件中，从所述封装组件的上方向下看去，所述第一连接器和所述第二连接器具有基本相同的形状。
在该器件中，还包括：第一局部表面区域，包括多个第一连接器，所述第一连接器是所述多个第一连接器中的一个，其中，所述多个第一连接器中的每一个都具有所述第一横向尺寸；以及第二局部表面区域，包括多个第二连接器，所述第二连接器是所述多个第二连接器中的一个，其中，所述多个第二连接器中的每一个都具有所述第二横向尺寸。
在该器件中，所述第一局部表面区域具有第一连接器密度，所述第二局部表面区域具有第二连接器密度，并且其中，所述第一连接器密度基本等于所述第二连接器密度。
在该器件中，所述多个第一连接器均匀地分布在所述第一局部表面区域中，并且其中，所述多个第二连接器均匀地分布在所述第二局部表面区域中。
在该器件中，所述第二横向尺寸与所述第一横向尺寸的比率小于约2.55。
在该器件中，所述第一连接器和所述第二连接器包括金属柱。
根据本发明的另一方面，提供了一种器件，包括：封装组件，包括：第一表面区域；多个第一连接器，位于所述封装组件的顶表面上，并且均匀地分布在所述第一表面区域中，其中，所述多个第一连接器具有第一横向尺寸；第二表面区域；以及多个第二连接器，位于所述封装组件的顶表面上，并且均匀地分布在所述第二表面区域中，其中，所述多个第二连接器具有第二横向尺寸，并且其中，所述第二横向尺寸大于所述第一横向尺寸。
在该器件中，所述第一表面区域具有第一连接器密度，所述第二表面区域具有第二连接器密度，并且其中，所述第一连接器密度基本等于所述第二连接器密度。
在该器件中，所述多个第一连接器的第一间距与所述第一横向尺寸具有第一比率，其中，所述多个第二连接器的第二间距与所述第二横向尺寸具有第二比率，并且其中，所述第一比率基本等于第二比率。
在该器件中，所述第二横向尺寸与所述第一横向尺寸的比率小于约2.55。
在该器件中，所述多个第一连接器和所述多个第二连接器包括金属柱。
在该器件中，所述封装组件是器件管芯。
根据本发明的又一方面，提供了一种方法，包括：在封装组件的表面上形成第一连接器，其中，所述第一连接器具有第一横向尺寸；以及在所述封装组件的所述表面上形成第二连接器，其中，所述第二连接器具有比所述第一横向尺寸更大的第二横向尺寸，并且其中，同时形成所述第一连接器和所述第二连接器。
在该方法中，还包括：修改所述封装组件的第一设计以生成第二设计，其中，所述修改步骤包括：将所述封装组件的所述第一设计中的所述第一连接器的均匀横向尺寸减小到所述第二设计中的所述第一横向尺寸；以及将所述封装组件的所述第一设计中的所述第二连接器的所述均匀横向尺寸增大到所述第二设计中的所述第二横向尺寸；以及对物理晶圆实施所述封装组件的所述第二设计，其中，实施所述第二设计的步骤包括：形成所述第一连接器和所述第二连接器的步骤。
在该方法中，还包括：在减小和增大的步骤之前，计算所述封装组件的所述第一设计中的所有连接器的平均连接器密度；计算所述第一横向尺寸，其中，计算所述第一横向尺寸，使得当所述第一连接器的横向尺寸减小到所述第一横向尺寸时，包含所述第一连接器的第一局部区域的连接器密度减小到基本等于所述平均连接器密度；以及计算所述第二横向尺寸，其中，计算所述第二横向尺寸，使得当所述第二连接器的横向尺寸减小到所述第二横向尺寸时，包含所述第二连接器的第二局部区域的连接器密度增加到基本等于所述平均连接器密度。
在该方法中，根据计算所述第一横向尺寸的步骤获得的尺寸小于设计规则所允许的最小尺寸，并且其中，将所述第一横向尺寸设置为所述最小尺寸。
在该方法中，根据计算所述第二横向尺寸的步骤获得的尺寸大于设计规则所允许的最大尺寸，并且其中，将所述第一横向尺寸设置为所述最大尺寸。
在该方法中，所述第二横向尺寸与所述第一横向尺寸的比率小于约2.55。
在该方法中，形成所述第一连接器和所述第二连接器的步骤包括电镀。
附图说明
为了更完整地理解实施例及其优点，现在结合附图对以下说明作出参考，其中：
图1至图5是根据多种实施例的在封装组件的表面上制造连接器的中间阶段的横截面图；
图6示出根据实施例的在封装组件的第一设计中的连接器的俯视图；
图7示出根据实施例的连接器的俯视图；
图8示出在封装组件的第一设计中限定局部区域；
图9示出根据实施例的两个局部表面区域，其中，在封装组件的第二设计中，从第一设计放大一个表面区域中的连接器，同时从第一设计缩小一个表面区域中的连接器；以及
图10示出封装组件的第一设计的多个部分，其中，根据实施例，修改第一设计中的连接器的尺寸，以生成第二设计。
具体实施方式
下面，详细讨论本发明各实施例的制造和使用。然而，应该理解，本发明提供了许多可以在各种具体环境中实现的可应用的概念。所讨论的具体实施例仅仅示出了制造和使用本发明的具体方式，而不用于限制本发明的范围。
根据多种实施例，提供一种用于形成用于封装组件的连接器的方法。示出了根据实施例设计和制造连接器的中间阶段。论述实施例的改变。在多个附图和示意性实施例中，使用类似参考数字指示类似元件。
参考图1，提供封装组件2。在整个说明书中，还将封装组件2称为芯片2，其可以是晶片的一部分。芯片2包括衬底10。在一些实施例中，衬底10是诸如硅衬底的半导体衬底，但是其可以由诸如硅锗、碳化硅、砷化镓等的其他半导体材料形成。可以在衬底10的表面处形成半导体器件14，其可以包括晶体管、二极管、电阻器等。在衬底10上方形成互连结构12，其包括形成在其中并且电连接至半导体器件14的金属线和通孔(未示出)。金属线和通孔可以由铜或铜合金形成，并且可以使用镶嵌工艺形成。互连结构12可以包括层间电介质(ILD)和金属间电介质(IMD)。
在可选实施例中，芯片2是中介层(interposer)或封装衬底，并且基本没有包括晶体管的有源器件和诸如电阻器、电容器、电感器等的无源器件。在这些实施例中，衬底10可以由半导体材料或介电材料形成，并且连接器可以形成在衬底的相对侧上，并且相互电连接。
在互连结构12上方形成金属焊盘28。金属焊盘28可以包含铝(Al)、铜(Cu)、银(Ag)、金(Au)、镍(Ni)、钨(W)、其合金、和/或其多层。在典型实施例中，金属焊盘28包含铝铜。金属焊盘28可以例如通过下部互连结构12电连接至半导体器件14。可以形成钝化层30以覆盖金属焊盘28的边缘部分。在典型实施例中，钝化层30由聚酰亚胺或诸如氧化硅、氮化硅的其他介电材料、及其多层形成。
参考图2，形成凸块下金属(UBM)层36。在一个实施例中，UBM层36可以包括钛层、以及钛层上的铜种子层。图3A示出掩模48的形成，例如，其可以由光刻胶或干膜形成。图案化掩模48，并且通过掩模48中的开口40暴露UBM层36的一部分。接下来，形成金属柱50。在一个实施例中，将芯片2的晶片放到电镀溶液(未示出)中，并且执行电镀步骤，以形成金属柱50。金属柱50位于UBM层36上并且在开口40中。电镀可以是电板电镀(electro plating)、无电镀、浸镀等。在典型实施例中，金属柱50包括纯铜、基本纯的铜、或铜合金。
可以在金属柱50上形成金属盖52。在一个实施例中，金属盖52包含镍。在可选实施例中，金属盖52包含其他材料，诸如锡、钯、或其合金。金属盖52还可以是复合层，包括诸如镍层、钯层等的多层。接下来，在金属盖52上形成焊锡盖54，其可以包含Sn-Ag、Sn-Cu、Sn-Ag-Cu等。例如，可以用掩模48作为电镀掩模，使用电镀来电镀金属盖52和焊锡盖54。
在形成金属柱50/金属盖52/焊锡盖54之后，可以去除掩模48。然后，例如通过蚀刻，去除由掩模48覆盖的UBM层36的多个部分。所得到的结构如图4A中所示。在所得到的结构中，金属柱50、金属盖52、以及焊锡盖54在下文中被结合称为连接器56(或可选地称为金属凸块)。
图3B示出一个可选实施例，其中，连接器56是例如将掩模48作为电镀掩模，使用电镀来电镀的焊料柱。接下来，如图4B中所示，去除掩模48和由掩模48覆盖的UBM层36的多个部分。然后，执行回流以熔化焊料柱56，形成焊料球60，如图5中所示。
在整个说明书中，参考图4A和图4B，连接器56的横向尺寸在下文中是指横向尺寸W1。在平行于封装组件2的主要顶面2A的方向上测量横向尺寸W1。连接器56的高度H1还在图4A和图4B中标记。
图6示出芯片2的中间设计的俯视图，其包括芯片2的顶面上的多个连接器56。可以了解，芯片2是芯片2的设计(在下文中称为第一设计)而不是物理芯片。在整个芯片2上，连接器56的横向尺寸(大小)W1是均匀的。芯片2包括一些(局部)表面区域(在下文中称为稀疏区域)，其中，连接器56比其他(局部)表面区域(在下文中被称为密集区域)中更稀疏。稀疏区域具有比密集区域的连接器密度更小的连接器密度。可以通过将对应局部区域100中的所有连接器56的顶视图面积相加，以获得对应局部区域100中的总连接器面积，并且用总连接器面积除以局部区域100的总面积，计算芯片2的局部表面区域100的连接器密度。局部区域100可以被限定为具有尺寸d1(参考图6)，其可以比对应芯片2中的连接器56的最小间距Pmin的四倍更大、或比其六倍更大。可替换地，局部区域100可以被限定为具有比对应芯片尺寸d2的十分之一更大的尺寸d1(参考图6)。
进行实验，以了解局部区域中的连接器密度与局部区域中的连接器56的连接器高度H1(如图4A和图4B中所示)之间的关系。可以发现，虽然在同一芯片2中同时形成所有连接器56，但是在同一芯片2上，密集区域中的连接器56具有较小的高度H1，并且稀疏区域中的连接器56具有较大的高度H1。而且，如果两个局部表面区域具有相同连接器密度，则这两个局部表面区域中的连接器高度H1基本相等。
基于这些发现，调节芯片中的连接器56的横向尺寸W1(图4A、图4B和图6)，以使整个芯片2的连接器密度更加均匀。从而，修改芯片的第一设计中的连接器56的横向尺寸W1以生成第二设计，其在物理芯片/晶片上实现。在修改中，可以增加稀疏区域中的连接器56的横向尺寸W1。可以减小密集区域中的连接器56的横向尺寸W1。
在一些实施例中，在修改之前，首先计算芯片2上的平均连接器密度BDavg，并且修改每个局部区域100中的连接器56的横向尺寸W1，使得对应局部区域100中的连接器密度被调节成基本等于平均连接器密度BDavg。注意，当修改横向尺寸W1时，可以不改变对应芯片2中的连接器56的位置。
再次参考图6，提供芯片2和连接器56的第一设计，可以计算平均连接器密度BDavg。由于在整个封装组件2上的连接器56在第一设计中可以具有相同大小，所以可以通过将单个连接器56的面积乘以芯片2上的连接器56的总数，以获得芯片2中的所有连接器56的总(俯视图)面积，来计算平均连接器密度BDavg。然后，将连接器56的总面积除以芯片2的总面积，以获得平均连接器密度BDavg。
在图6中，限定具有尺寸d1的典型局部区域100(并且面积等于d12)。局部连接器密度BDlocal可以按照局部区域100中的所有连接器56的总面积除以面积d12计算出。从而，等式1可以表达为：
BDavg＝(CxW12xcon_countlocal)/total_arealocal     [Eq.1]
其中，con_countlocal是局部区域中的连接器56的总数，total_arealocal是局部区域100的总面积，并且在典型实施例中，可以等于d12。因数C是形状因数，其中，(Cx W12)表示具有尺寸W1的单个连接器56的面积。
图7示出一些典型连接器56的顶视图，其被用于解释形状因数C的概念。将认识到，连接器56的俯视图形状可以是圆形、六边形、八边形、正方形等。形状因数C与连接器56的形状相关。例如，当连接器具有尺寸等于W1的圆形形状时，形状因数C是π/4。当连接器56具有横向尺寸等于W1的八边形形状时，形状因数C是2/(1+sqrt(2))，其中，sqrt是运算符“平方根”。当连接器56具有诸如椭圆形的另一形状时，可以推倒形状因数C，例如通过绘制具有与椭圆形相同面积的等效圆形57，并且计算形状因数C。
基于等式1，为了将局部区域100中的局部连接器密度调节为平均连接器密度BDavg，将局部区域中的所有连接器56的横向尺寸修改为等于Wadj，其可以表达为：
Wadj＝sqrt((BDavg x total_arealocal)/(con_countlocal/C))    [Eq.2]
可以从图8看出，芯片2可以划分为多个局部区域100。根据一些实施例，限定局部区域100，使得加在一起的所有局部区域100覆盖整个芯片2。在图8中示出典型局部区域100。可以使用等式2计算每个局部区域100中的连接器56的期望修改后的横向尺寸。在遍历所有局部区域100并且所有局部区域100中的相应连接器56均被调节为对应横向尺寸Wadj之后，芯片2上的所有局部区域100的连接器密度等于或基本等于BDavg。从而，生成芯片2的连接器56的第二设计。图9示出典型第二设计的多个部分。然后，可以在物理芯片上实现第二设计，其中，图9还可以表示物理芯片的顶面的多个部分。
由于不同局部区域100的值con_countlocal可以不同，所以所得到的不同局部区域100的Wadj可以相互不同，但是它们还可以相同。图9示意性地示出芯片2的两个局部区域100的部分的顶视图(标记为100-1和100-2)。请注意，除了连接器56的大小被调节为不同横向尺寸，并且所示的局部区域100-1和100-2是两个典型局部区域之外，图9还可以类似于图6那样绘制。实线圆圈表示大小修改之后的连接器56，同时虚线圆圈表示大小调节之前的连接器56。在为稀疏区域的局部区域100-1中，将连接器56的横向尺寸从W1调节为Wadj1，其可以大于原始横向尺寸W1。在为密集区域的局部区域100-2中，可以将连接器56的横向尺寸从W1调节为Wadj2，其可以小于原始横向尺寸W1。在一些实施例中，调节之前的连接器56的形状可以与调节之后的连接器56的形状相同。例如，如果连接器56的原始形状是圆形，则调节后的连接器56的形状也是圆形。如果连接器56的原始形状是六边形，则调节后的连接器56的形状也是六边形。
在一些典型实施例中，连接器56被均匀地分布在局部区域100-1和100-2中，局部区域100-1中的间距P1和局部区域100-2中的间距P2可以具有以下关系：
P1/Wadj1＝P2/Wadj2                  [Eq.3]
注意，可以存在多个局部区域(诸如，局部区域100-1)，其中，对应调节后的横向尺寸Wadj1大于原始宽度W1并且相互不同。而且，可以存在多个局部区域(诸如，局部区域2)，其中，对应调节后的横向尺寸Wadj1小于原始宽度W1并且相互不同。
在一些实施例中，设计规则可以要求，对于特定设计，芯片上的连接器的最大横向尺寸不能大于预定最大横向尺寸Wmax，并且不能小于预定最小横向尺寸Wmin。从而，如果通过等式2获得的Wadj值大于最大横向尺寸Wmax，将相应局部区域100中的对应连接器56的横向尺寸设置为Wmax，而不是计算出的Wadj值。相反地，如果通过等式2获得的Wadj值小于最小横向尺寸Wmin，将相应局部区域100中的对应连接器56的横向尺寸设置为Wmin，而不是所计算出的Wadj值。
设计规则还可以要求，对于特定设计，芯片上的连接器的最大连接器密度不能大于预定最大连接器密度BDmax，并且不能小于预定最小连接器密度BDmin。从而，横向尺寸的调节受BDmax和BDmin的值限制。从而，需要遵循以下等式：
sqrt(BDmin/BDmax)≤Wadj/W1≤sqrt(BDmax/BDmin)    [Eq.4]
其中，Wadj表示芯片上的任何连接器的调节后的横向尺寸。
根据一些典型实施例，值BDmax是26％，并且值BCmin是4％。从而，sqrt(BDmax/BDmin)等于约2.55。从而，可以将Wadj/W1的值设置为在1/2.55和2.55之间的值，并且不能超过该范围。结果，在调节芯片设计中的连接器的横向尺寸之后，芯片上的最大连接器的横向尺寸与芯片上的最小连接器的横向尺寸的比率可以小于约sqrt(BDmax/BDmin)，或在给定实例中，约为2.55。
如图10中所示，芯片2可以包括多个部分200(标记为200A、200B和200C)，其中，相同部分200中的连接器56具有相同连接器密度，同时不同部分200可以具有不同连接器密度。在每个部分200中，均匀地分布连接器56。部分200可以包括通过其他部分相互分离的多个表面区域。例如，部分200B包括四个分离区域。在典型实施例中，假设在芯片上存在n个部分，其中，n是大于1的整数，可以使用以下等式计算芯片2的平均连接器密度：
BDavg＝错误！未找到引用源。             [Eq.5]
其中，BDi是部分i(其可以是200A、200B或200C等)的连接器密度，其还可以通过将部分i中的所有连接器的面积相加，并且将部分i中的所有连接器的总面积除以部分i的总面积计算。
可以使用以下等式计算每个部分i中的期望连接器密度BDi，其中，i为1至n：
Wadj_i＝sqrt((BDavg x total_areai)/(con_counti/C))     [Eq.6]
其中，Wadj_1是尺寸调节后的部分i中的连接器56的横向尺寸，total_areai是部分i的总面积，con_counti是部分i中的连接器56的总数，并且C是形状因数。BDavg从等式5获得，并且其还是将由大小调节实现的期望平均连接器密度。
将想到，通过使用等式5和6，芯片中的最大连接器的横向尺寸与芯片中的最小连接器的横向尺寸的比率可以具有以下关系：
1＜R≤sqrt((total_areamax/con_countmax)/(total_areamin/con_countmin))[Eq.7]
其中，值total_areamax是在对应芯片中的所有连接器密度中连接器密度最高的部分的总面积。值total_areamin是在对应芯片中的所有连接器密度中连接器密度最低的部分的总面积。值con_countmax是在对应芯片中连接器密度最高的部分中的所有连接器的总数。值con_countmin是在对应芯片中连接器密度最低的部分中的所有连接器的总数。
可以了解，在根据一些实施例的上述连接器大小调节之后，可以改变平均连接器密度BDavg。当例如如果使用等式5至等式7调节连接器大小时，这可能发生。根据一些实施例，可以执行迭代(iteration)，并且可以重复关于等式5至等式7的上述步骤，以基于调节后的大小进一步调节连接器大小。可以重复迭代，直到所计算的Wadj_i值会聚(converge)到预定阈值。
使用等式1至等式4或等式5至等式7，可以将芯片上的连接器的横向尺寸调节至不同值，以生成芯片2的第二设计，如图9中示意性示出的。然后，可以在物理半导体芯片/晶片上实现如图9中所示的第二设计，其中，执行图1至图4中所示的步骤，以形成具有调节后的尺寸的连接器56。所得到的芯片2可以由图4A/4B和图9表示。
可以由包括软件和硬件的计算机执行关于等式1至等式7的步骤。而且，可以将实施例的中间和最终结果保存在诸如硬盘、光盘等的非暂时计算机可读介质上。例如，诸如图6和图9中所示的多种图案可以保存在非暂时计算机可读介质上。另外，与等式1至等式7相关的计算步骤还可以由计算机执行，其重新得到用于根据实施例执行计算的程序代码。程序代码还可以保存在诸如硬盘、光盘等的非暂时计算机可读介质上。
根据实施例，通过调节连接器尺寸，如果所有连接器均具有相同横向尺寸，在整个芯片/晶片上的连接器密度可以更加均匀。从而，连接器的高度更加均匀，并且改进连接器的顶表面的共面性。这还导致减少不良接头。还可以实现对共面性具有非常严格要求的接合处理，具有改进的可靠性。
根据实施例，一种器件包括在封装组件的顶表面上的多个连接器。多个连接器包括具有第一横向尺寸的第一连接器、以及具有第二横向尺寸的第二连接器。第二横向尺寸大于第一横向尺寸。在平行于封装组件的主表面的方向上测量第一横向尺寸和第二横向尺寸。
根据其他实施例，一种封装组件包括第一表面区域、在封装组件的顶表面上并且均匀地分布在第一表面区域中的第一多个连接器，其中，第一多个连接器具有第一横向尺寸。封装组件还包括第二表面区域、以及在封装组件的顶表面上并且均匀地分布在第二表面区域中的第二多个连接器。第二多个连接器具有第二横向尺寸，并且第二横向尺寸大于第一横向尺寸。
根据另外的其他实施例，一种方法包括：在封装组件的表面上形成第一连接器，其中，第一连接器具有第一横向尺寸，并且在封装组件的表面上形成第二连接器。第二连接器具有比第一横向尺寸更大的第二横向尺寸。同时形成第一连接器和第二连接器。
尽管已经详细地描述了本发明及其优势，但应该理解，可以在不背离所附权利要求限定的本发明主旨和范围的情况下，做各种不同的改变，替换和更改。而且，本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员应理解，通过本发明，现有的或今后开发的用于执行与根据本发明所采用的所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造，材料组分、装置、方法或步骤根据本发明可以被使用。因此，所附权利要求应该包括在这样的工艺、机器、制造、材料组分、装置、方法或步骤的范围内。此外，每条权利要求构成单独的实施例，并且多个权利要求和实施例的组合在本发明的范围内。

Claims (10)

1.一种器件，包括：
多个连接器，位于封装组件的顶表面上，其中，所述多个连接器包括：
第一连接器，具有第一横向尺寸；以及
第二连接器，具有第二横向尺寸，其中，所述第二横向尺寸大于所述第一横向尺寸，并且其中，在平行于所述封装组件的主表面的方向上测量所述第一横向尺寸和所述第二横向尺寸。
2.根据权利要求1所述的器件，其中，从所述封装组件的上方向下看去，所述第一连接器和所述第二连接器具有基本相同的形状。
3.根据权利要求1所述的器件，还包括：
第一局部表面区域，包括多个第一连接器，所述第一连接器是所述多个第一连接器中的一个，其中，所述多个第一连接器中的每一个都具有所述第一横向尺寸；以及
第二局部表面区域，包括多个第二连接器，所述第二连接器是所述多个第二连接器中的一个，其中，所述多个第二连接器中的每一个都具有所述第二横向尺寸。
4.根据权利要求3所述的器件，其中，所述第一局部表面区域具有第一连接器密度，所述第二局部表面区域具有第二连接器密度，并且其中，所述第一连接器密度基本等于所述第二连接器密度。
5.根据权利要求3所述的器件，其中，所述多个第一连接器均匀地分布在所述第一局部表面区域中，并且其中，所述多个第二连接器均匀地分布在所述第二局部表面区域中。
6.根据权利要求1所述的器件，其中，所述第二横向尺寸与所述第一横向尺寸的比率小于约2.55。
7.根据权利要求1所述的器件，其中，所述第一连接器和所述第二连接器包括金属柱。
8.一种器件，包括：
封装组件，包括： 
第一表面区域；
多个第一连接器，位于所述封装组件的顶表面上，并且均匀地分布在所述第一表面区域中，其中，所述多个第一连接器具有第一横向尺寸；
第二表面区域；以及
多个第二连接器，位于所述封装组件的顶表面上，并且均匀地分布在所述第二表面区域中，其中，所述多个第二连接器具有第二横向尺寸，并且其中，所述第二横向尺寸大于所述第一横向尺寸。
9.根据权利要求8所述的器件，其中，所述第一表面区域具有第一连接器密度，所述第二表面区域具有第二连接器密度，并且其中，所述第一连接器密度基本等于所述第二连接器密度。
10.一种方法，包括：
在封装组件的表面上形成第一连接器，其中，所述第一连接器具有第一横向尺寸；以及
在所述封装组件的所述表面上形成第二连接器，其中，所述第二连接器具有比所述第一横向尺寸更大的第二横向尺寸，并且其中，同时形成所述第一连接器和所述第二连接器。 
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TW201322404A (zh) 2013-06-01
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US20140308764A1 (en) 2014-10-16
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