TWI497675B - 連接元件及其形成方法以及封裝元件 - Google Patents

連接元件及其形成方法以及封裝元件 Download PDF

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Publication number
TWI497675B
TWI497675B TW101142758A TW101142758A TWI497675B TW I497675 B TWI497675 B TW I497675B TW 101142758 A TW101142758 A TW 101142758A TW 101142758 A TW101142758 A TW 101142758A TW I497675 B TWI497675 B TW I497675B
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Taiwan
Prior art keywords
contacts
lateral dimension
contact
density
partial surface
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TW101142758A
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English (en)
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TW201322404A (zh
Inventor
Chih Wei Lai
Ming Che Ho
Tzong Hann Yang
Chien Rhone Wang
Chia Tung Chang
Hung Jui Kuo
Chung Shi Liu
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Taiwan Semiconductor Mfg Co Ltd
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Publication of TW201322404A publication Critical patent/TW201322404A/zh
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
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Description

連接元件及其形成方法以及封裝元件
本發明有關於元件，且特別是有關於連接元件及其形成方法、封裝元件。
積體電路係由數百萬個主動元件(例如電晶體與電容)所組成。在一開始的時候，這些元件是彼此分離的，之後，這些元件會相互連接而構成功能電路(functional circuit)。習知的互連結構包括橫向互連結構以及垂直互連結構，橫向互連結構例如為金屬線(線路)，垂直互連結構例如為導電通孔(via)以及接點。互連結構對於現今積體電路的效能以及密度的影響日益增加。
在互連結構上可形成接點結構。接點結構可包括銲球或是金屬柱，其暴露於各自的晶片表面上。可藉由銲球或是金屬柱將晶片電性連接至封裝基板或是另一晶片。
本發明一實施例提供一種連接元件，包括：多個接點，位於一封裝組件的一頂面上，其中接點包括：一第一接點，具有一第一橫向尺寸；以及一第二接點，具有一第二橫向尺寸，其中第二橫向尺寸大於第一橫向尺寸，且第一橫向尺寸與第二橫向尺寸係由平行於封裝組件的一主表面的方向上量測而得的。
本發明一實施例提供一種封裝元件，包括：一封裝組件，包括：一第一表面區；一第一複數個接點，位於一封裝組件的一頂面上，並均勻地分布於第一表面區中，其中 第一複數個接點具有一第一橫向尺寸；一第二表面區；以及一第二複數個接點，位於封裝組件的頂面上，並均勻地分布於第二表面區中，其中第二複數個接點具有一第二橫向尺寸，且第二橫向尺寸大於第一橫向尺寸。
本發明一實施例提供一種連接元件的形成方法，包括：形成一第一接點於一封裝組件的一表面上，其中第一接點具有一第一橫向尺寸；以及形成一第二接點於封裝組件的表面上，其中第二接點具有一第二橫向尺寸大於第一橫向尺寸，且第一接點與第二接點係同時形成。
以下將詳細說明本發明實施例之製作與使用方式。然應注意的是，本發明提供許多可供應用的發明概念，其可以多種特定型式實施。文中所舉例討論之特定實施例僅為製造與使用本發明之特定方式，非用以限制本發明之範圍。此外，在不同實施例中可能使用重複的標號或標示。這些重複僅為了簡單清楚地敘述本發明，不代表所討論之不同實施例及/或結構之間具有任何關連性。再者，當述及一第一材料層位於一第二材料層上或之上時，包括第一材料層與第二材料層直接接觸或間隔有一或更多其他材料層之情形。在圖式中，實施例之形狀或是厚度可擴大，以簡化或是方便標示。再者，圖中未繪示或描述之元件，為所屬技術領域中具有通常知識者所知的形式。
以下將介紹多個實施例之用於封裝組件的多個的形成方法。以下將介紹多個實施例之設計與製作接點的中間步驟。以下將詳述實施例的多種不同的變化。在不同的圖式 中，相似的元件符號係用以標示相似的元件。
請參照第1圖，提供一封裝組件2。在本說明書中，封裝組件2亦稱為晶片2，其可為一晶圓的一部分。晶片2包括基板10。在一些實施例中，基板10為一半導體基板，例如一矽基板，或者是亦可以其他半導體材料形成基板10，例如矽鍺、碳化矽、砷化鎵、或其相似物。可在基板10的表面上形成半導體元件14，其可包括電晶體、二極體、電阻、或其相似物。可在基板10上形成互連結構12，其包括金屬線以及形成於其中並電性耦接至半導體元件14的導孔(未繪示)。可以銅或是銅合金形成金屬線與導孔，並可以大馬士革製程(damascene process，又稱鑲嵌製程)形成金屬線與導孔。互連結構12可包括一層間介電層(inter-layer dielectric，ILD)以及金屬間介電層(inter-metal dielectric，IMD)
在其他實施例中，晶片2為一插入基板或是一封裝基板，且大體上並未有主動元件(包括電晶體)以及被動元件(例如電阻、電容、電感、及/或其相似物)設置於晶片2上。在這些實施例中，基板10可由半導體材料或是介電材料所構成，且多個接點可分別形成在基板10的對側上並彼此電性耦接。
金屬墊28形成在互連結構12上。金屬墊28的材質可包括鋁、銅、銀、金、鎳、鎢、前述之合金、及/或前述之多層結構。在一實施例中，金屬墊28的材質包括鋁銅。金屬墊28例如經由其下的的互連結構12而電性耦接至半導體元件14。可形成保護層30以覆蓋金屬墊28的邊緣部分。 在一實施例中，保護層30的材質包括聚亞醯氨(polyimide)、或是其他的介電材料，例如氧化矽、氮化矽、以及前述材料之多層結構。
請參照第2圖，形成凸塊下金屬層(under-bump metallurgy layer，UBM layer)36。在一實施例中，凸塊下金屬層36可包括一鈦層、以及一位於鈦層上的銅晶種層。第3A圖繪示形成罩幕48的步驟，罩幕48可例如為光阻或是乾膜。圖案化罩幕48，且罩幕48的開口40暴露出部分的凸塊下金屬層36。接著，形成金屬柱(metal pillar)50。在一實施例中，將具有晶片2的晶圓置入一鍍液(plating solution，未繪示)中，並進行一鍍膜製程(plating step)以形成金屬柱50。金屬柱50位於凸塊下金屬層36上並位於開口40中。前述鍍膜製程可為電鍍製程、無電鍍製程、浸鍍製程(immersion plating)、或其相似製程。在多個實施例中，金屬柱50包括純銅、實質上純的銅、或銅合金。
可在金屬柱50上形成金屬蓋52。在一實施例中，金屬蓋52的材質包括鎳。在另一實施例中，金屬蓋52的材質包括其他材料，例如錫、鈀、或其合金。金屬蓋52亦可為一複合層，包括多個膜層，例如一鎳層、一鈀層、或其相似物。接著，在金屬蓋52上形成銲料蓋54，銲料蓋54的材質包括錫銀、錫銅、錫銀銅、或其相似物。可以罩幕48為鍍膜罩幕，利用例如電鍍製程形成金屬蓋52與銲料蓋54。
在形成金屬柱50/金屬蓋52/銲料蓋54之後，可移除罩幕48。之後，可以例如蝕刻的方式移除凸塊下金屬層36 之被罩幕48所覆蓋的部份。最終形成的結構係如第4A圖所示。在最終形成的結構中，金屬柱50、金屬蓋52、以及銲料蓋54之全體於下文中可稱為接點56(或者是稱為金屬凸塊)。
第3B圖繪示另一實施例，其中接點56為一銲料柱，其係以罩幕48為鍍膜罩幕進行例如電鍍製程而形成的。接著，如第4B圖所示，移除罩幕48以及凸塊下金屬層36之被罩幕48所覆蓋的部分。然後，進行一回焊製程(reflow)以熔化銲料柱56而形成銲球60，如第5圖所示。
在本說明書中，請參照第4A圖與第4B圖，接點56的橫向尺寸在下文中係稱為橫向尺寸W1。橫向尺寸W1的量測方向係平行於封裝組件2的主要頂表面2A。接點56的高度H1亦標記在第4A圖與第4B圖中。
第6圖繪示晶片2的中間設計的上視圖，其包括位於晶片2之頂表面上的多個接點56。可以知道的是，晶片2為晶片2的一種設計(於下文中稱為第一設計)，而非一實體晶片(physical chip)。在整個晶片2中，接點56的橫向尺寸W1可皆相同。晶片2包括一些(局部)表面區(於下文中稱為稀疏區，sparse region)，位於稀疏區中的接點56比位於其他(局部)表面區(於下文中稱為稠密區，dense region)中的接點稀疏。稀疏區的接點密度小於稠密區的接點密度。計算晶片2的一局部表面區100的接點密度的方法可為藉由將在個別局部區100中的所有接點56的上視面積相加以獲得個別局部區100中的總接點面積，並使總接點面積除以局部區100的總面積即可獲得晶片2的 局部表面區100的接點密度。在個別的晶片2中，局部區100可具有尺寸d1(請參照第6圖)，尺寸d1可大於4倍或是6倍的(接點56的)最小間距(minimum pitch)Pmin 。或者是，局部區100可具有尺寸d1(請參照第6圖)大於個別晶片尺寸d2的十分之一。
已進行實驗研究在局部區中的接點密度以及在局部區中的接點56的高度H1(如第4A、4B圖所示)之間的關係。由實驗結果觀察到在相同的晶片2上，在稠密區中的接點56具有較小的高度H1，在稀疏區中的接點56具有較大的高度H1，即使是同時在晶片2上形成所有的接點56。再者，若是兩局部表面區具有相同的接點密度，則在這兩局部表面區中的接點的高度H1大致上彼此相等。
基於這些發現，可調整晶片中的接點56的橫向尺寸W1(第4A、4B、6圖)，以使整個晶片2的接點密度更加一致。對應地修改晶片的第一設計中的接點56的橫向尺寸W1，以產生一第二設計，第二設計係實施於實體晶片/晶圓上。在前述修改步驟中，可增加在稀疏區中的接點56的橫向尺寸W1。可減少在稠密區中的接點56的橫向尺寸W1。
在一些實施例中，在進行前述修改步驟之前，可先計算晶片2上的平均接點密度BDavg ，之後才調整各局部區100中的接點56的橫向尺寸W1，以將各局部區100中的接點密度調整成大體上等於平均接點密度BDavg 。值得注意的是，當修改橫向尺寸W1，可不改變各晶片2中的接點56的位置。
請再次參照第6圖，可利用第一設計的晶片2與接點56計算出平均接點密度BDavg 。由於第一設計中遍佈封裝組件2的接點56可具有相同尺寸，故可藉由使單一接點56的面積乘以晶片2上的接點56的總數，以獲得晶片2中的所有接點56的總(上視)面積(亦即，接點56在上視圖中的總面積)。然後，可使接點56的總面積除以晶片2的總面積，以得到平均點密度BDavg 。
第6圖係繪示出局部區100具有尺寸d1(且具有面積等同於d12 )。可計算出局部接點密度BDlocal 的方法為將局部區100中的所有接點56的總面積除以面積d12 。因此，式1可表示為：BDavg =(C x W12 x con_countlocal )/total_arealocal [式1]
其中con_countlocal 為位於局部區中的接點56的總數，且total_arealocal 為局部區100的總面積，在本實施例中，局部區100的總面積可等同於d12 。係數C為一形狀因子(shape factor)，其中(C x W12 )代表具有尺寸W1的單一接點56的面積。
第7圖繪示多個示範接點56的上視圖，用以解釋形狀因子C的概念。可以知道的是，接點56的上視形狀可為圓形、六角形、八角形、方形、或其相似形狀。形狀因子C與接點56的形狀相關。舉例來說，當接點56呈圓形且直徑等於W1，形狀因子C為π/4。當接點56呈八角形且具有橫向尺寸等於W1，形狀因子C為2/(1+sqrt(2))，其中sqrt為運算子『平方根』。當接點56具有另一種形狀(例如橢圓形)時，形狀因子C亦可推導出來，舉例來說，藉 由畫出等面積的圓57，其具有相等於該橢圓形的面積，以及計算形狀因子C。
根據式一，為了要將局部區100中的局部接點密度調整成等於平均接點密度BDavg ，可將位於局部區中的所有接點56的橫向尺寸修改為等同於Wadj ，其可表示為式2：Wadj =sqrt((BDavg x total_arealocal )/(con_countlocal /C)) [式2]
由第8圖可看出晶片2可被分割成多個局部區100。在一些實施例中，定義了多個局部區100，以使所有局部區100之總體可覆蓋整個晶片2。示範的局部區100係繪示於第8圖中。可使用式2計算出在各局部區100中的接點56的適合修改橫向尺寸(desirable modified lateral dimension)。在計算過所有局部區100之後，在所有局部區100中的接點56被調整成具有各自的橫向尺寸Wadj ，且晶片2上的所有局部區100的接點密度等於(或大致上等於)BDavg 。如此一來，即可形成晶片2的接點56的第二設計。第9圖繪示示範的第二設計的多個部分。可將第二設計施行在一實體晶片上，其中第9圖亦繪示實體晶片的頂表面的多個部分。
由於不同的局部區100的接點總數(con_countlocal )可彼此不同，因此，不同的局部區100的Wadj 可彼此不同，但是不同的局部區100的Wadj 亦可彼此相同。第9圖繪示晶片2的兩個局部區100(第9圖中表示為100-1、100-2)的部份的上視圖。值得注意的是，第9圖可相似於第6圖，兩者差異之處在於第9圖的多個接點56的尺寸被調整成具有不同的橫向尺寸，且圖式的局部區100-1、100-2為兩個 示範局部區。實線圓代表調整尺寸後的接點56，此時，虛線圓代表在調整尺寸之前的接點56。在局部區100-1(其為稀疏區)中，接點56的橫向尺寸由原本的W1被調整成Wadj1 ，其中Wadj1 可大於原本的橫向尺寸W1。在局部區100-2(其為稠密區)中，接點56的橫向尺寸由原本的W1被調整成Wadj2 ，其中Wadj2 可小於原本的橫向尺寸W1。在一些實施例中，調整之前的接點56的形狀可相同於調整之後的接點56的形狀。舉例來說，若是原本的接點56的形狀為圓形，則調整後的接點56的形狀亦為圓形。若是原本的接點56的形狀為六角形，則調整後的接點56的形狀亦為六角形。
在一些示範性的實施例中，接點56係均勻地分布在局部區100-1、100-2中，其中接點56在局部區100-1中的間距(pitch)P1與接點56在局部區100-2中的間距P2可具有下式3的關係：P1/Wadj1 =P2/Wadj2 [式3]
值得注意的是，可以有多個局部區(例如局部區100-1)，在這些局部區中，各自的調整橫向尺寸Wadj1 係大於原本的寬度W1，且這些局部區的這些調整橫向尺寸Wadj1 係彼此不同。再者，可以有多個局部區(例如局部區100-2)，在這些局部區中，各自的調整橫向尺寸Wadj2 係小於原本的寬度W1，且這些局部區的這些調整橫向尺寸Wadj2 係彼此不同。
在一些實施例中，對某些設計而言，設計法則可能有下列要求：晶片上的接點的最大橫向尺寸不能大於一預定 最大橫向尺寸Wmax，且不能小於一預定最小橫向尺寸Wmin。因此，若是經由式2計算得到的Wadj 值大於最大橫向尺寸Wmax，則在對應的局部區100中的各自的接點56的橫向尺寸將會被設置為Wmax，而非計算出的Wadj 值。相反地，若是經由式2計算得到的Wadj 值小於最小橫向尺寸Wmin，則在對應的局部區100中的各自的接點56的橫向尺寸將會被設置為Wmin，而非計算出的Wadj 值。
對某些設計而言，設計法則可能有下列要求：晶片上的接點的最大接點密度不能大於一預定最大接點密度BDmax，且不能小於一預定最小接點密度BDmin。因此，橫向尺寸的調整受限於預定最大接點密度BDmax以及預定最小接點密度BDmin。因此，需遵守下式4：sqrt(BDmin/BDmax)Wadj /W1sqrt(BDmax/BDmin) [式4]
其中Wadj 代表晶片上的任一接點的調整後的橫向尺寸。
在一些示範性的實施例中，BDmax的值為26%，BDmin的值為4%。因此，sqrt(BDmax/BDmin)的值約為2.55。因此，Wadj /W1的值約介於1/2.55與2.55之間，而不會超出此一範圍。因此，在調整一晶片設計中的接點的橫向尺寸之後，晶片上的最大接點的橫向尺寸與晶片上的最小接點的橫向尺寸的比值可約小於sqrt(BDmax/BDmin)，或是約為2.55(前述的實施例)。
如第10圖所示，晶片2可包括多個部分200(在第10圖中係標記為200A、200B、200C)，其中在相同部分200中的多個接點56具有相同的接點密度，而不同的部份200 可具有不同的接點密度。在各部分200中，接點56可均勻地分佈。一部分200可包括多個表面區，這些表面區彼此之間被其他的部份所隔開。舉例來說，部分200B包括四個分離的區域。在示範性的實施例中，假設一晶片上有n個部分，其中n為一大於1的整數，下式可用以計算晶片2的平均接點密度：
其中BDi為第i部分(可為200A、200B、200C等)的接點密度，計算接點密度的方法為：加總第i部分中的所有接點的面積，並使第i部分中的所有接點的總面積除以第i部分的總面積。
下式可用以計算各部分i的適當的接點密度BDi，其中i可為1至n：Wadj_i =sqrt((BDavg x total_areai )/(con_counti /C)) [式6]
其中Wadj_i 係為尺寸調整後的第i部分中的接點56的橫向尺寸，total_areai 為第i部分的總面積，con_counti 為第i部分中的接點56的總數，且C為形狀因子。可由式5得到BDavg ，其係為適當的平均接點密度，並且可藉由調整尺寸來達到適當的平均接點密度。
可以知道的是，藉由使用式5、6，晶片中最大的接點的橫向尺寸與晶片中最小的接點的橫向尺寸的比值R可滿足下列關係式：
其中total_areamax 的值為該部分的總面積，該部分的接 點密度為各晶片的接點密度中最高者。total_areamin 的值為該部分的總面積，該部分的接點密度為各晶片的接點密度中最低者。con_countmax 的值為該部分中的總接點數，該部分的接點密度為各晶片中最高者。con_countmin 的值為該部分中的總接點數，該部分的接點密度為各晶片中最低者。
可以知道的是，在多個實施例中，在前述接點尺寸調整之後，可改變平均接點密度BDavg 。這是可能發生的，舉例來說，當以式5-7調整接點尺寸時。在一些實施例中，可以重複進行調整，前述關於式5-7的步驟可重複進行以根據調整的尺寸(adjusted size)來進一步調整接點的尺寸。可以重複進行調整，直到計算出的Wadj_i 值趨近一預定的臨界值(predefined threshold)。
使用式1-4或是式5-7，晶片上的接點的橫向尺寸可被調整成不同的值以形成晶片2的第二設計，如第9圖所示。第9圖所示的第二設計可被施行在實體半導體晶片/晶圓上，其中進行如第1-4圖所示之步驟以形成具有調整後的尺寸的接點56。最終的晶片2可如第4A、4B、9圖所示。
可利用電腦執行關於式1-7的步驟，其中電腦包括軟體與硬體。再者，多個實施例之中間與最終結果可被儲存於非暫態之電腦可讀介質(non-transitory computer-readable medium)上，例如硬碟(hard drive)、光碟片(disc)、及其相似物。舉例來說，各種圖案(例如第6、9圖所示之圖案)可被儲存於非暫態之電腦可讀介質上。此外，在多個實施例中，關於式1-7的計算步驟亦可利用電腦執行，電腦可擷取程式碼以進行計算。程式碼亦可被儲存於非暫 態之電腦可讀介質上，例如硬碟、光碟片、及其相似物。
相較於所有的接點具有相同的橫向尺寸，在多個實施例中，藉由調整接點尺寸可使整個晶片或是晶圓的接點密度更加均勻。如此一來，可使接點的高度更加均勻，進而提昇接點的頂面的共平面性(co-planarity)，從而減少具有缺陷的連接點。因此，本實施例可達成對於共平面性的要求相當嚴格的接合製程，並且提昇可靠度。
在多個實施例中，一元件包括多個接點位於一封裝組件的一頂表面上。多個接點包括一第一接點具有一第一橫向尺寸以及一第二接點具有一第二橫向尺寸。第二橫向尺寸大於第一橫向尺寸。第一橫向尺寸與第二橫向尺寸係由平行於封裝組件的一主表面的方向上量測而得的。
在多個其他實施例中，一封裝組件包括一第一表面區、以及第一複數個接點位於一封裝組件的一頂表面上並均勻地分佈於第一表面區中，其中第一複數個接點具有一第一橫向尺寸。封裝組件更包括一第二表面區、以及第二複數個接點位於封裝組件的頂表面上並均勻地分佈於第二表面區中。第二複數個接點具有一第二橫向尺寸，且第二橫向尺寸大於第一橫向尺寸。
在又一實施例中，一種方法包括形成一第一接點於一封裝組件的一表面上，其中第一接點具有一第一橫向尺寸，以及形成一第二接點於封裝組件的表面上。第二接點具有一第二橫向尺寸大於第一橫向尺寸。第一接點與第二接點係同時形成。
本發明雖以較佳實施例揭露如上，然其並非用以限定 本發明的範圍，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可做些許的更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
2‧‧‧封裝組件、晶片
2A‧‧‧頂表面
10‧‧‧基板
12‧‧‧互連結構
14‧‧‧半導體元件
28‧‧‧金屬墊
30‧‧‧保護層
36‧‧‧凸塊下金屬層
40‧‧‧開口
48‧‧‧罩幕
50‧‧‧金屬柱
52‧‧‧金屬蓋
54‧‧‧銲料蓋
56‧‧‧接點、銲料柱
57‧‧‧圓
60‧‧‧銲球
100、100-1、100-2‧‧‧局部表面區、局部區
200、200A、200B、200C‧‧‧部分
W1、Wadj、Wadj1、Wadj2‧‧‧橫向尺寸
d1‧‧‧尺寸
d2‧‧‧晶片尺寸
H1‧‧‧高度
Pmin‧‧‧最小間距
P1、P2‧‧‧間距
第1至2圖、第3A-3B圖、第4A-4B圖及第5圖繪示本發明之多個實施例之位於封裝組件的表面上的接點的製程的中間步驟的剖面圖。
第6圖繪示本發明之多個實施例之第一設計的封裝組件的接點的上視圖。
第7圖繪示本發明之多個實施例之接點的上視圖。
第8圖繪示本發明一實施例之在第一設計的封裝組件中定義出的局部區。
第9圖繪示本發明之多個實施例之二個局部表面區，其中在第二設計的封裝組件中，在一表面區中的接點相較於第一設計被擴大，而在一表面區中的接點相較於第一設計被縮小。
第10圖繪示本發明一實施例之一第一設計的封裝組件的多個部分，第一設計中的接點的尺寸被修改為第二設計。
2‧‧‧封裝組件、晶片
56‧‧‧接點、銲料柱
100、100-1、100-2‧‧‧局部表面區、局部區
W1、Wadj1、Wadj2‧‧‧橫向尺寸
P1、P2‧‧‧間距

Claims (8)

  1. 一種連接元件，包括：一第一局部表面區，包括複數個第一接點位於一封裝組件的一頂面上，其中每一該些第一接點具有一第一橫向尺寸，其中該第一局部表面區具有一第一接點密度，且該第一接點密度係該些第一接點之上視總面積除以該第一局部表面區之總面積的值；以及一第二局部表面區，包括複數個第二接點位於該封裝組件的該頂面上，其中每一該些第二接點具有一第二橫向尺寸，該第二橫向尺寸大於該第一橫向尺寸，且該第一橫向尺寸與該第二橫向尺寸係由平行於該封裝組件的一主表面的方向上量測而得的，其中該第二局部表面區具有一第二接點密度，且該第二接點密度係該些第二接點之上視總面積除以該第二局部表面區之總面積的值，其中該第一接點密度大體上等於該第二接點密度。
  2. 如申請專利範圍第1項所述之連接元件，其中在該封裝組件的上視圖中，該些第一接點與該些第二接點實質上具有相同的形狀。
  3. 如申請專利範圍第1項所述之連接元件，其中該些第一接點均勻地分布於該第一局部表面區中，且該些第二接點均勻地分布於該第二局部表面區中。
  4. 一種封裝元件，包括：一封裝組件，包括：一第一表面區；複數個第一接點，位於一封裝組件的一頂面上，並均 勻地分布於該第一表面區中，其中該些第一接點具有一第一橫向尺寸，其中該第一局部表面區具有一第一接點密度，且該第一接點密度係該些第一接點之上視總面積除以該第一局部表面區之總面積的值；一第二表面區；以及複數個第二接點，位於該封裝組件的該頂面上，並均勻地分布於該第二表面區中，其中該第二複數個接點具有一第二橫向尺寸，且該第二橫向尺寸大於該第一橫向尺寸，其中該第二局部表面區具有一第二接點密度，且該第二接點密度係該些第二接點之上視總面積除以該第二局部表面區之總面積的值，其中該第一接點密度大體上等於該第二接點密度。
  5. 如申請專利範圍第4項所述之封裝元件，其中該第一複數個接點的一第一間距與該第一橫向尺寸具有一第一比值，且該第二複數個接點的一第二間距與該第二橫向尺寸具有一第二比值，且該第一比值大體上等於該第二比值。
  6. 一種連接元件的形成方法，包括：形成複數個第一接點於一封裝組件的一表面上的一第一局部表面區中，其中該些第一接點具有一第一橫向尺寸，其中該第一局部表面區具有一第一接點密度，且該第一接點密度係該些第一接點之上視總面積除以該第一局部表面區之總面積的值；以及形成複數個第二接點於該封裝組件的該表面上的一第二表面區中，其中該些第二接點具有一第二橫向尺寸大於該第一橫向尺寸，且該些第一接點與該些第二接點係同時 形成，其中該第二局部表面區具有一第二接點密度，且該第二接點密度係該些第二接點之上視總面積除以該第二局部表面區之總面積的值，其中該第一接點密度大體上等於該第二接點密度。
  7. 如申請專利範圍第6項所述之連接元件的形成方法，更包括：修改該封裝組件的一第一設計以產生一第二設計，該修改的步驟包括：減少該封裝組件的該第一設計中的該第一接點的一均勻橫向尺寸(uniform lateral size)成該第二設計中的該第一橫向尺寸；增加該封裝組件的該第一設計中的該些第二接點的該均勻橫向尺寸成該第二設計中的該第二橫向尺寸；於一實體晶圓上實施該封裝組件的該第二設計，其中實施該第二設計的步驟包括形成該些第一接點與該些第二接點的步驟；在該減少的步驟與該增加的步驟之前，計算該封裝組件的該第一設計中的所有接點的一平均接點密度；計算該第一橫向尺寸，以使當該些第一接點的一橫向尺寸減少成該第一橫向尺寸時，包括該第一接點的該第一局部表面區的第一接點密度減少成大體上等於該平均接點密度；以及計算該第二橫向尺寸，以使當該些第二接點的一橫向尺寸減少成該第二橫向尺寸時，包括該些第二接點的該第二局部表面區的第二接點密度增加成大體上等於該平均接 點密度。
  8. 如申請專利範圍第7項所述之連接元件的形成方法，其中一由計算該第一橫向尺寸的步驟得到的尺寸係小於一設計法則所允許的最小尺寸，則該第一橫向尺寸係設置為該最小尺寸，其中一由計算該第二橫向尺寸的步驟得到的尺寸係大於一設計法則所允許的最大尺寸，且該第一橫向尺寸係設置為該最大尺寸。
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US20140308764A1 (en) 2014-10-16
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