CN110729198B - 半导体装置制造方法及相关半导体裸片 - Google Patents

半导体装置制造方法及相关半导体裸片 Download PDF

Info

Publication number
CN110729198B
CN110729198B CN201910639113.9A CN201910639113A CN110729198B CN 110729198 B CN110729198 B CN 110729198B CN 201910639113 A CN201910639113 A CN 201910639113A CN 110729198 B CN110729198 B CN 110729198B
Authority
CN
China
Prior art keywords
formation
formation site
site
bump
sites
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201910639113.9A
Other languages
English (en)
Other versions
CN110729198A (zh
Inventor
蔡明和
陈俊宏
刘俊成
徐玉女
陈鹏任
郑文豪
蔡启铭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN110729198A publication Critical patent/CN110729198A/zh
Application granted granted Critical
Publication of CN110729198B publication Critical patent/CN110729198B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/05186—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05666—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/05686—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06132—Square or rectangular array being non uniform, i.e. having a non uniform pitch across the array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0614—Circular array, i.e. array with radial symmetry
    • H01L2224/06142—Circular array, i.e. array with radial symmetry being non uniform, i.e. having a non uniform pitch across the array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131—Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H01L2224/1132—Screen printing, i.e. using a stencil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11334—Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H01L2224/11472—Profile of the lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/116—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/11618—Manufacturing methods by patterning a pre-deposited material with selective exposure, development and removal of a photosensitive bump material, e.g. of a photosensitive conductive resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/117—Manufacturing methods involving monitoring, e.g. feedback loop
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13026—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1413—Square or rectangular array
    • H01L2224/14132—Square or rectangular array being non uniform, i.e. having a non uniform pitch across the array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1414—Circular array, i.e. array with radial symmetry
    • H01L2224/14142—Circular array, i.e. array with radial symmetry being non uniform, i.e. having a non uniform pitch across the array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明实施例涉及半导体装置制造方法及相关半导体裸片。本发明实施例涉及一种半导体装置制造方法，其包含：通过根据与各形成位点相关的环境密度调整形成因数来使多个导电凸块同时分别形成于多个形成位点上；其中所述多个导电凸块包含小于一值的凸块间高度均匀性，且所述环境密度由预定范围内各形成位点周围的相邻形成位点的数目确定。

Description

半导体装置制造方法及相关半导体裸片
技术领域
本发明实施例涉及半导体装置制造方法及相关半导体裸片。
背景技术
晶片凸块工艺是半导体封装过程(例如倒装芯片封装或板级封装)的基本过程。凸块工艺是先进晶片级过程技术，其中在将晶片切割成个别芯片之前，使由焊料制成的凸块形成于呈整个晶片形式的晶片上。晶片上的这些凸块(其可由金、铅、焊料、镍或铜构成)是将使裸片及衬底一起互连成单一封装的基本互连组件。这些凸块不仅提供裸片和衬底之间的连接路径，且还在电、机械及热性能中起重要作用。然而，形成于晶片上的这些凸块的不佳高度均匀性会带来电路的可靠性问题。
发明内容
本发明的一实施例涉及一种半导体装置制造方法，其包括：通过根据与各形成位点相关的环境密度调整凸块生成参数来使多个导电凸块同时分别形成于多个形成位点上；其中所述多个导电凸块包含小于一值的凸块间高度均匀性，且所述环境密度由预定范围内各形成位点周围的相邻形成位点的数目确定。
本发明的一实施例涉及一种半导体装置制造方法，其包括：通过根据各形成位点的环境密度调整凸块生成参数来使多个凸块同时形成于多个形成位点上；其中当对应于第一形成位点的第一环境密度和对应于第二形成位点的第二环境密度之间的差值大于预定密度时，所述第二形成位点的横截面积大于所述第一形成位点的横截面积；其中所述第一环境密度由预定范围内所述第一形成位点周围的形成位点的数目确定且所述第二环境密度由所述预定范围内所述第二形成位点周围的形成位点的数目确定。
本发明的一实施例涉及一种半导体裸片，其包括：第一形成位点，其用于形成第一凸块；及第二形成位点，其用于形成第二凸块；其中所述第一形成位点的第一环境密度和所述第二形成位点的第二环境密度之间的差值大于预定密度，且所述第一环境密度由预定范围内所述第一形成位点周围的形成位点的数目确定且所述第二环境密度由预定范围内所述第二形成位点周围的形成位点的数目确定；且其中所述第二形成位点的横截面积和所述第一形成位点的横截面积之间的差值大于预定值。
附图说明
从结合附图来解读的以下详细描述最佳理解本揭露的方面。应注意，根据行业标准做法，各种构件未按比例绘制。事实上，为使讨论清楚，可任意放大或缩小各种构件的尺寸。
图1是绘示根据本揭露的一实施例的形成于实施于晶片上的裸片上的导电凸块的图式。
图2A至图2B是绘示根据本揭露的一实施例的制造对应于凸块的形成位点的过程的图式。
图3A至图3B是绘示根据本揭露的另一实施例的制造对应于凸块的形成位点的过程的图式。
图4是绘示根据本揭露的一实施例的使导电凸块形成于图2B中所展示的形成位点上的过程的图式。
图5是绘示根据本揭露的一实施例的半导体装置制造方法的流程图。
图6A是绘示根据本揭露的一实施例的基于不同环境密度来分成若干区的裸片的图式。
图6B是绘示根据本揭露的一实施例的基于不同环境密度来分成若干区的裸片的图式。
图7是绘示根据本揭露的另一实施例的基于不同环境密度来分成若干区的裸片的图式。
图8是绘示根据本揭露的又一实施例的基于不同环境密度来分成若干区的裸片的图式。
图9是绘示根据本揭露的一实施例的对应于不同环境密度的横截面积的图式。
图10是绘示根据本揭露的一实施例的调整凸块生成参数之后的铜柱的图式。
图11是绘示根据本揭露的一实施例的光刻操作的图式。
图12是绘示根据本揭露的另一实施例的半导体装置制造方法1200的流程图。
图13是绘示根据本揭露的一实施例的裸片上的形成位点的坐标的图式。
图14是绘示根据本揭露的一实施例的对应于裸片600上的各形成位点的OPC的参数的图式。
具体实施方式
本揭露提供用于实施本揭露的不同特征的诸多不同实施例或实例。下文将描述组件及布置的特定实例以简化本揭露。当然，这些仅为实例且不意在限制。例如，在以下描述中，“使第一构件形成于第二构件上方或第二构件上”可包含其中形成直接接触的所述第一构件及所述第二构件的实施例，且还可包含其中额外构件可形成于所述第一构件和所述第二构件之间使得所述第一构件及所述第二构件可不直接接触的实施例。另外，本揭露可在各种实例中重复元件符号及/或字母。此重复是为了简化及清楚且其本身不指示所讨论的各种实施例及/或配置之间的关系。
此外，为便于描述，例如“下面”、“下方”、“下”、“上方”、“上”等等的空间相对术语在本文中可用于描述一元件或构件与另一(些)元件或构件的关系，如图中所绘示。空间相对术语除涵盖图中所描绘的定向之外，还意图涵盖装置在使用或操作中的不同定向。设备可依其它方式定向(旋转90度或依其它定向)且还可因此解释本文所使用的空间相对描述词。
尽管阐述本揭露的广泛范围的数值范围及参数是近似值，但尽可能精确地报告具体实例中所阐述的数值。然而，任何数值本质上含有由各自测试测量中所发现的标准偏差必然所致的特定误差。另外，如本文所使用，术语“约”大体上意指在给定值或范围的10％、5％、1％或0.5％内。替代地，如所属领域的一般技术人员所考量，术语“约”意指在平均数的可接受标准误差内。除在操作/工作实例中之外，或除非另有明确指定，否则所有数值范围、量、值及百分比(例如材料、持续时间、温度、操作条件、量比率及本文所揭露的其类似者的数量的数值范围、量、值及百分比)应被理解为在所有例子中由术语“约”修饰。因此，除非相反指示，否则本揭露及随附权利要求书中所阐述的数值参数是可视需要变动的近似值。最后，各数值参数应至少依据所报告的有效数字的数目及通过应用一般舍入技术来解释。范围可在本文中表示为从一端点至另一端点或在两个端点之间。除非另有指定，否则本文所揭露的所有范围包含端点。
图1是绘示形成于裸片100上的导电凸块bp01至bp12的图式。根据本揭露的一实施例，裸片100位于晶片10(由虚线标记)的部分上。导电凸块bp01至bp12形成于裸片100上且凸块bp01至bp12的各者形成于对应形成位点ST01至ST12上。凸块bp01至bp12可通过不同方法(例如电镀、焊料膏转印、蒸镀及焊球直接粘着等等)来附接至对应形成位点ST01至ST12。应注意，形成于裸片100上的导电凸块的数目及对应形成位点的形状仅供说明。所属领域的技术人员应了解，基于裸片100的布局来确定形成于裸片100上的凸块的数目。再者，任两个相邻凸块之间的距离可不相同。换句话说，包含于裸片100上的特定范围内的凸块的数目可不相同。另外，在形成凸块bp01至bp12的操作期间制造形成位点ST01至ST12，且将在以下段落中描述制造形成位点的细节。
为实现大量生产的目标，使用相同操作来同时形成裸片100上的凸块bp01至bp12。在一些实例中，在相同过程或参数下同时形成裸片100上的凸块bp01至bp12。然而，当形成过程完成时，由于用于形成各凸块的不同负载效应，凸块间高度均匀性会因太大而无法忽略。例如，凸块bp01、bp03、bp04及bp12相对较短，而凸块bp06及bp07相对较高，即使所述凸块被同时形成。凸块bp01至bp12之间的高度偏差会带来可靠性问题且降低晶片10的合格率。本揭露的实施例提出用于形成凸块及相关产品的方法，其可缓解高度偏差问题。
图2A至图2B是绘示根据本揭露的一实施例的制造对应于凸块的形成位点的操作的图式。在图2A的步骤(A)中，制备用于形成导电凸块的晶片20。可观察到，金属垫PAD1及PAD2形成于晶片20(即，衬底)上且钝化层覆盖于其上。在此实施例中，金属垫PAD1及PAD2可由铜或铝等等制成。钝化层可由氮化硅(SiN)或二氧化硅(SiO2)制成，且钝化层的材料不应受限于本揭露。接着，在图2A的步骤(B)中，配置为凸块下金属层(UBM)或晶种层的导电层溅镀为扩散阻障及凸块粘着物，且进一步形成凸块和垫之间的连接。在此实施例中，导电层可由TiN、TaN、铜或钛或任何其它适合材料制成，其也不应受限于本揭露。接着，对晶片20执行光刻操作且将在图2B中描述所述操作。应注意，介电层(图2A中未展示)可作为保护层或隔离层涂布于钝化层和导电层之间。在此实施例中，介电层可由聚酰亚胺制成且介电层的材料也不应受限于本揭露。
在图2B的步骤(C)中，涂布光敏材料层或光致抗蚀剂(PR)层。在此实施例中，光致抗蚀剂可为正光致抗蚀剂或负光致抗蚀剂，且光致抗蚀剂的类型也不应受限于本揭露。在图2B的步骤(D)中，将掩模安置于晶片上方且使用紫外(UV)光、电子束或离子束来暴露经涂布PR。在图2B的步骤(E)中，在曝光之后图案化PR，且因此在衬底上提供图案化掩模210。可观察到，在曝光之后于PR中形成开口OP1及OP2，其中开口OP1及OP2的各者被视为对应凸块的形成位点。另外，各开口暴露被视为形成位点的横截面积(图2B中注释为“A1”及“A2”)的底面。
图3A至图3B是绘示根据本揭露的另一实施例的导电凸块的工艺的图式。在图3A的步骤(A)中，制备用于形成导电凸块的晶片30。可观察到，金属垫形成于晶片30(即，衬底)上且钝化层覆盖于其上。在此实施例中，金属垫可由铜制成，且钝化层可由氮化硅(SiN)或二氧化硅(SiO2)制成。金属垫及钝化层的材料不应受限于本揭露。接着，在图3A的步骤(B)中，使介电层作为保护层或隔离层涂布于钝化层上。在此实施例中，介电层可由聚酰亚胺制成，然而，介电层的材料也不应受限于本揭露。在图3A的步骤(C)中，将配置为凸块下金属层(UBM)或晶种层的导电层溅镀于介电层上。在此实施例中，导电层可由TiN、TaN、铜或钛或任何其它适合材料制成，其也不应受限于本揭露。图3A中可为了简明而省略一些步骤，例如，在涂布介电层之后，可执行蚀刻步骤以形成介电层，如图3A的步骤(B)中所展示。另外，聚酰亚胺的形成可经历例如涂布、曝光、显影、固化等等的步骤。接着，执行光刻操作。
在图3B的步骤(D)中，涂布光敏材料层或光阻层。在此实施例中，光致抗蚀剂(PR)可为正光致抗蚀剂或负光致抗蚀剂，然而，光致抗蚀剂的类型也不应受限于本揭露。在图3B的步骤(E)中，将重布层(RDL)涂布于导电层上。在此实施例中，RDL可由用于重新布线的含铜钛合金制成，然而，RDL的材料不应受限于本揭露。在图3B的步骤(F)中，由PR剥离器剥离PR。在图3B的步骤(G)中，将另一介电层涂布于RDL及导电层上，且因此在衬底上提供图案化掩模310。在此实施例中，介电层可由苯并环丁烯(BCB)制成，然而，介电层的材料不应受限于本揭露。图案化掩模310包含开口OP3，其中开口OP3被视为对应凸块的形成位点。另外，各开口暴露被视为形成位点的横截面积(图3B中注释为“面积”)的底面。图3B中可为了简明而省略一些步骤，例如，PR层的形成可经历例如图2B中所提及的涂布及曝光的步骤。所属领域的技术人员应在阅读图2B的实施例之后了解光刻操作。如果所产生的结果大致上相同，那么所属领域的技术人员应了解，图3A至图3B中所展示的步骤无需依准确顺序执行。应注意，用于形成形成位点的操作不受限于图2A至图3B的实施例。所属领域的技术人员应了解用于形成形成位点的替代操作。
图4是绘示根据本揭露的一实施例的使导电凸块形成于图2B中所展示的形成位点上的操作的图式。在图4的步骤(A)中，用例如铜的导电材料同时填充开口OP1及OP2以形成铜柱CP1及CP2。在此实施例中，在开口OP1及OP2中电镀导电材料(即，铜)。接着，在图4的步骤(B)中，在铜柱CP1及CP2上电镀焊料层。在图4的步骤(C)中，由PR剥离器剥离PR。在图4的步骤(D)中，回焊焊料层，同时将铜柱CP1及CP2视为掩模，图案化导电层。
如上文所提及，由于负载效应，铜柱CP1和CP2之间存在高度偏差。例如，形成于开口OP1中的铜柱的高度是H1，而形成于开口OP2中的铜柱是H2。H1和H2之间的差值(即，H1-H2)>k，其中k可为例如10um的值。此高度偏差会带来可靠性问题。应注意，形成图4的导电凸块的操作可与制造图3A至图3B的形成位点的操作或任何其它不同操作协调。
图5是绘示根据本揭露的一实施例的用于形成凸块的半导体装置制造方法500的流程图。如果结果大致上相同，那么图5的步骤无需依准确顺序执行。方法500概述如下。
在步骤502中：根据与各形成位点相关的环境密度来调整凸块生成参数。
参考图6A，其是绘示根据本揭露的一实施例的基于不同环境密度来分成区Z1及Z2的裸片600的面积的图式。事实上，根据裸片的布局，形成于裸片上的导电凸块可布置成若干集群。在图6A中，裸片600的区Z2中的凸块被密集形成，而形成于区Z1(裸片600的左手侧或右手侧)中的凸块被稀疏形成。因此，步骤502中所提及的环境密度由预定范围内各形成位点周围的相邻形成位点的数目确定。在此实施例中，预定范围由其面积是L1*L2的四边形范围确定，如图6A中所展示。图6A的左手侧上的区Z1中的形成位点(例如601)对应于相同于图6A的右手侧上的区Z1中的形成位点(例如602)的环境密度ED1。区Z2中的形成位点(例如603及604)对应于大于ED1的环境密度ED2。
然而，预定范围可为具有较小大小的另一四边形范围。参考图6B，其是绘示根据本揭露的另一实施例的基于不同环境密度来分成区Z1'及Z2'的裸片600的面积的图式。在此实施例中，利用具有较小大小的预定范围。例如，预定范围由其面积是L3*L2的四边形范围确定，如图6B中所展示，其中在此实施例中，L3是L1的一半。就这些配置来说，位于裸片600的四个角上的区Z1'中的形成位点对应于相同环境密度ED1'，且位于裸片600的中间的区Z2'中的形成位点对应于大于ED1'的环境密度ED2'。所属领域的技术人员应了解，鉴于环境密度ED1'及ED1两者在单位面积中包含相同数目个形成位点，环境密度ED1'相同于ED1。同样地，环境密度ED2'相同于ED2。
应注意，四边形范围可为图2B及图3B中所提及的光刻操作的单位曝光面积。然而，这不应受限于本揭露。再次参考图6A，就这些配置来说，步骤502中针对具有相同环境密度的形成位点所提及的凸块生成参数被调整为相同。换句话说，对应于形成位点601及602的凸块生成参数在步骤502之后相同，且对应于形成位点603及604的凸块生成参数在步骤502之后相同。应注意，形成于裸片600的各区中的形成位点的数目仅供说明，且不应受限于本揭露。另外，预定范围未必为四边形范围。在其它实施例中，预定范围可为基于裸片的布局的圆形或其它形状。
参考图7，其是绘示根据本揭露的另一实施例的基于不同环境密度来分成区Z1至Z4的裸片700的图式。在图7中，裸片700的区Z1中的凸块被密集形成，而裸片700的区Z2、Z3及Z4中的凸块被稀疏形成。区Z1中的形成位点(例如701及702)对应于环境密度ED3，区Z2中的形成位点(例如703及704)对应于小于ED3的环境密度ED4，Z3中的形成位点对应于小于ED4的环境密度ED5。在图7中，不存在区Z4中所描绘的形成位点，其指示对应于区Z4的环境密度ED6可为最低。就这些配置来说，步骤502中针对具有相同环境密度的形成位点所提及的凸块生成参数被调整为相同。换句话说，对应于形成位点701及702的凸块生成参数在步骤502之后相同，且对应于形成位点703及704的凸块生成参数在步骤502之后相同。应注意，形成于裸片700的各区中的形成位点的数目仅供说明，不应受限于本揭露。
参考图8，其是绘示根据本揭露的又一实施例的基于不同环境密度来分成区Z1至Z2的裸片800的图式。如图8中所展示，区Z2包含位于远离区Z1的裸片800的不同角上的4个部分。因此，区Z1和区Z2之间存在稀疏区域。区Z1中的形成位点(例如801及802)对应于环境密度ED7，且区Z2中的形成位点(例如803及804)对应于小于ED7的环境密度ED8。就这些配置来说，步骤502中针对具有相同环境密度的形成位点所提及的凸块生成参数被调整为相同。换句话说，对应于形成位点801及802的凸块生成参数在步骤502之后相同，且对应于形成位点803及804的凸块生成参数在步骤502之后相同。应注意，形成于裸片800的各区中的形成位点的数目仅供说明，其不应受限于本揭露。
事实上，裸片600及700可实施于片上系统(SOC)，且裸片800可实施于具有高带宽存储器(HBM)的SOC，其中裸片800的区Z1是SOC部分且裸片的区Z2是HBM部分。然而，这仅供说明，其不应受限于本揭露。
在实施例中，步骤502中所提及的凸块生成参数是各形成位点的暴露横截面积。参考图9，其是绘示根据本揭露的实施例的对应于不同环境密度的横截面积的图式。在图9中，衬底的左手侧是对应于环境密度ED1的区Z1，而衬底的右手侧是对应于环境密度ED2的区Z2。环境密度ED1大于ED2，即，区Z1中的形成位点(即，沟槽901至903)被密集形成，而区Z2中的形成位点(即，沟槽904至905)被稀疏形成。根据不同环境密度，区Z1中的形成位点的总横截面积被调整为相对较小，而区Z2中的形成位点的总横截面积被调整为相对较大。如图9中所展示，区Z1中的形成位点的横截面积是X，而区Z2中的形成位点的横截面积是Y，且Y大于X。当环境密度ED1比环境密度ED2大15％时，横截面积Y比横截面积X大10％。
再次参考图5，在步骤504中，使多个导电凸块同时分别形成于多个形成位点上。在调整凸块生成参数之后，将图4中所提及的导电材料(例如铜)同时填充于形成位点内以形成导电凸块。
参考图10，其是绘示根据本揭露的实施例的调整凸块生成参数之后的铜柱的图式。通过根据不同环境密度调整横截面积，当将图4中所提及的导电材料(例如铜)同时填充于沟槽901至905中时，形成于沟槽901至905中的铜柱之间的凸块间高度均匀性小于一值。例如，形成于区Z1中的铜柱的高度是H1'，而形成于区Z2中的铜柱的高度是H2'。H1'和H2'之间的差值(即，H1'-H2')<k，其中k可为例如10um的值。因此，有效缓解上文所提及的高度偏差问题。
为调整各形成位点的横截面积，可根据不同环境密度来改变用于光刻操作中的掩模的垫大小。参考图11及图9，其中图11是绘示根据本揭露的一实施例的光刻操作的图式。为根据不同环境密度来获得不同横截面积，在将PR涂布于衬底上之后，使用用于光刻操作的不同掩模大小。例如，为获得具有较小横截面积X的沟槽901至903，用于制造区Z1中的形成位点的使用掩模相对较小。为获得具有较大横截面积Y的沟槽904至905，用于制造区Z2中的形成位点的使用掩模相对较大。换句话说，凸块生成参数不限于为各形成位点的横截面积。在其它实施例中，凸块生成参数是用于光刻操作中的掩模的垫大小。根据不同环境密度来调整掩模的垫大小。
为调整各形成位点的横截面积，可根据不同环境密度来改变用于光刻操作中的曝光能量。例如，为获得具有较小横截面积X的开口901至903，用于制造区Z1中的形成位点的曝光能量相对较小。为获得具有较大横截面积Y的开口904至905，用于制造区Z2中的形成位点的曝光能量相对较大。换句话说，凸块生成参数是用于光刻操作中的曝光能量。根据不同环境密度来调整曝光能量。在一些实施例中，凸块生成参数是光刻操作的光学邻近效应校正(OPC)的参数。根据不同环境密度来调整参数。然而，凸块生成参数不限于为上文所提及的凸块生成参数。
为知悉裸片中的不同环境密度，方法500可进一步包含额外步骤。参考图12，其是绘示根据本揭露的另一实施例的半导体装置制造方法1200的流程图。在步骤1202中，分析裸片的布局以获得裸片中的各形成位点的环境密度。可通过各种方式来分析布局。接着，执行步骤502。
如上文所提及，根据与各形成位点相关的环境密度来调整凸块生成参数。例如，凸块生成参数可为各形成位点的横截面积、用于光刻操作中的掩模的垫大小或光刻操作中的曝光能量。在一些实施例中，引用模型来调整凸块生成参数。例如，模型是涉及裸片中的各形成位点的坐标及对应环境密度的函数。图13是绘示根据本揭露的一实施例的裸片600上的形成位点1301的坐标的图式。如图13中所展示，获取形成位点1301的坐标(Xa,Ya)。可通过分析裸片600的布局或不应受限于本揭露的任何其它适合方法来获取形成位点1301的坐标(Xa,Ya)。接着，为根据与形成位点1301相关的环境密度ED1来调整凸块生成参数，引用函数F(X,Y,D)。例如，函数F(X,Y,D)可书写为：
F(X,Y,D)＝a*X+b*Y+c*D+e，
其中X及Y是形成位点1301的坐标(Xa,Ya)，D是形成位点1301的环境密度ED1，且a、b、c及e是常数。引用从函数F(X,Y,D)输出的结果来调整凸块生成参数。例如，从函数F(X,Y,D)输出的结果可为上文所提及的OPC的参数。应注意，形成位点的坐标可为笛卡儿(Cartesian)坐标或极坐标，且由函数F(X,Y,D)利用的坐标的类型不应受限于本揭露。
参考图14，其是绘示根据本揭露的一实施例的对应于裸片600上的各形成位点的OPC的参数的图式。如图14中所展示，在引用函数F(X,Y,D)之后获取与各形成位点的OPC的参数有关的图。对应于裸片600上的各形成位点的OPC图上的数字仅供说明，且其不应受限于本揭露。接着，根据图14中所展示的OPC图来使导电凸块同时形成于形成位点上。
在其它实施例中，函数F(X,Y,D)可书写为：
F(X,Y,D)＝a*X2+b*Y2+c*X+d*Y+e*X*Y+G(D,D')，
其中X及Y是形成位点1301的坐标(Xa,Ya)，D是形成位点1301的环境密度ED1，D'是形成位点1301周围的相邻形成位点的环境密度，G(*)是涉及密度D及D'的函数，且a、b、c、d、e是常数。所属领域的技术人员应易于在阅读上述实施例之后了解如何通过参考不同模型来调整凸块生成参数。此处为了简明而省略详细描述。
在一些实施例中，揭露一种半导体装置制造方法，其包含：通过根据与各形成位点相关的环境密度调整凸块生成参数来使多个导电凸块同时分别形成于多个形成位点上；其中所述多个导电凸块包含小于一值的凸块间高度均匀性，且所述环境密度由预定范围内各形成位点周围的相邻形成位点的数目确定。
在一些实施例中，揭露一种半导体装置制造方法，其包含：通过根据各形成位点的环境密度调整凸块生成参数来使多个凸块同时形成于多个形成位点上；其中当对应于第一形成位点的第一环境密度和对应于第二形成位点的第二环境密度之间的差值大于预定密度时，所述第二形成位点的横截面积大于所述第一形成位点的横截面积；其中所述第一环境密度由预定范围内所述第一形成位点周围的形成位点的数目确定且所述第二环境密度由所述预定范围内所述第二形成位点周围的形成位点的数目确定。
在一些实施例中，揭露一种半导体裸片，其包含：第一形成位点，其用于形成第一凸块；及第二形成位点，其用于形成第二凸块；其中所述第一形成位点的第一环境密度和所述第二形成位点的第二环境密度之间的差值大于预定密度，且所述第一环境密度由预定范围内所述第一形成位点周围的形成位点的数目确定且所述第二环境密度由所述预定范围内所述第二形成位点周围的形成位点的数目确定；且其中所述第二形成位点的横截面积和所述第一形成位点的横截面积之间的差值大于预定值。
符号说明
10 晶片
20 晶片
30 晶片
100 裸片
210 图案化掩模
310 图案化掩模
500 半导体装置制造方法
502 步骤
504 步骤
600 裸片
601 形成位点
602 形成位点
603 形成位点
604 形成位点
700 裸片
701 形成位点
702 形成位点
703 形成位点
704 形成位点
800 裸片
801 形成位点
802 形成位点
803 形成位点
804 形成位点
901至905 沟槽/开口
1200 半导体装置制造方法
1202 步骤
1301 形成位点
A1 横截面积
A2 横截面积
BCB 苯并环丁烯
bp01至bp12 导电凸块
CP1 铜柱
CP2 铜柱
ED1 环境密度
ED1' 环境密度
ED2 环境密度
ED2' 环境密度
ED3 环境密度
ED4 环境密度
ED5 环境密度
ED6 环境密度
ED7 环境密度
ED8 环境密度
H1 高度
H1' 高度
H2 高度
H2' 高度
OP1 开口
OP2 开口
OP3 开口
PAD1 金属垫
PAD2 金属垫
PR 光致抗蚀剂
RDL 重布层
ST01至ST12 形成位点
X 横截面积
Y 横截面积
Z1 区
Z1' 区
Z2 区
Z2' 区
Z3 区
Z4 区

Claims (14)

1.一种半导体装置制造方法，其包括：
在衬底上形成第一金属垫和第二金属垫；
将钝化层覆盖于所述第一金属垫和所述第二金属垫之上并暴露所述第一金属垫和所述第二金属垫的上表面；
将介电层涂布于所述钝化成层并暴露所述第一金属垫和所述第二金属垫的上表面；
以溅镀方式形成导电层于所述介电层之上并接触所述第一金属垫和所述第二金属垫；
涂布光敏材料层于所述导电层之上并通过光刻操作曝光所述光敏材料层以暴露所述导电层的部分；
涂布重布层于所述导电层的所述部分之上；
涂布光敏材料层于所述重布层之上并通过光刻操作曝光所述光敏材料层以在通过所述重布层分别连接到所述第一金属垫和所述第二金属垫的对应位置分别产生第一形成位点和第二形成位点，包括：
获取所述第一形成位点和所述第二形成位点的环境密度，其中所述环境密度指示在所述第一形成位点和所述第二形成位点周遭的预定范围内相邻预计形成位点的数量；
根据所述环境密度调整所述第一形成位点和所述第二形成位点的凸块生成参数，其中所述凸块生成参数是所述第一形成位点和所述第二形成位点的横截面积、在光刻操作中用于图案化所述光敏材料层以暴露所述第一形成位点和所述第二形成位点时使用的曝光能量，或者暴露所述第一形成位点和所述第二形成位点所对应的掩模的开口大小；
通过将所述凸块生成参数并入生成工艺中来使所述生成工艺执行于所述第一形成位点和所述第二形成位点的位置上以生成所述第一形成位点和所述第二形成位点；以及
使第一导电凸块和第二导电凸块同时分别形成于所述第一形成位点和所述第二形成位点上；
其中，所述第一导电凸块包括具有第一高度的第一铜柱，所述第二导电凸块包括具有第二高度的第二铜柱，所述第一高度与所述第二高度的高度差小于10um；
其中，当对应于第一形成位点的第一环境密度大于对应于第二形成位点的第二环境密度时，所述第二形成位点的横截面积大于所述第一形成位点的横截面积；
其中，所述第一环境密度由所述第一形成位点周围预定范围内的形成位点数量确定，所述第二环境密度由所述第二形成位点周围预定范围内的形成位点数量确定。
2.根据权利要求1所述的方法，其中使第一导电凸块和第二导电凸块同时分别形成于所述第一形成位点和所述第二形成位点上包括：在衬底上提供图案化掩模。
3.根据权利要求2所述的方法，其中所述图案化掩模包含第一沟槽和第二沟槽，且所述第一沟槽和所述第二沟槽暴露配置为所述第一形成位点和所述第二形成位点的面积的底面。
4.根据权利要求3所述的方法，其中使第一导电凸块和第二导电凸块同时分别形成于所述第一形成位点和所述第二形成位点上包括：将导电材料同时填充至所述第一沟槽和所述第二沟槽中。
5.根据权利要求3所述的方法，其中所述预定范围由所述光刻操作的单位曝光面积确定。
6.根据权利要求5所述的方法，其中所述凸块生成参数是在所述光刻操作中用于图案化所述光敏材料层时使用的曝光能量，且所述光刻操作包括：将所述光敏材料层安置于所述衬底上且图案化所述光敏材料层以形成所述图案化掩模。
7.根据权利要求5所述的方法，其中所述单位曝光面积是四边形面积。
8.根据权利要求5所述的方法，其中所述凸块生成参数是用于所述光刻操作中的所述掩模的所述开口大小。
9.根据权利要求1所述的方法，其进一步包括：分析对应于所述第一导电凸块和所述第二导电凸块的布局以获得所述第一形成位点和所述第二形成位点的所述环境密度。
10.根据权利要求9所述的方法，其中分析对应于所述第一导电凸块和所述第二导电凸块的布局以获得所述第一形成位点和所述第二形成位点的所述环境密度包括：从所述布局提取对应于所述预定范围的面积；及计算与所述面积中的形成位点的各者相关的所述环境密度。
11.根据权利要求1所述的方法，其中根据所述第一形成位点和所述第二形成位点的所述环境密度来调整凸块生成参数包含：
获得对应于所述第一形成位点和所述第二形成位点的坐标；及
通过参考涉及所述第一形成位点和所述第二形成位点的所述坐标及所述环境密度的模型来调整所述凸块生成参数。
12.根据权利要求9所述的方法，其中所述预定范围是基于所述布局的圆形面积。
13.根据权利要求9所述的方法，其中所述布局指示所述第一导电凸块和所述第二导电凸块散布于不同的分离区域，所述预定范围是各个分离区域的面积。
14.一种半导体装置制造方法，其包括：
在衬底上形成第一金属垫和第二金属垫；
将钝化层覆盖于所述第一金属垫和所述第二金属垫之上并暴露所述第一金属垫和所述第二金属垫的上表面；
以溅镀方式形成导电层于所述钝化层之上并接触所述第一金属垫和所述第二金属垫；
涂布光敏材料层于所述导电层之上；
通过光刻操作曝光所述光敏材料层以在所述第一金属垫和所述第二金属垫的对应位置分别产生第一形成位点和第二形成位点，包括：
根据所述第一形成位点的环境密度和所述第二形成位点的环境密度来分别调整凸块生成参数来使凸块同时形成于所述第一形成位点和所述第二形成位点上；
其中，所述第一形成位点上的凸块形成第一铜柱，所述第一铜柱具有第一高度，所述第二形成位点上的凸块形成第二铜柱，所述第二铜柱具有第二高度，所述第一高度与所述第二高度的高度差小于10um；
其中当对应于第一形成位点的第一环境密度大于对应于第二形成位点的第二环境密度时，所述第二形成位点的横截面积大于所述第一形成位点的横截面积；
其中所述第一环境密度由预定范围内所述第一形成位点周围的形成位点的数目确定且所述第二环境密度由所述预定范围内所述第二形成位点周围的形成位点的数目确定。
CN201910639113.9A 2018-07-16 2019-07-16 半导体装置制造方法及相关半导体裸片 Active CN110729198B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201862698614P 2018-07-16 2018-07-16
US62/698,614 2018-07-16
US16/353,425 US11469198B2 (en) 2018-07-16 2019-03-14 Semiconductor device manufacturing method and associated semiconductor die
US16/353,425 2019-03-14

Publications (2)

Publication Number Publication Date
CN110729198A CN110729198A (zh) 2020-01-24
CN110729198B true CN110729198B (zh) 2023-07-18

Family

ID=69139717

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910639113.9A Active CN110729198B (zh) 2018-07-16 2019-07-16 半导体装置制造方法及相关半导体裸片

Country Status (3)

Country Link
US (3) US11469198B2 (zh)
CN (1) CN110729198B (zh)
TW (1) TWI711142B (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112420534B (zh) * 2020-11-27 2021-11-23 上海易卜半导体有限公司 形成半导体封装件的方法及半导体封装件

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103123915A (zh) * 2011-11-17 2013-05-29 台湾积体电路制造股份有限公司 调节封装组件的连接器的尺寸
CN103137587A (zh) * 2011-11-30 2013-06-05 台湾积体电路制造股份有限公司 用于底部填充控制的平坦化凸块
US20150262949A1 (en) * 2014-03-14 2015-09-17 Lsi Corporation Method for Fabricating Equal Height Metal Pillars of Different Diameters
CN102214627B (zh) * 2010-04-07 2015-12-16 马克西姆综合产品公司 具有凸块组合件的晶片级芯片尺寸封装装置
US9905527B1 (en) * 2016-12-15 2018-02-27 Micron Technology, Inc. Uniform electrochemical plating of metal onto arrays of pillars having different lateral densities and related technology

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI313507B (en) * 2002-10-25 2009-08-11 Megica Corporatio Method for assembling chips
JP4746770B2 (ja) * 2001-06-19 2011-08-10 ルネサスエレクトロニクス株式会社 半導体装置
TW498530B (en) 2001-08-29 2002-08-11 Via Tech Inc Flip-chip pad and redistribution layer arrangement
US6979896B2 (en) 2001-10-30 2005-12-27 Intel Corporation Power gridding scheme
US9048233B2 (en) 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
KR20120060960A (ko) * 2010-09-20 2012-06-12 삼성전자주식회사 반도체 패키지, 전자 장치 및 이를 채택하는 전자 시스템
US9064879B2 (en) 2010-10-14 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures using a die attach film
US8797057B2 (en) 2011-02-11 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Testing of semiconductor chips with microbumps
JP5286382B2 (ja) * 2011-04-11 2013-09-11 株式会社日立製作所 半導体装置およびその製造方法
US9000584B2 (en) 2011-12-28 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor device with a molding compound and a method of forming the same
US20130193570A1 (en) * 2012-02-01 2013-08-01 Chipbond Technology Corporation Bumping process and structure thereof
US9111949B2 (en) 2012-04-09 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus of wafer level package for heterogeneous integration technology
US9263511B2 (en) 2013-02-11 2016-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package with metal-insulator-metal capacitor and method of manufacturing the same
US9048222B2 (en) 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices
JP2014179433A (ja) 2013-03-14 2014-09-25 Toshiba Corp 半導体装置
US9368460B2 (en) 2013-03-15 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and method for forming same
US9281254B2 (en) 2014-02-13 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuit package
US9496189B2 (en) 2014-06-13 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor devices and methods of forming same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102214627B (zh) * 2010-04-07 2015-12-16 马克西姆综合产品公司 具有凸块组合件的晶片级芯片尺寸封装装置
CN103123915A (zh) * 2011-11-17 2013-05-29 台湾积体电路制造股份有限公司 调节封装组件的连接器的尺寸
CN103137587A (zh) * 2011-11-30 2013-06-05 台湾积体电路制造股份有限公司 用于底部填充控制的平坦化凸块
US20150262949A1 (en) * 2014-03-14 2015-09-17 Lsi Corporation Method for Fabricating Equal Height Metal Pillars of Different Diameters
US9905527B1 (en) * 2016-12-15 2018-02-27 Micron Technology, Inc. Uniform electrochemical plating of metal onto arrays of pillars having different lateral densities and related technology

Also Published As

Publication number Publication date
CN110729198A (zh) 2020-01-24
TW202006912A (zh) 2020-02-01
US11469198B2 (en) 2022-10-11
US20200020655A1 (en) 2020-01-16
US12021050B2 (en) 2024-06-25
TWI711142B (zh) 2020-11-21
US20240312939A1 (en) 2024-09-19
US20220367396A1 (en) 2022-11-17

Similar Documents

Publication Publication Date Title
US20200020666A1 (en) Packaging Methods for Semiconductor Devices, Packaged Semiconductor Devices, and Design Methods Thereof
CN105448752B (zh) 埋入硅基板扇出型封装方法
US9595496B2 (en) Integrated device package comprising silicon bridge in an encapsulation layer
US9082870B2 (en) Methods and apparatus of packaging semiconductor devices
TWI402939B (zh) 包含一矽貫通電極之積體電路結構及形成該積體電路結構之方法
US10937688B2 (en) Semiconductor package and method of fabricating semiconductor package
CN104471680A (zh) 垫上柱体互连结构、半导体裸片及包含所述互连结构的裸片组合件及相关方法
US20240312939A1 (en) Semiconductor device
KR20090047862A (ko) 웨이퍼 레벨 패키지 제조방법
KR20190003294A (ko) 패키지 내의 격리막으로서의 릴리스막
CN112530815A (zh) 半导体装置制造中的移位控制方法
US10157803B2 (en) Semiconductor device and method of unit specific progressive alignment
TWI656604B (zh) Semiconductor rewiring method
KR20210075558A (ko) 반도체 패키지의 제조 방법
EP4095891A1 (en) Pre-resist island forming via method and apparatus
US11652085B2 (en) Fan-out wafer-level packaging structure and method packaging the same
US11670541B2 (en) Methods of manufacturing semiconductor device using phase shift mask
US20240113089A1 (en) Semiconductor package and manufacturing method thereof
US20230067826A1 (en) Semiconductor package structure and method for forming the same
US12125741B2 (en) Semiconductor package and method of fabricating semiconductor package

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant