TWI656604B - Semiconductor rewiring method - Google Patents
Semiconductor rewiring method Download PDFInfo
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- TWI656604B TWI656604B TW106133723A TW106133723A TWI656604B TW I656604 B TWI656604 B TW I656604B TW 106133723 A TW106133723 A TW 106133723A TW 106133723 A TW106133723 A TW 106133723A TW I656604 B TWI656604 B TW I656604B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- 238000001259 photo etching Methods 0.000 claims abstract description 58
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
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- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
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Abstract
一種半導體重佈線方法,計算出載體上每個電性連接點的偏移值後,先使用無遮罩光蝕刻方式進行偏移值修正,在電性連接點上形成重佈線結構,然後藉由有遮罩光蝕刻方式對載體進行單一化處理,以在重佈線結構上方形成佈線層和/或形成焊球。這樣將無遮罩光蝕刻和有遮罩光蝕刻相互結合,相對於單純使用無遮罩光蝕刻方式,能够提高效率,節省時間。
Description
本發明有關於半導體領域,特別有關於一種半導體重佈線方法。
隨著積體電路技術的不斷發展,電子產品越來越向小型化、智慧化、高性能以及高可靠性方向發展。而積體電路封裝不僅直接影響著積體電路性能,而且還制約著整個電子系統的小型化、低成本和可靠性。在積體電路晶片尺寸逐步縮小,集成高度不斷提高的情況下,對積體電路封裝提出越來越高的要求。
扇出型晶圓封裝(Fan Out Wafer Level Package,可簡寫為FOWLP)是一種如圖1所示將晶片晶圓切割成獨立晶片2後重新排列在新載體1上進行晶圓級封裝的封裝技藝。藉由傳統的晶圓級封裝技藝,可以在新載體1上形成新的封裝體3(如圖2所示)。其中單顆封裝體的封裝結構示意圖如圖4所示,圖4中,晶片2嵌入在封裝體3內,針對晶片2的焊盤4,藉由光蝕刻、CVD、PVD、蝕刻和電鍍等技藝形成由下絕緣層7、金屬層5和上絕緣層6組成的重新再佈線結構,在新的I/O埠(即電性連接點,從金屬層5引出)上形成焊球8均勻的分佈在新封裝體3上,若干個新封裝體3排列在新載體1上形成圖2所示的結構。
典型的扇出型晶圓封裝重佈線技藝方法,是採用光蝕 刻技藝定義上絕緣層6、金屬層5和下絕緣層7的圖形和位置,再藉由CVD、PVD和電鍍等技藝生成絕緣層和金屬層。主流的光蝕刻技術(即有遮罩光蝕刻)需要先按照目標圖形的一定比例製造遮罩,藉由光學投影的方式使晶片上塗敷的光敏膠部分區域發生反應定義圖形和位置。由於滿足大規模量產的產率的晶片重新排列設備的晶片定位精度僅為7μm~10μm(而上述光蝕刻技藝所要求的定位精度為小於5μm),使得光蝕刻良率不高,難以大規模量產。
另外還有一種無遮罩光蝕刻技術,其原理是藉由光調製器取代遮罩,藉由即時控制調製出需要的圖形,採用無遮罩光蝕刻時結構如圖3所示,這種方式能夠解決晶片重新排列定位精度不準的問題,但是這種方式需要將整片新載體1上的所有光蝕刻區域都進行擬合計算,所以每次光蝕刻的產率極低(每次光蝕刻需要2~3小時),不能滿足目前扇出型晶圓封裝技藝的生產節拍(5~10分鐘)。
為解決上述問題,本發明提出一種半導體重佈線方法,使用無遮罩曝光方式和有遮罩曝光方式相互配合,綜合兩者的優點,相對於單純使用無遮罩曝光方式能够節省時間、提高效率,相對於單純使用有遮罩曝光方式能够提高光蝕刻精度。
為達到上述目的,本發明提供一種半導體重佈線方法,包括以下步驟:步驟1:設置承載多個半導體元件的載體,該多個半導體元件中的每一個具有多個電性連接點;步驟2:測量每個電性連接點相對於該載體的位置,將所測得 的位置與該電性連接點相對於該載體的標準位置比較,獲得每個電性連接點的偏移值;步驟3:根據得到的偏移值,藉由無遮罩光蝕刻的方式,在每個電性連接點上形成重佈線結構,以修正該偏移值;步驟4:藉由有遮罩曝光方式,對該載體進行單一化處理,以在重佈線結構上方形成佈線層和/或形成焊球。
較佳的,步驟3包括:沉積第一介質層;在第一介質層上塗覆第一光蝕刻膠層;根據步驟2得到的偏移值,藉由無遮罩光蝕刻的方式在第一光蝕刻膠層中形成多個第一光蝕刻膠圖形,其中,每個第一光蝕刻膠圖形與相應的一個電性連接點對準;以第一光蝕刻膠層為遮罩,蝕刻第一介質層,在第一介質層中形成多個第一開口,每個第一開口暴露出相應的電性連接點;去除第一光蝕刻膠層;塗覆第二光蝕刻膠層;根據該偏移值,藉由無遮罩光蝕刻的方式在第二光蝕刻膠層中形成多個第二光蝕刻膠圖形,以定義出用於形成該重佈線結構的區域;在該區域中填充金屬,以形成該重佈線結構。
較佳的,步驟4包括:沉積第二介質層;在第二介質層上塗覆第三光蝕刻膠層;藉由有遮罩曝光方式,在第三光蝕刻膠層中形成多個第三光蝕 刻膠圖形,每個第三光蝕刻膠圖形對應於一個植球墊區域;以第三光蝕刻膠層為遮罩,蝕刻第二介質層,在第二介質層中形成多個第二開口,每個第二開口中暴露出部分重佈線結構;在所暴露出的部分重佈線結構上形成焊球。
較佳的,該重佈線結構的區域被定義為使得步驟4中的該第二開口中只有重佈線結構被暴露。
較佳的,該半導體元件為晶片。
本發明還提供一種半導體重佈線方法,包括以下步驟:設置承載多個半導體元件的載體,該多個半導體元件中的每一個具有多個電性連接點;測量每個電性連接點相對於該載體的位置;將所測得的位置與該電性連接點相對於該載體的標準位置比較,獲得每個電性連接點的偏移值;將該偏移值與預設的一臨界範圍進行比較,根據比較結果進行光蝕刻,在該電性連接點上形成重佈線結構,其中,形成重佈線結構包括:對偏移值小於該臨界範圍的電性連接點,使用有遮罩曝光方式;對偏移值大於該臨界範圍的電性連接點,使用無遮罩曝光方式;對偏移值位於該臨界範圍內的電性連接點,選擇圍繞該電性連接點的其它電性連接點使用得更多的曝光方式;藉由有遮罩曝光方式,對該載體進行單一化處理,以在重佈 線結構上方形成佈線層和/或形成焊球。
較佳的,選取兩條相互垂直且同時平行於該載體表面的直線方向作為X和Y方向,選取垂直於該載體表面的直線方向作為Z方向,形成XYZ三維座標系,該偏移值為X偏移值、Y偏移值和RZ偏移值的至少其一,其中RZ為圍繞Z軸旋轉的方向。
較佳的,形成重佈線結構包括:首先對偏移值大於該臨界範圍的電性連接點,使用無遮罩曝光方式曝光;然後對偏移值小於該臨界範圍的電性連接點,使用有遮罩曝光方式曝光,曝光時對已經使用無遮罩方式曝光之處予以屏蔽;其中對偏移值位於該臨界範圍內的電性連接點,計算圍繞目前區域的相鄰區域的個數,在這些相鄰區域中任意一種曝光方式被選擇的次數若大於相鄰區域個數的一半,则目前區域選擇該曝光方式曝光。
較佳的,形成重佈線結構包括:首先對偏移值小於該臨界範圍的電性連接點,使用有遮罩曝光方式曝光;然後對偏移值大於該臨界範圍的電性連接點,使用無遮罩曝光方式曝光,曝光時對已經使用有遮罩方式曝光之處予以屏蔽;其中對偏移值位於該臨界範圍內的電性連接點,計算圍繞目前區域的相鄰區域的個數,在這些相鄰區域中任意一種曝光方式被選擇的次數若大於相鄰區域個數的一半,则目前區域選擇該曝光方式曝光。
較佳的,該臨界範圍為5μm~7μm。
較佳的,該半導體元件為晶片。
與現有技術相比,本發明的有益效果是:本發明提供一種半導體重佈線方法,計算出載體上每個電性連接點的偏移值後,先使用無遮罩光蝕刻方式進行偏移值修正,在電性連接點上形成重佈線結構,然後藉由有遮罩光蝕刻方式對載體進行單一化處理(無需考慮偏移值),以在重佈線結構上方形成佈線層和/或形成焊球。這樣將無遮罩光蝕刻和有遮罩光蝕刻相互結合,相對於單純使用無遮罩光蝕刻方式,能够提高效率,節省時間。
本發明還提供一種半導體重佈線方法,在計算出載體上每個電性連接點的偏移值後,並對偏移值設定臨界範圍,對偏移值小於該臨界範圍的電性連接點,使用有遮罩曝光方式;對偏移值大於該臨界範圍的電性連接點,選擇無遮罩曝光方式;其中對偏移值位於該臨界範圍內的電性連接點,計算圍繞目前區域的相鄰區域的個數,在這些相鄰區域中任意一種曝光方式被選擇的次數若大於相鄰區域個數的一半,則目前區域選擇該曝光方式曝光,這樣具有針對性地選擇曝光方式,對於精度要求高之處選擇無遮罩曝光,對於精度要求低之處選擇有遮罩曝光,將有遮罩曝光與無遮罩曝光相互配合,從而提高技藝效率,節省時間,並同時保證精度。
1‧‧‧新載體
2‧‧‧晶片
3‧‧‧封裝體
4‧‧‧焊盤
5‧‧‧金屬層
6‧‧‧上絕緣層
7‧‧‧下絕緣層
8‧‧‧焊球
100‧‧‧載體
210、220、230‧‧‧晶片
211、212、221、222、231、232‧‧‧電性連接點
241‧‧‧修正電性連接點
310、320、330‧‧‧保護層
311‧‧‧開口
410、420、430‧‧‧光蝕刻膠
411、431‧‧‧光蝕刻膠圖形
421‧‧‧金屬佈線圖形
500‧‧‧金屬線路
600‧‧‧植球墊
700‧‧‧焊球
LL‧‧‧晶片中心軸
UU‧‧‧封裝體中心軸
圖1和圖2皆為現有技術中扇出型晶圓封裝的結構示意圖;圖3為現有技術中使用無遮罩光蝕刻技術的扇出型晶圓封裝的結構示意圖; 圖4為現有技術中單顆封裝體的封裝結構示意圖;圖5為本發明實施例一中晶片在載體上形成偏移的示意圖;圖6為本發明實施例一的方法流程圖;圖7為本發明實施例一中在晶片上沉積保護層後示意圖;圖8為本發明實施例一中在保護層上沉積光蝕刻膠後示意圖;圖9為本發明實施例一中對光蝕刻膠曝光顯影後示意圖;圖10為本發明實施例一中對保護層曝光顯影後示意圖;圖11為本發明實施例一中對圖10結構進行沉積光蝕刻膠後示意圖;圖12為本發明實施例一中對光蝕刻膠進行曝光顯影後示意圖;圖13為本發明實施例一中對圖12結構沉積金屬層後示意圖;圖14為本發明實施例一中對圖13結構沉積保護層後示意圖;圖15為本發明實施例一中對圖14結構沉積光蝕刻膠後示意圖;圖16為本發明實施例一中對圖15結構對光蝕刻膠曝光顯影後示意圖;圖17為本發明實施例一中將植球墊暴露示意圖;圖18為本發明實施例一中植球示意圖;圖19為本發明實施例二的方法流程圖;圖20為本發明實施例二在晶片上沉積保護層後示意圖;圖21為本發明實施例二在圖20結構上沉積光蝕刻膠後示意圖;圖22為本發明實施例二對保護層光蝕刻將電性連接點暴露示意圖;圖23為本發明實施例二在圖22結構上沉積金屬種子層形成導通線路示意圖;圖24為本發明實施例二在圖23結構上沉積保護層後示意圖; 圖25為本發明實施例二在將導通線路暴露示意圖;圖26為本發明實施例二形成植球墊示意圖;圖27為本發明實施例二在植球墊上沉積保護層示意圖;圖28為本發明實施例二對圖27結構光蝕刻並形成焊球後示意圖。
為使本發明的上述目的、特徵和優點能夠更加明顯易懂,下面結合附圖對本發明的具體實施方式做詳細的說明。
本發明實施例一提供一種扇出型晶圓封裝方法,請參照圖5,在載體100上完成晶片重新排列,在圖5中繪視水平橫向排列的三個晶片210、220和230,每個晶片上各自設置兩個I/O埠,亦即設置兩個電性連接點,即形成六個電性連接點211、212、221、222、231、232。
以水平橫向為X軸,以垂直方向為Z軸,以垂直於XZ平面方向為Y軸建立XYZ三維座標系。
在載體100上排列若干個晶片,圖5中僅示意性畫出三個晶片210、220和230,根據後續植球技藝的參數,對每個晶片上的電性連接點以及植球墊定義其座標值的標準值。
從圖5中可以看出,由於前道技藝原因,導致排列在載體100上的三個晶片產生不同程度的偏移,尤其是其中晶片210和晶片230的晶片中心軸LL相對於每個封裝體中心軸UU產生的偏移較大,偏移間距可達7μm,從而每個電性連接點的實際座標值 相對於標準值必定會產生偏移。
因此在進行植球技藝之前,必須對三個晶片上的電性連接點進行位置修正,得到相對於標準值無偏移的植球墊,才能進行精確地植球。位置修正的方法就是藉由光蝕刻重新佈線,將電性連接點連通至位置修正後的植球墊上。
如圖6所示,具體實施的技藝步驟如下:步驟1.01:首先對載體100上已經完成重新排列的晶片逐步掃描,形成晶片位置佈局(mapping)圖,請參照圖7,在完成晶片重新排列的載體100的晶片裝置面沉積保護層材料,形成保護層310;其中,保護層材料可以選擇介質材料或者有機材料。保護層310的沉積技藝可以採用各種氣相沉積、氧化等方法。
步驟1.02:在步驟1.01形成的保護層310上沉積光蝕刻膠410,請參照圖8;步驟1.03:採用具有無遮罩光蝕刻功能設備,在六個電性連接點211、212、221、222、231、232對應的區域進行曝光技藝,藉由曝光、顯影、堅膜等光蝕刻技藝定義要製作重新佈線的電性連接點對應的區域,如圖9所示;其中,無遮罩光蝕刻設備可根據預先輸入的晶片位置佈局圖和光蝕刻定義圖形在載體100上藉由與晶片的對準,找出對應的光蝕刻區域,在完成步驟1.03之後,光蝕刻膠410中形成與電性連接點一一對準的光蝕刻膠圖形411。
步驟1.04:去除步驟1.03中光蝕刻技藝定義出的在電性連接點區域覆蓋的保護層材料,如圖10所示;其中,保護層材料去除方式可藉由濕式腐蝕或乾式蝕刻等方式 來實現,在完成步驟1.04之後,保護層310中形成多個開口311,每個開口311與一個電性連接點對應且開口底部暴露出該電性連接點,以便後續藉由金屬佈線將電性連接點引出。
步驟1.05:在步驟1.04形成的結構上沉積光蝕刻膠420,如圖11所示;步驟1.06:採用具有無遮罩光蝕刻功能設備,藉由曝光、顯影、堅膜等光蝕刻技藝定義製作金屬重新佈線區域。藉由金屬重新佈線實現與晶片的電性連接點互連,其中金屬重佈線的金屬線路位置藉由載體100上的基準統一定義,並根據晶片的位置偏移進行微調和補償,具體的,可基於無偏差的標準金屬佈線圖形,結合考慮各晶片的位置偏移,形成修正後的金屬佈線圖形421,如圖12所示,舉例而言,當晶片中心軸相對於封裝體中心軸左偏一定偏移量時,可以在標準金屬佈線圖形的基礎上將圖形向右延伸和/或向右移動一定距離以形成修正後的金屬佈線圖形,該延伸和/或移動距離例如可以大於等於該偏移量;當晶片中心軸相對於封裝體中心軸右偏時,則可以在標準金屬佈線圖形的基礎上將圖形向左延伸和/或向左移動一定距離以形成修正後的金屬佈線圖形;此外,該修正後的金屬佈線圖形421應當暴露出步驟1.04中形成的開口311;容易理解的是,步驟1.06中所形成的各金屬佈線圖形的形狀、大小、位置中的一種或多種是可以互不相同的,即該各金屬佈線圖形在整個載體100上的分佈不具有規律性;步驟1.07:在步驟1.06形成的結構上濺射金屬種子層,再藉由化學鍍、電鍍等方法,形成重新佈線的金屬線路500,如圖13所示,該金屬線路500用於在後續技藝中形成用於植球的植球墊或者進一 步連接至上層金屬;其中,生長金屬材料可以是銅、鋁、鎢等金屬,並不限於所述的三種金屬材料。
至此,藉由形成金屬線路500實現晶片上的電性連接點的位置修正。接下來只需藉由單一化處理完成後續的佈線和/或植球技藝。此處的單一化處理也可以理解為統一化處理,即不需要考慮單個晶片在載體100上的位置偏移,而直接基於標準的無偏移的位置對各個晶片進行統一處理。
下面以藉由單一化處理直接進行植球技藝為例加以說明。
步驟1.08:去除殘餘光蝕刻膠,然後沉積保護層320,如圖14所示;其中,保護層320的材料可以選擇介質材料或者有機材料,保護層320的沉積技藝可以採用各種氣相沉積、氧化或濺射等方法。
步驟1.09:在步驟1.08形成的結構上沉積光蝕刻膠430,如圖15所示;步驟1.10:採用有遮罩光蝕刻功能設備,以載體100為統一基準,定義相對於標準值無偏移的植球墊600的位置和圖形尺寸,形成與金屬線路500一一對應的光蝕刻膠圖形431,如圖16所示,容易理解的是,由於採用單一化處理方式,步驟1.10所形成的光蝕刻膠圖形431在整個載體100上的分佈是具有規律性的;步驟1.11:去除光蝕刻技藝定義出的植球墊600區域覆蓋的保護層材料320以暴露出下方的部分金屬線路500,然後去除光蝕刻膠430,如圖17所示,所暴露出的部分金屬線路形成植球墊600; 其中,保護層材料去除方式可藉由濕式腐蝕或乾式蝕刻等方式來實現。
步驟1.12:完成焊球700製作技藝,如圖18所示。
本實施例可將無遮罩光蝕刻和有遮罩光蝕刻相互結合,相對於單純使用無遮罩光蝕刻方式,能夠提高效率,節省時間。
本發明實施例二提供一種扇出晶圓封裝方法,對於載體100的晶片位置數量較少的情況,可首先對載體100上的經過重新排列的晶片進行位置掃描,形成晶片位置佈局圖,並且對於偏移值設定臨界範圍,臨界範圍可根據具體工況設定,本實施例中以偏移5μm~7μm為臨界基準。如當晶片位置偏移值大於臨界範圍的區域採用無遮罩曝光然後再整片採用有遮罩曝光的光蝕刻方式,藉由這種方式可大大提高扇出型晶圓封裝的產率。
或者在曝光時,對於偏移值大於臨界範圍的區域採用無遮罩曝光,對於偏移值小於臨界範圍的區域採用有遮罩曝光,對於偏移值位於臨界範圍內的區域,選擇圍繞該區域的其它區域中被選擇次數最多的曝光方式曝光。在曝光前的光蝕刻系統中,所有區域的曝光方式都已經事先定義好,則偏移值位於臨界範圍內的區域若選擇有遮罩曝光方式,則與偏移值小於臨界範圍的區域一起進行有遮罩曝光;若偏移值位於臨界範圍內的區域選擇無遮罩曝光方式,則與偏移值大於臨界範圍內的區域一起進行無遮罩曝光。
其中偏移值大於臨界範圍的區域和小於臨界範圍的區域的曝光順序並不固定,如可先對偏移值大於臨界範圍的區域以 及臨界範圍內需要選擇無遮罩曝光方式的區域採用無遮罩方式曝光,然後對於剩下的區域採用有遮罩曝光方式曝光,曝光的同時對於已經曝光過的區域予以屏蔽處理;或者也可先對偏移值小於臨界範圍的區域以及臨界範圍內需要選擇有遮罩曝光方式的區域採用有遮罩曝光方式曝光,對於剩下的區域採用無遮罩曝光方式曝光,曝光的同時對於已經曝光過的區域予以屏蔽處理。
具體方法如圖19所示,具體步驟如下:步驟2.01:對載體100的晶片佈局進行位置掃描,形成晶片位置佈局圖;步驟2.02:在完成晶片重新排列的載體100的晶片裝置面沉積保護層材料,形成保護層310,如圖20所示;其中,保護層310的材料可以選擇介質材料或者有機材料。保護層310的沉積技藝可以採用各種氣相沉積、氧化等方法。
步驟2.03:在步驟2.02形成的結構上沉積光蝕刻膠410,如圖21所示;步驟2.04:以水平橫向為X軸,以垂直方向為Z軸,以垂直於XZ平面方向為Y軸建立XYZ三維座標系。偏移值分為X偏移值、Y偏移值和RZ偏移值,RZ為圍繞Z軸旋轉的方向,對電性連接點的上述任意一種偏移值大於臨界範圍的區域,採用無遮罩光蝕刻功能設備進行曝光技藝,對電性連接點的上述任意一種偏移值小於臨界範圍的區域,採用有遮罩光蝕刻功能設備進行曝光技藝,對於偏移值位於臨界範圍內的區域,選擇圍繞該區域的其它區域中被選擇次數最多的曝光方式曝光,然後去除電性連接點所對應區域的保護層310,如圖22所示; 其中無遮罩曝光和有遮罩曝光的順序並不限定,如可先對偏移值大於臨界範圍的區域以及臨界範圍內需要選擇無遮罩曝光方式的區域採用無遮罩方式曝光,然後對於剩下的區域採用有遮罩曝光方式曝光,曝光的同時對於已經曝光過的區域予以屏蔽處理;或者也可先對偏移值小於臨界範圍的區域以及臨界範圍內需要選擇有遮罩曝光方式的區域採用有遮罩曝光方式曝光,對於剩下的區域採用無遮罩曝光方式曝光,曝光的同時對於已經曝光過的區域予以屏蔽處理。
其中,保護層材料去除方式可藉由濕式腐蝕或乾式蝕刻等方式來實現。
其中,對於偏移值位於臨界範圍內的區域,選擇圍繞該區域的其它區域中被選擇次數最多的曝光方式曝光包括:計算圍繞目前區域的相鄰區域的個數,在這些相鄰區域中任意一種曝光方式被選擇的次數若大於相鄰區域個數的一半,則目前區域選擇該曝光方式曝光。例如偏移值位於臨界範圍內的某一區域周圍有8個鄰近區域,如果這8個鄰近區域中有半數以上的區域採用無遮罩曝光方式,則該區域也採用無遮罩曝光方式;如果這8個鄰近區域中有半數以上的區域採用有遮罩曝光方式,則該區域也採用有遮罩曝光方式;如果這8個鄰近區域中有4個採用有遮罩曝光方式、另外4個採用無遮罩曝光方式,則該區域可以採用有遮罩曝光方式和無遮罩曝光方式中的任一種。
步驟2.05:藉由與實施例一中的步驟1.05-1.06類似的方法用光蝕刻膠定義出修正電性連接點的區域,並藉由濺射金屬種子層,再藉由化學鍍、電鍍等方法,形成修正電性連接點241, 如圖23所示,從圖23可看出,各修正電性連接點241與對應的封裝體之間的相對位置是基本統一的,而與對應的晶片的中軸線的相對位置是不統一的,由此,藉由修正電性連接點241的位置補償,修正晶片位置偏移,此外,各修正電性連接點241均連接至對應的電性連接點;至此,藉由修正電性連接點241實現晶片上的電性連接點的位置補償。接下來只需藉由單一化處理完成後續的佈線和/或植球技藝。此處的單一化處理也可以理解為統一化處理,即不需要考慮單個晶片在載體100上的位置偏移,而直接基於標準的無偏移的位置對各個晶片進行統一處理。
下面以藉由單一化處理依次進行佈線和植球技藝為例加以說明。
步驟2.06:在步驟2.05形成的結構上沉積保護層320,如圖24所示;步驟2.07:採用有遮罩光蝕刻功能設備,藉由光蝕刻技藝定義出修正電性連接點241所在的區域,並去除該區域上覆蓋的保護層320,如圖25所示;步驟2.08:採用有遮罩光蝕刻功能設備藉由曝光技藝定義製作上層金屬佈線區域。濺射金屬種子層,再藉由化學鍍、電鍍等方法,形成上層金屬線路,如圖26所示,容易理解的是,由於採用單一化處理方式,步驟2.08所形成的上層金屬線路在整個載體100上的分佈是具有規律性的;其中,生長金屬材料可以是銅、鋁、鎢等金屬,並不限於所述的三種金屬材料。
步驟2.09:在步驟2.08形成的結構上沉積保護層330,如圖27所示;其中,保護層材料可以選擇介質材料或者有機材料,保護層330的沉積技藝可以採用各種氣相沉積、氧化或濺射等方法。
步驟2.10:採用有遮罩光蝕刻功能設備,定義無偏移的植球墊600的位置和圖形尺寸,去除植球墊600對應的區域上覆蓋的保護層330,所暴露出的上層金屬線路部分即為植球墊600,最後在植球墊600上完成焊球700製作技藝,如圖28所示。
本實施例對於具有不同偏移值的不同區域針對性地採用不同的曝光方式,更好地將無遮罩光蝕刻和有遮罩光蝕刻相互結合,提高光蝕刻效率,節省時間。
本發明對上述實施例進行描述,但本發明不僅限於上述實施例,如載體100可以承載晶片以外的其它具有電性連接點的半導體裝置。顯然本領域的技術人員可以對發明進行各種改動和變型而不脫離本發明的精神和範圍。這樣,倘若本發明的這些修改和變型屬於本發明請求項及其等同技術的範圍之內,則本發明也意圖包括這些改動和變型在內。
Claims (11)
- 一種半導體重佈線方法,其包括以下步驟:步驟1:設置承載多個半導體元件的一載體,該多個半導體元件中的每一個具有多個電性連接點;步驟2:測量每個電性連接點相對於該載體的位置,將所測得的位置與該多個電性連接點相對於該載體的一標準位置比較,獲得每個電性連接點的一偏移值;步驟3:根據得到的該偏移值,藉由無遮罩光蝕刻的方式,在每個電性連接點上形成一重佈線結構,以修正該偏移值;步驟4:藉由有遮罩曝光方式,對該載體進行單一化處理,以在該重佈線結構上方形成一佈線層和/或形成一焊球。
- 如請求項1之半導體重佈線方法,其中,步驟3包括:沉積一第一介質層;在該第一介質層上塗覆一第一光蝕刻膠層;根據步驟2得到的該偏移值,藉由無遮罩光蝕刻的方式在該第一光蝕刻膠層中形成多個第一光蝕刻膠圖形,其中,每個第一光蝕刻膠圖形與相應的一個電性連接點對準;以該第一光蝕刻膠層為遮罩,蝕刻該第一介質層,在該第一介質層中形成多個第一開口,每個第一開口暴露出相應的每個電性連接點;去除該第一光蝕刻膠層;塗覆一第二光蝕刻膠層;根據該偏移值,藉由無遮罩光蝕刻的方式在該第二光蝕刻膠層中形成多個第二光蝕刻膠圖形,以定義出用於形成該重佈線結構的一 區域;在該區域中填充金屬,以形成該重佈線結構。
- 如請求項2之半導體重佈線方法,其中,步驟4包括:沉積一第二介質層;在該第二介質層上塗覆一第三光蝕刻膠層;藉由有遮罩曝光方式,在該第三光蝕刻膠層中形成多個第三光蝕刻膠圖形,每個第三光蝕刻膠圖形對應於一個植球墊區域;以該第三光蝕刻膠層為遮罩,蝕刻該第二介質層,在該第二介質層中形成多個第二開口,每個第二開口中暴露出部分該重佈線結構;在所暴露出的該部分重佈線結構上形成該焊球。
- 如請求項3之半導體重佈線方法,其中,該重佈線結構的該區域被定義為使得步驟4中的該多個第二開口中只有該重佈線結構被暴露。
- 如請求項1之半導體重佈線方法,其中,該半導體元件為一晶片。
- 一種半導體重佈線方法,其包括以下步驟:設置承載多個半導體元件的一載體,該多個半導體元件中的每一個具有多個電性連接點;測量每個電性連接點相對於該載體的位置;將所測得的位置與該多個電性連接點相對於該載體的一標準位置比較,獲得每個電性連接點的一偏移值;將該偏移值與預設的一臨界範圍進行比較,根據比較結果進行光蝕刻,在該多個電性連接點上形成一重佈線結構,其中,形成該重 佈線結構包括:對該偏移值小於該臨界範圍的該多個電性連接點,使用有遮罩曝光方式;對該偏移值大於該臨界範圍的該多個電性連接點,使用無遮罩曝光方式;對該偏移值位於該臨界範圍內的該多個電性連接點,選擇圍繞該多個電性連接點的其它電性連接點使用得更多的曝光方式;藉由有遮罩曝光方式,對該載體進行單一化處理,以在該重佈線結構上方形成一佈線層和/或形成一焊球。
- 如請求項6之半導體重佈線方法,其中,選取兩條相互垂直且同時平行於該載體表面的直線方向作為X方向和Y方向,選取垂直於該載體表面的直線方向作為Z方向,形成XYZ三維座標系,該偏移值為一X偏移值、一Y偏移值和一RZ偏移值的至少其一,其中RZ為圍繞一Z軸旋轉的方向。
- 如請求項6之半導體重佈線方法,其中,形成該重佈線結構包括:首先對該偏移值大於該臨界範圍的該多個電性連接點,使用無遮罩曝光方式曝光;然後對該偏移值小於該臨界範圍的該多個電性連接點,使用有遮罩曝光方式曝光,曝光時對已經使用無遮罩方式曝光之處予以屏蔽;其中對該偏移值位於該臨界範圍內的該多個電性連接點,計算圍繞目前區域的相鄰區域的個數,在這些相鄰區域中任意一種曝光方式被選擇的次數若大於相鄰區域個數的一半,則目前區域選擇該曝 光方式曝光。
- 如請求項6之半導體重佈線方法,其中,形成該重佈線結構包括:首先對該偏移值小於該臨界範圍的該多個電性連接點,使用有遮罩曝光方式曝光;然後對該偏移值大於該臨界範圍的該多個電性連接點,使用無遮罩曝光方式曝光,曝光時對已經使用有遮罩方式曝光之處予以屏蔽;其中對該偏移值位於該臨界範圍內的該多個電性連接點,計算圍繞目前區域的相鄰區域的個數,在這些相鄰區域中任意一種曝光方式被選擇的次數若大於相鄰區域個數的一半,則目前區域選擇該曝光方式曝光。
- 如請求項6之半導體重佈線方法,其中,該臨界範圍為5μm~7μm。
- 如請求項6之半導體重佈線方法,其中,該半導體元件為一晶片。
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JPWO2011024939A1 (ja) * | 2009-08-28 | 2013-01-31 | 日本電気株式会社 | 半導体装置およびその製造方法 |
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CN102332408B (zh) | 2010-07-13 | 2015-05-13 | 矽品精密工业股份有限公司 | 芯片尺寸封装件及其制法 |
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CN104465418B (zh) | 2014-12-24 | 2017-12-19 | 通富微电子股份有限公司 | 一种扇出晶圆级封装方法 |
CN105304507B (zh) * | 2015-11-06 | 2018-07-31 | 通富微电子股份有限公司 | 扇出晶圆级封装方法 |
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US10157803B2 (en) * | 2016-09-19 | 2018-12-18 | Deca Technologies Inc. | Semiconductor device and method of unit specific progressive alignment |
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US20100073663A1 (en) * | 2008-09-19 | 2010-03-25 | Infineon Technologies Ag | System and process for fabricating semiconductor packages |
US20110198762A1 (en) * | 2010-02-16 | 2011-08-18 | Deca Technologies Inc. | Panelized packaging with transferred dielectric |
CN104838486A (zh) * | 2012-11-05 | 2015-08-12 | 德卡技术股份有限公司 | 半导体器件和用于板式封装的自适性图案化的方法 |
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CN107887324A (zh) | 2018-04-06 |
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TW201826444A (zh) | 2018-07-16 |
EP3522209A4 (en) | 2019-12-04 |
KR102224436B1 (ko) | 2021-03-05 |
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