WO2018059474A1 - 一种半导体重布线方法 - Google Patents

一种半导体重布线方法 Download PDF

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Publication number
WO2018059474A1
WO2018059474A1 PCT/CN2017/103900 CN2017103900W WO2018059474A1 WO 2018059474 A1 WO2018059474 A1 WO 2018059474A1 CN 2017103900 W CN2017103900 W CN 2017103900W WO 2018059474 A1 WO2018059474 A1 WO 2018059474A1
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Prior art keywords
electrical connection
connection point
offset value
exposure
semiconductor
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PCT/CN2017/103900
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English (en)
French (fr)
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陈勇辉
唐世弋
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上海微电子装备（集团）股份有限公司
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Application filed by 上海微电子装备（集团）股份有限公司 filed Critical 上海微电子装备（集团）股份有限公司
Priority to US16/338,665 priority Critical patent/US10727112B2/en
Priority to JP2019515906A priority patent/JP6918100B2/ja
Priority to KR1020197012497A priority patent/KR102224436B1/ko
Priority to EP17854924.2A priority patent/EP3522209A4/en
Publication of WO2018059474A1 publication Critical patent/WO2018059474A1/zh

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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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Definitions

  • the present invention relates to the field of semiconductors, and in particular to a semiconductor rewiring method.
  • the integrated circuit package not only directly affects the performance of the integrated circuit, but also limits the miniaturization, low cost and reliability of the entire electronic system. As the size of integrated circuit chips is gradually reduced and the integration height is continuously increasing, higher and higher requirements are placed on integrated circuit packages.
  • Fan Out Wafer Level Package is a kind of wafer-level package which is cut into individual chips 2 and then re-arranged on the new carrier 1 for wafer level packaging as shown in FIG. Packaging process.
  • a new package 3 (shown in Figure 2) can be formed on the new carrier 1 by a conventional wafer level packaging process.
  • FIG. 4 is a schematic diagram of a package structure of a single package. In FIG. 4, the chip 2 is embedded in the package 3, and the pads 4 of the chip 2 are processed by photolithography, CVD, PVD, etching, and electroplating.
  • a typical fan-out wafer package rewiring process uses a photolithography process to define the pattern and position of the upper insulating layer 6, the metal layer 5, and the lower insulating layer 7, and then generates an insulating layer by processes such as CVD, PVD, and electroplating. Metal layer.
  • the mainstream lithography technique ie, mask lithography
  • Chip rearrangement equipment for large-scale mass production yield The chip positioning accuracy is only 7 ⁇ m to 10 ⁇ m (the positioning accuracy required by the above photolithography process is less than 5 ⁇ m), so that the photolithography yield is not high, and mass production is difficult.
  • the present invention proposes a semiconductor rewiring method, which uses a maskless exposure method and a mask exposure method to cooperate with each other to combine the advantages of both, and save time by simply using a maskless exposure method. Improving the efficiency can improve the lithography precision compared to the simple use of the mask exposure method.
  • the present invention provides a semiconductor rewiring method comprising the following steps:
  • Step 1 providing a carrier carrying a plurality of semiconductor elements, each of the plurality of semiconductor elements having a plurality of electrical connection points;
  • Step 2 Measure the position of each electrical connection point with respect to the carrier, compare the measured position with the standard position of the electrical connection point with respect to the carrier, and obtain an offset of each electrical connection point. value;
  • Step 3 forming a rewiring structure on each of the electrical connection points by maskless lithography according to the obtained offset value to correct the offset value;
  • Step 4 The carrier is subjected to a singulation treatment by mask exposure to form a wiring layer and/or a solder ball over the rewiring structure.
  • step 3 comprises:
  • the first dielectric layer is etched by using the first photoresist layer as a mask, and a plurality of first openings are formed in the first dielectric layer, and each of the first openings exposes a corresponding electrical connection point;
  • a metal is filled in the region to form the redistribution structure.
  • step 4 comprises:
  • the second dielectric layer is etched by using the third photoresist layer as a mask, and a plurality of second openings are formed in the second dielectric layer, and a part of the redistribution structure is exposed in each of the second openings;
  • Solder balls are formed on the exposed portion of the redistribution structure.
  • the region of the redistribution structure is defined such that only the redistribution structure of the second opening in step 4 is exposed.
  • the semiconductor component is a chip.
  • the invention also provides a semiconductor rewiring method comprising the following steps:
  • a maskless exposure mode is used for an electrical connection point whose offset value is greater than the critical range.
  • the carrier is singulated by mask exposure to form a wiring layer over the redistribution structure and/or to form solder balls.
  • the offset value It is at least one of an X offset value, a Y offset value, and an R Z offset value, where R Z is a direction of rotation about the Z axis.
  • forming the rewiring structure comprises:
  • the electrical connection point whose offset value is greater than the critical range is exposed by using no mask exposure
  • the electrical connection point whose offset value is within the critical range is calculated around the current area
  • forming the rewiring structure comprises:
  • the electrical connection point whose offset value is less than the critical range is exposed by using a mask exposure mode
  • the exposure is performed by using no mask exposure, and the exposure is masked when the mask has been used for exposure;
  • the current area selects the exposure mode exposure.
  • the critical range is from 5 ⁇ m to 7 ⁇ m.
  • the semiconductor component is a chip.
  • the present invention has the beneficial effects that the present invention provides a semiconductor rewiring method, which is used to calculate the offset value of each electrical connection point on the carrier, and then uses a maskless lithography method.
  • the value-shifting correction forms a redistribution structure on the electrical connection point, and then singulates the carrier by mask lithography (without considering the offset value) to form a wiring layer and/or form over the re-wiring structure Solder balls.
  • maskless lithography and mask lithography are combined with each other, and efficiency can be improved and time can be saved with respect to the simple use of the maskless lithography method.
  • the present invention also provides a semiconductor rewiring method, after calculating an offset value of each electrical connection point on the carrier, and setting a critical range for the offset value, and an electrical property with an offset value smaller than the critical range a connection point, using a mask exposure mode; for an electrical connection point whose offset value is greater than the critical range, selecting a maskless exposure mode; wherein the electrical connection point where the offset value is within the critical range is calculated If the number of adjacent regions of the current region is selected, if the number of times of any one of the adjacent regions is selected is greater than half of the number of adjacent regions, the current region selects the exposure mode to be exposed. In this way, the exposure mode is selected in a targeted manner, and no mask exposure is selected for high precision requirements, mask exposure is selected for low precision requirements, and mask exposure and maskless exposure are combined to improve process efficiency. , saving time and ensuring accuracy.
  • FIG. 1 and 2 are schematic structural views of a fan-out type wafer package in the prior art
  • FIG. 3 is a schematic structural view of a fan-out type wafer package using a maskless lithography technique in the prior art
  • FIG. 4 is a schematic view showing a package structure of a single package in the prior art
  • FIG. 5 is a schematic diagram showing the offset of a chip on a carrier according to Embodiment 1 of the present invention.
  • FIG. 7 is a schematic view showing a deposition of a protective layer on a chip according to Embodiment 1 of the present invention.
  • FIG. 8 is a schematic view showing a photoresist deposited on a protective layer in Embodiment 1 of the present invention.
  • FIG. 9 is a schematic view showing exposure and development of a photoresist in the first embodiment of the present invention.
  • Embodiment 10 is a schematic view showing exposure and development of a protective layer in Embodiment 1 of the present invention.
  • FIG. 11 is a schematic view showing the deposition of a photoresist in the structure of FIG. 10 according to Embodiment 1 of the present invention.
  • FIG. 12 is a schematic view showing exposure and development of a photoresist in the first embodiment of the present invention.
  • Figure 13 is a schematic view showing the deposition of a metal layer on the structure of Figure 12 in the first embodiment of the present invention
  • Figure 14 is a schematic view showing the deposition of a protective layer on the structure of Figure 13 in the first embodiment of the present invention
  • FIG. 15 is a schematic view showing the deposition of a photoresist on the structure of FIG. 14 according to Embodiment 1 of the present invention.
  • FIG. 16 is a schematic view showing the structure of FIG. 15 after exposure and development of the photoresist according to the first embodiment of the present invention
  • 17 is a schematic view showing the exposure of the ball pad in the first embodiment of the present invention.
  • Figure 18 is a schematic view of a ball planting in the first embodiment of the present invention.
  • FIG. 20 is a schematic view showing a deposition of a protective layer on a chip according to Embodiment 2 of the present invention.
  • FIG. 21 is a schematic view showing a photoresist deposited on the structure of FIG. 20 according to Embodiment 2 of the present invention.
  • FIG. 22 is a schematic diagram showing exposure of a protective layer lithography to electrical connection points according to Embodiment 2 of the present invention.
  • FIG. 23 is a schematic view showing the formation of a conductive line by depositing a metal seed layer on the structure of FIG. 22 according to Embodiment 2 of the present invention.
  • Figure 24 is a schematic view showing the deposition of a protective layer on the structure of Figure 23 according to the second embodiment of the present invention.
  • FIG. 25 is a schematic view showing the exposure of a conduction line according to Embodiment 2 of the present invention.
  • 26 is a schematic view showing the formation of a ball-forming pad according to Embodiment 2 of the present invention.
  • FIG. 27 is a schematic view showing deposition of a protective layer on a ball pad according to Embodiment 2 of the present invention.
  • FIG. 28 is a schematic view showing the structure of FIG. 27 after photolithography and forming a solder ball according to Embodiment 2 of the present invention.
  • 1 to 4 1-new carrier, 2-chip, 3-package, 4-pad, 5-metal layer, 6-upper insulating layer, 7-lower insulating layer, 8-bump ball;
  • Figure 5 - Figure 28 100-carrier, 210, 220, 230-chip, 211, 212, 221, 222, 231, 232 - electrical connection point, 241 - modified electrical connection point, 310, 320, 330- Protective layer, 311-opening, 410, 420, 430-resist, 411, 431-resist pattern, 421-metal wiring pattern, 500-metal line, 600-ball mat, 700-bump ball;
  • Embodiment 1 of the present invention provides a fan-out type wafer packaging method.
  • the chip rearrangement is completed on the carrier 100.
  • three horizontal chips 210, 220 and horizontally arranged are depicted.
  • two I/O ports are respectively disposed on each chip, that is, two electrical connection points are disposed, that is, six electrical connection points 211, 212, 221, 222, 231, and 232 are formed.
  • the horizontal axis is the X axis
  • the vertical direction is the Z axis
  • the vertical direction is the Y axis.
  • a plurality of chips are arranged on the carrier 100. Only three chips 210, 220 and 230 are schematically illustrated in FIG. 5, and the electrical connection points and the ball pad definitions on each chip are defined according to the parameters of the subsequent ball placement process. The standard value of its coordinate value.
  • the three chips arranged on the carrier 100 are displaced to different degrees due to the previous process, especially in which the chip center axis LL of the chip 210 and the chip 230 is relative to each package.
  • the center axis UU produces a large offset, and the offset pitch can be up to 7 ⁇ m, so that the actual coordinate value of each electrical connection point must be offset with respect to the standard value.
  • the positional correction of the electrical connection points on the three chips must be performed to obtain a ball pad with no offset from the standard value in order to accurately implant the ball.
  • the method of position correction is to re-wire through lithography to connect the electrical connection point to the position-corrected ball-pad.
  • Step 1.01 First, the chip that has been rearranged on the carrier 100 is gradually scanned to form a chip position layout map. Referring to FIG. 7, the protective layer material is deposited on the chip device surface of the carrier 100 on which the chip is rearranged. Forming a protective layer 310;
  • the protective layer material may be selected from a dielectric material or an organic material.
  • the deposition process of the protective layer 310 may employ various methods such as vapor deposition, oxidation, and the like.
  • Step 1.02 depositing a photoresist 410 on the protective layer 310 formed in step 1.01, please refer to FIG. 8;
  • Step 1.03 using a device having a maskless lithography function, performing an exposure process in a region corresponding to six electrical connection points 211, 212, 221, 222, 231, and 232, and defining by a photolithography process such as exposure, development, and hard filming.
  • a photolithography process such as exposure, development, and hard filming.
  • the maskless lithography apparatus can find the corresponding lithography area by aligning with the chip on the carrier 100 according to the pre-input chip position layout diagram and the lithography definition pattern, and after completing step 1.03, the photoresist A photoresist pattern 411 that is aligned one-to-one with the electrical connection points is formed in 410.
  • Step 1.04 removing the protective layer material covered by the lithography process in the area of the electrical connection point defined in step 1.03, as shown in FIG. 10;
  • the method for removing the protective layer material may be implemented by wet etching or dry etching.
  • a plurality of openings 311 are formed in the protective layer 310, and each opening 311 corresponds to an electrical connection point. And the electrical connection point is exposed at the bottom of the opening, so that the electrical connection point is subsequently taken out through the metal wiring.
  • Step 1.05 depositing a photoresist 420 on the structure formed in step 1.04, as shown in FIG. 11;
  • Step 1.06 Using a device having a maskless lithography function, a metal rewiring region is defined by a photolithography process such as exposure, development, and hard film.
  • the electrical connection point interconnection with the chip is realized by metal rewiring, wherein the metal wiring position of the metal rewiring is uniformly defined by the reference on the carrier 100, and fine adjustment and compensation are performed according to the positional deviation of the chip, specifically, based on no deviation
  • the standard metal wiring pattern taking into account the positional offset of each chip, forms a modified metal wiring pattern 421, as shown in FIG. 12, for example, when the chip central axis is offset to the left by a certain offset from the central axis of the package.
  • the pattern may be extended to the right and/or to the right by a distance on the basis of the standard metal wiring pattern to form a modified metal wiring pattern, which may be greater than or equal to the offset, for example;
  • the pattern may be extended to the left and/or to the left by a certain distance on the basis of the standard metal wiring pattern to form a corrected metal wiring pattern;
  • the rear metal wiring pattern 421 should expose the opening 311 formed in step 1.04; it is easy to understand that the gold formed in step 1.06
  • One or more of the shapes, sizes, and positions of the wiring patterns may be different from each other, that is, the distribution of the metal wiring patterns on the entire carrier 100 is not regular;
  • Step 1.07 sputtering a metal seed layer on the structure formed in step 1.06, and then forming a rewiring metal line 500 by electroless plating, electroplating, etc., as shown in FIG. 13, the metal line 500 is formed in a subsequent process. a ball pad for planting the ball or further connected to the upper metal;
  • the growth metal material may be a metal such as copper, aluminum, or tungsten, and is not limited to the three metal materials.
  • the positional correction of the electrical connection point on the chip is realized by forming the metal line 500.
  • the subsequent routing and/or ball placement process is then completed by singulation.
  • the singulation process here can also be understood as a unified process, that is, it is not necessary to consider the positional offset of a single chip on the carrier 100, and the individual chips are directly processed based on the standard non-offset position.
  • the following is an example of directly performing the ball placement process by singulation.
  • Step 1.08 removing the residual photoresist, and then depositing a protective layer 320, as shown in FIG. 14;
  • the material of the protective layer 320 may be selected from a dielectric material or an organic material, and the deposition process of the protective layer 320 may be performed by various methods such as vapor deposition, oxidation, or sputtering.
  • Step 1.09 depositing a photoresist 430 on the structure formed in step 1.08, as shown in FIG.
  • Step 1.10 Using a mask lithography function device, using the carrier 100 as a unified reference, defining the position and pattern size of the ball bumper 600 without offset from the standard value, forming a photoresist corresponding to the metal line 500 one by one.
  • the graphic 431, as shown in FIG. 16, is easily understood to have a regular distribution of the photoresist pattern 431 formed in the step 1.10 over the entire carrier 100 due to the singular processing method;
  • Step 1.11 removing the protective layer material 320 covered by the ball pad 600 defined by the photolithography process to expose a portion of the underlying metal line 500, and then removing the photoresist 430, as shown in FIG. 17, the exposed part of the metal The line forms a ball pad 600;
  • the protective layer material removal method can be realized by wet etching or dry etching.
  • Step 1.12 Complete the solder ball 700 fabrication process, as shown in FIG.
  • the maskless lithography and the mask lithography can be combined with each other, and the efficiency can be improved and the time can be saved with respect to the simple use of the maskless lithography method.
  • a second embodiment of the present invention provides a method for fan-out wafer packaging.
  • the position of the rearranged chip on the carrier 100 may be first scanned to form a chip position layout diagram.
  • the critical range is set, and the critical range can be set according to a specific working condition.
  • the offset is 5 ⁇ m to 7 ⁇ m as a critical reference. For example, when the area where the chip position offset value is larger than the critical range is mask-free exposure and then the entire film is masked by photolithography, the yield of the fan-out wafer package can be greatly improved.
  • the exposure mode of all areas has been defined in advance, and if the area where the offset value is within the critical range, if the mask exposure mode is selected, it is performed together with the area where the offset value is smaller than the critical range. There is a mask exposure; if the region where the offset value is within the critical range selects the maskless exposure mode, the maskless exposure is performed together with the region where the offset value is larger than the critical range.
  • the exposure order of the region where the offset value is larger than the critical range and the region smaller than the critical range is not fixed, for example, the region where the offset value is larger than the critical range and the region where the maskless exposure mode is selected within the critical range may be used first.
  • Membrane exposure then exposure to the remaining areas using mask exposure, shielding the exposed areas while shielding; or you can first select the area where the offset is less than the critical range and the critical range
  • the area with mask exposure is exposed by mask exposure, and the remaining area is exposed by maskless exposure, while the exposed area is masked.
  • Step 2.01 performing position scanning on the chip layout of the carrier 100 to form a chip position layout diagram
  • Step 2.02 depositing a protective layer on the chip device surface of the carrier 100 on which the chip is rearranged a protective layer 310 is formed as shown in FIG. 20;
  • the material of the protective layer 310 may be selected from a dielectric material or an organic material.
  • the deposition process of the protective layer 310 may employ various methods such as vapor deposition, oxidation, and the like.
  • Step 2.03 depositing a photoresist 410 on the structure formed in step 2.02, as shown in FIG. 21;
  • Step 2.04 The horizontal direction is the X axis, the vertical direction is the Z axis, and the XYZ three-dimensional coordinate system is established with the Y axis perpendicular to the XZ plane direction.
  • the offset value is divided into an X offset value, a Y offset value, and an R Z offset value, where R Z is a direction of rotation about the Z axis, and any one of the above-mentioned offset values of the electrical connection point is greater than a critical range
  • the exposure process is performed by using a maskless lithography function device, and any of the above-mentioned areas where the offset value of the electrical connection point is smaller than the critical range is performed by using a mask lithography function device, and the offset value is in a critical range.
  • the inner region is selected to be exposed in the exposure mode with the most selection times among other regions of the region, and then the protective layer 310 of the region corresponding to the electrical connection point is removed, as shown in FIG. 22;
  • the order of maskless exposure and mask exposure is not limited, for example, the area where the offset value is larger than the critical range and the area where the maskless exposure mode is selected within the critical range may be exposed without masking, and then The remaining area is exposed by mask exposure, and the exposed area is shielded at the same time as the exposure; or the area where the offset value is less than the critical range and the critical range is required to be masked. The area is exposed by mask exposure, and the remaining area is exposed by maskless exposure, and the exposed area is masked while exposed.
  • the protective layer material removal method can be realized by wet etching or dry etching.
  • selecting the exposure mode with the most selection times among the other areas surrounding the area includes: calculating the number of adjacent areas surrounding the current area, and arbitrarily among the adjacent areas If the number of times an exposure mode is selected is greater than half of the number of adjacent regions, the current region selects the exposure mode exposure. For example, if the offset value is within the critical range There are 8 adjacent areas around an area.
  • the area is also mask-free; if more than half of the 8 areas are If the area is masked, the area is also masked; if 4 of the 8 adjacent areas use mask exposure and the other 4 use maskless exposure, the area can Any of a mask exposure method and a maskless exposure method is employed.
  • Step 2.05 The region of the modified electrical connection point is defined by a photoresist in a similar manner to the step 1.05-1.06 in the first embodiment, and the metal seed layer is sputtered, and then the electroless plating, electroplating, etc. are used to form a correction.
  • the electrical connection point 241, as shown in FIG. 23, can be seen from FIG. 23, the relative position between each modified electrical connection point 241 and the corresponding package is substantially uniform, and the central axis of the corresponding chip The relative position is not uniform. Therefore, the positional offset of the electrical connection point 241 is corrected, and the chip positional offset is corrected. Further, each of the modified electrical connection points 241 is connected to a corresponding electrical connection point;
  • the position compensation of the electrical connection point on the chip is realized by correcting the electrical connection point 241.
  • the subsequent routing and/or ball placement process is then completed by singulation.
  • the singulation process here can also be understood as a unified process, that is, it is not necessary to consider the positional offset of a single chip on the carrier 100, and the individual chips are directly processed based on the standard non-offset position.
  • Step 2.06 depositing a protective layer 320 on the structure formed in step 2.05, as shown in FIG. 24;
  • Step 2.07 using a mask lithography function device, defining a region where the electrical connection point 241 is modified by a photolithography process, and removing the protective layer 320 covered on the region, as shown in FIG. 25;
  • Step 2.08 The upper metal wiring region is formed by an exposure process using a mask lithography function device.
  • the metal seed layer is sputtered, and then the upper metal line is formed by electroless plating, electroplating, etc., as shown in FIG. 26, it is easily understood that the upper metal line formed in step 2.08 is used throughout the carrier due to the singular processing method.
  • the distribution on 100 is regular;
  • the growth metal material may be a metal such as copper, aluminum, or tungsten, and is not limited to the three metal materials.
  • Step 2.09 depositing a protective layer 330 on the structure formed in step 2.08, as shown in FIG.
  • the protective layer material may be selected from a dielectric material or an organic material, and the deposition process of the protective layer 330 may be performed by various methods such as vapor deposition, oxidation, or sputtering.
  • Step 2.10 Using a mask lithography function device, defining the position and pattern size of the offset-free ball pad 600, removing the protective layer 330 covered on the corresponding area of the ball pad 600, and exposing the upper metal line portion That is, the ball pad 600, and finally the solder ball 700 manufacturing process is completed on the ball pad 600, as shown in FIG.
  • the present invention has been described in the above embodiments, but the present invention is not limited to the above embodiments, and the carrier 100 may carry other semiconductor devices having electrical connection points other than the chip. It will be apparent to those skilled in the art that various modifications and changes can be made in the invention without departing from the spirit and scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of the invention as claimed.

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Abstract

提供一种半导体重布线方法，计算出载体（100）上每个电性连接点（211,212,221,222,231,232）的偏移值后，先使用无掩膜光刻方式进行偏移值修正，在电性连接点上形成重布线结构，然后通过有掩膜光刻方式对载体（100）进行单一化处理，以在重布线结构上方形成布线层和/或形成焊球（700）。这样将无掩膜光刻和有掩膜光刻相互结合，相对于单纯使用无掩膜光刻方式，能够提高效率，节省时间。

Description

一种半导体重布线方法 技术领域
本发明涉及半导体领域，特别涉及一种半导体重布线方法。
背景技术
随着集成电路技术的不断发展，电子产品越来越向小型化、智能化、高性能以及高可靠性方向发展。而集成电路封装不仅直接影响着集成电路性能，而且还制约着整个电子系统的小型化、低成本和可靠性。在集成电路芯片尺寸逐步缩小，集成高度不断提高的情况下，对集成电路封装提出了越来越高的要求。
扇出型晶圆封装(Fan Out Wafer Level Package，可简写为FOWLP)是一种如图1所示将芯片晶圆切割成独立芯片2后重新排布在新载体1上进行晶圆级封装的封装工艺。通过传统的晶圆级封装工艺，可以在新载体1上形成新的封装体3(如图2所示)。其中单颗封装体的封装结构示意图如图4所示，图4中，芯片2嵌入在封装体3内，针对芯片2的焊盘4，通过光刻、CVD、PVD、刻蚀和电镀等工艺形成由下绝缘层7、金属层5和上绝缘层6组成的重新再布线结构，在新的I/O端口(即电性连接点，从金属层5引出)上形成焊球8均匀的分布在新封装体3上，若干个新封装体3排列在新载体1上形成图2所示的结构。
典型的扇出型晶圆封装重布线工艺方法，是采用光刻工艺定义上绝缘层6、金属层5和下绝缘层7的图形和位置，再通过CVD、PVD和电镀等工艺生成绝缘层和金属层。主流的光刻技术(即有掩膜光刻)需要先按照目标图形的一定比例制造掩膜，通过光学投影的方式使芯片上涂敷的光敏胶部分区域发生反应定义图形和位置。由于满足大规模量产产率的芯片重新排布设备 的芯片定位精度仅为7μm～10μm(而上述光刻工艺所要求的定位精度为小于5μm)，使得光刻良率不高，难以大规模量产。
另外还有一种无掩膜光刻技术，其原理是通过光调制器取代掩膜，通过实时控制调制出需要的图形，采用无掩膜光刻时结构如图3所示，这种方式能够解决芯片重新排布定位精度不准的问题，但是这种方式需要将整片新载体1上的所有光刻区域都进行拟合计算，所以每次光刻的产率极低(每次光刻需要2～3小时)，不能满足目前扇出型晶圆封装工艺的生产节拍(5～10分钟)。
发明内容
为解决上述问题，本发明提出了一种半导体重布线方法，使用无掩膜曝光方式和有掩膜曝光方式相互配合，综合两者的优点，相对于单纯使用无掩膜曝光方式能够节省时间、提高效率，相对于单纯使用有掩膜曝光方式能够提高光刻精度。
为达到上述目的，本发明提供一种半导体重布线方法，包括以下步骤：
步骤1：设置承载多个半导体元件的载体，所述多个半导体元件中的每一个具有多个电性连接点；
步骤2：测量每个电性连接点相对于所述载体的位置，将所测得的位置与该电性连接点相对于所述载体的标准位置比较，获得每个电性连接点的偏移值；
步骤3：根据得到的偏移值，通过无掩膜光刻的方式，在每个电性连接点上形成重布线结构，以修正所述偏移值；
步骤4：通过有掩膜曝光方式，对所述载体进行单一化处理，以在重布线结构上方形成布线层和/或形成焊球。
作为优选，步骤3包括：
淀积第一介质层；
在第一介质层上涂覆第一光刻胶层；
根据步骤2得到的偏移值，通过无掩膜光刻的方式在第一光刻胶层中形成多个第一光刻胶图形，其中，每个第一光刻胶图形与相应的一个电性连接点对准；
以第一光刻胶层为掩膜，刻蚀第一介质层，在第一介质层中形成多个第一开口，每个第一开口暴露出相应的电性连接点；
去除第一光刻胶层；
涂覆第二光刻胶层；
根据所述偏移值，通过无掩膜光刻的方式在第二光刻胶层中形成多个第二光刻胶图形，以定义出用于形成所述重布线结构的区域；
在所述区域中填充金属，以形成所述重布线结构。
作为优选，步骤4包括：
淀积第二介质层；
在第二介质层上涂覆第三光刻胶层；
通过有掩膜曝光方式，在第三光刻胶层中形成多个第三光刻胶图形，每个第三光刻胶图形对应于一个植球垫区域；
以第三光刻胶层为掩膜，刻蚀第二介质层，在第二介质层中形成多个第二开口，每个第二开口中暴露出部分重布线结构；
在所暴露出的部分重布线结构上形成焊球。
作为优选，所述重布线结构的区域被定义为，使得步骤4中的所述第二开口中只有重布线结构被暴露。
作为优选，所述半导体元件为芯片。
本发明还提供一种半导体重布线方法，包括以下步骤：
设置承载多个半导体元件的载体，所述多个半导体元件中的每一个具有多个电性连接点；
测量每个电性连接点相对于所述载体的位置；
将所测得的位置与该电性连接点相对于所述载体的标准位置比较，获得每个电性连接点的偏移值；
将所述偏移值与预设的一临界范围进行比较，根据比较结果进行光刻，在所述电性连接点上形成重布线结构，其中，形成重布线结构包括：
对偏移值小于所述临界范围的电性连接点，使用有掩膜曝光方式；
对偏移值大于所述临界范围的电性连接点，使用无掩膜曝光方式；
对偏移值位于所述临界范围内的电性连接点，选择围绕该电性连接点的其它电性连接点使用得更多的曝光方式；
通过有掩膜曝光方式，对所述载体进行单一化处理，以在重布线结构上方形成布线层和/或形成焊球。
作为优选，选取两条相互垂直且同时平行于所述载体表面的直线方向作为X和Y方向，选取垂直于所述载体表面的直线方向作为Z方向，形成XYZ三维坐标系，所述偏移值为X偏移值、Y偏移值和RZ偏移值的至少其一，其中RZ为围绕Z轴旋转的方向。
作为优选，形成重布线结构包括：
首先对偏移值大于所述临界范围的电性连接点，使用无掩膜曝光方式曝光；
然后对偏移值小于所述临界范围的电性连接点，使用有掩膜曝光方式曝光，曝光时对已经使用无掩膜方式曝光之处予以屏蔽；
其中对偏移值位于所述临界范围内的电性连接点，计算围绕当前区域的 相邻区域的个数，在这些相邻区域中任意一种曝光方式被选择的次数若大于相邻区域个数的一半，则当前区域选择该曝光方式曝光。
作为优选，形成重布线结构包括：
首先对偏移值小于所述临界范围的电性连接点，使用有掩膜曝光方式曝光；
然后对偏移值大于所述临界范围的电性连接点，使用无掩膜曝光方式曝光，曝光时对已经使用有掩膜方式曝光之处予以屏蔽；
其中对偏移值位于所述临界范围内的电性连接点，计算围绕当前区域的相邻区域的个数，在这些相邻区域中任意一种曝光方式被选择的次数若大于相邻区域个数的一半，则当前区域选择该曝光方式曝光。
作为优选，所述临界范围为5μm～7μm。
作为优选，所述半导体元件为芯片。
与现有技术相比，本发明的有益效果是：本发明提供一种半导体重布线方法，计算出载体上每个电性连接点的偏移值后，先使用无掩膜光刻方式进行偏移值修正，在电性连接点上形成重布线结构，然后通过有掩膜光刻方式对载体进行单一化处理(无需考虑偏移值)，以在重布线结构上方形成布线层和/或形成焊球。这样将无掩膜光刻和有掩膜光刻相互结合，相对于单纯使用无掩膜光刻方式，能够提高效率，节省时间。
本发明还提供一种半导体重布线方法，在计算出载体上每个电性连接点的偏移值后，并对偏移值设定临界范围，对偏移值小于所述临界范围的电性连接点，使用有掩膜曝光方式；对偏移值大于所述临界范围的电性连接点，选择无掩膜曝光方式；其中对偏移值位于所述临界范围内的电性连接点，计算围绕当前区域的相邻区域的个数，在这些相邻区域中任意一种曝光方式被选择的次数若大于相邻区域个数的一半，则当前区域选择该曝光方式曝光， 这样具有针对性地选择曝光方式，对于精度要求高之处选择无掩膜曝光，对于精度要求低之处选择有掩膜曝光，将有掩膜曝光与无掩膜曝光相互配合，从而提高工艺效率，节省时间，并同时保证了精度。
附图说明
图1和图2皆为现有技术中扇出型晶圆封装的结构示意图；
图3为现有技术中使用无掩膜光刻技术的扇出型晶圆封装的结构示意图；
图4为现有技术中单颗封装体的封装结构示意图；
图5为本发明实施例一中芯片在载体上形成偏移的示意图；
图6为本发明实施例一的方法流程图；
图7为本发明实施例一中在芯片上沉积保护层后示意图；
图8为本发明实施例一中在保护层上沉积光刻胶后示意图；
图9为本发明实施例一中对光刻胶曝光显影后示意图；
图10为本发明实施例一中对保护层曝光显影后示意图；
图11为本发明实施例一中对图10结构进行沉积光刻胶后示意图；
图12为本发明实施例一中对光刻胶进行曝光显影后示意图；
图13为本发明实施例一中对图12结构沉积金属层后示意图；
图14为本发明实施例一中对图13结构沉积保护层后示意图；
图15为本发明实施例一中对图14结构沉积光刻胶后示意图；
图16为本发明实施例一中对图15结构对光刻胶曝光显影后示意图；
图17为本发明实施例一中将植球垫暴露示意图；
图18为本发明实施例一中植球示意图；
图19为本发明实施例二方法流程图；
图20为本发明实施例二在芯片上沉积保护层后示意图；
图21为本发明实施例二在图20结构上沉积光刻胶后示意图；
图22为本发明实施例二对保护层光刻将电性连接点暴露示意图；
图23为本发明实施例二在图22结构上沉积金属种子层形成导通线路示意图；
图24为本发明实施例二在图23结构上沉积保护层后示意图；
图25为本发明实施例二在将导通线路暴露示意图；
图26为本发明实施例二形成植球垫示意图；
图27为本发明实施例二在植球垫上沉积保护层示意图；
图28为本发明实施例二对图27结构光刻并形成焊球后示意图。
图1-图4中：1-新载体、2-芯片、3-封装体、4-焊盘、5-金属层、6-上绝缘层，7-下绝缘层、8-焊球；
图5-图28中：100-载体，210、220、230-芯片，211、212、221、222、231、232-电性连接点，241-修正电性连接点，310、320、330-保护层，311-开口，410、420、430-光刻胶，411、431-光刻胶图形，421-金属布线图形，500-金属线路，600-植球垫，700-焊球；
LL-芯片中心轴、UU-封装体中心轴。
具体实施方式
为使本发明的上述目的、特征和优点能够更加明显易懂，下面结合附图对本发明的具体实施方式做详细的说明。
实施例一
本发明实施例一提供一种扇出型晶圆封装方法，请参照图5，在载体100上完成了芯片重新排布，在图5中绘视了水平横向排列的三个芯片210、220和230，每个芯片上各自设置两个I/O端口，也即设置两个电性连接点，即形成了六个电性连接点211、212、221、222、231、232。
以水平横向为X轴，以竖直方向为Z轴，以垂直于XZ平面方向为Y轴 建立XYZ三维坐标系。
在载体100上排布若干个芯片，图5中仅示意性画出三个芯片210、220和230，根据后续植球工艺的参数，对每个芯片上的电性连接点以及植球垫定义其坐标值的标准值。
从图5中可以看出，由于前道工艺原因，导致排列在载体100上的三个芯片产生了不同程度的偏移，尤其是其中芯片210和芯片230的芯片中心轴LL相对于每个封装体中心轴UU产生的偏移较大，偏移间距可达7μm，从而每个电性连接点的实际坐标值相对于标准值必定会产生偏移。
因此在进行植球工艺之前，必须对三个芯片上的电性连接点进行位置修正，得到相对于标准值无偏移的植球垫，才能进行精确地植球。位置修正的方法就是通过光刻重新布线，将电性连接点连通至位置修正后的植球垫上。
如图6所示，具体实施的工艺步骤如下：
步骤1.01：首先对载体100上已经完成重新排布的芯片逐步扫描，形成芯片位置布局(mapping)图，请参照图7，在完成芯片重新排布的载体100的芯片器件面淀积保护层材料，形成保护层310；
其中，保护层材料可以选择介质材料或者有机材料。保护层310的淀积工艺可以采用各种气相沉积、氧化等方法。
步骤1.02：在步骤1.01形成的保护层310上沉积光刻胶410，请参照图8；
步骤1.03：采用具有无掩膜光刻功能设备，在六个电性连接点211、212、221、222、231、232对应的区域进行曝光工艺，通过曝光、显影、坚膜等光刻工艺定义要制作重新布线的电性连接点对应的区域，如图9所示；
其中，无掩膜光刻设备可根据预先输入的芯片位置布局图和光刻定义图形在载体100上通过与芯片的对准，找出对应的光刻区域，在完成步骤1.03之后，光刻胶410中形成了与电性连接点一一对准的光刻胶图形411。
步骤1.04：去除步骤1.03中光刻工艺定义出的在电性连接点区域覆盖的保护层材料，如图10所示；
其中，保护层材料去除方式可通过湿法腐蚀或干法刻蚀等方式来实现，在完成步骤1.04之后，保护层310中形成了多个开口311，每个开口311与一个电性连接点对应且开口底部暴露出所述电性连接点，以便后续通过金属布线将电性连接点引出。
步骤1.05：在步骤1.04形成的结构上沉积光刻胶420，如图11所示；
步骤1.06：采用具有无掩膜光刻功能设备，通过曝光、显影、坚膜等光刻工艺定义制作金属重新布线区域。通过金属重新布线实现与芯片电性连接点互连，其中金属重布线的金属线路位置通过载体100上的基准统一定义，并根据芯片的位置偏移进行微调和补偿，具体的，可基于无偏差的标准金属布线图形，结合考虑各芯片的位置偏移，形成修正后的金属布线图形421，如图12所示，举例而言，当芯片中心轴相对于封装体中心轴左偏一定偏移量时，可以在标准金属布线图形的基础上将图形向右延伸和/或向右移动一定距离以形成修正后的金属布线图形，该延伸和/或移动距离例如可以大于等于所述偏移量；当芯片中心轴相对于封装体中心轴右偏时，则可以在标准金属布线图形的基础上将图形向左延伸和/或向左移动一定距离以形成修正后的金属布线图形；此外，该修正后的金属布线图形421应当暴露出步骤1.04中形成的开口311；容易理解的是，步骤1.06中所形成的各金属布线图形的形状、大小、位置中的一种或多种是可以互不相同的，即所述各金属布线图形在整个载体100上的分布不具有规律性；
步骤1.07：在步骤1.06形成的结构上溅射金属种子层，再通过化学镀、电镀等方法，形成重新布线的金属线路500，如图13所示，该金属线路500用于在后续工艺中形成用于植球的植球垫或者进一步连接至上层金属；
其中，生长金属材料可以是铜、铝、钨等金属，并不限于所述的三种金属材料。
至此，通过形成金属线路500实现了芯片上的电性连接点的位置修正。接下来只需通过单一化处理完成后续的布线和/或植球工艺。此处的单一化处理也可以理解为统一化处理，即不需要考虑单个芯片在载体100上的位置偏移，而直接基于标准的无偏移的位置对各个芯片进行统一处理。
下面以通过单一化处理直接进行植球工艺为例加以说明。
步骤1.08：去除残余光刻胶，然后沉积保护层320，如图14所示；
其中，保护层320的材料可以选择介质材料或者有机材料，保护层320的沉积工艺可以采用各种气相沉积、氧化或溅射等方法。
步骤1.09：在步骤1.08形成的结构上沉积光刻胶430，如图15所示；
步骤1.10：采用有掩膜光刻功能设备，以载体100为统一基准，定义相对于标准值无偏移的植球垫600的位置和图形尺寸，形成与金属线路500一一对应的光刻胶图形431，如图16所示，容易理解的是，由于采用了单一化处理方式，步骤1.10所形成的光刻胶图形431在整个载体100上的分布是具有规律性的；
步骤1.11：去除光刻工艺定义出的植球垫600区域覆盖的保护层材料320以暴露出下方的部分金属线路500，然后去除光刻胶430，如图17所示，所暴露出的部分金属线路形成植球垫600；
其中，保护层材料去除方式可通过湿法腐蚀或干法刻蚀等方式来实现。
步骤1.12：完成焊球700制作工艺，如图18所示。
本实施例可将无掩膜光刻和有掩膜光刻相互结合，相对于单纯使用无掩膜光刻方式，能够提高效率，节省时间。
实施例二
本发明实施例二提供一种扇出晶圆封装方法，对于载体100的芯片位置数量较少的情况，可首先对载体100上的经过重新排布的芯片进行位置扫描，形成芯片位置布局图，并且对于偏移值，设定以临界范围，临界范围可根据具体工况设定，本实施例中以偏移5μm～7μm为临界基准。如当芯片位置偏移值大于临界范围的区域采用无掩摸曝光然后再整片采用有掩摸曝光的光刻方式，通过这种方式可大大提高扇出型晶圆封装的产率。
或者在曝光时，对于偏移值大于临界范围的区域采用无掩膜曝光，对于偏移值小于临界范围的区域采用有掩膜曝光，对于偏移值位于临界范围内的区域，选择围绕该区域的其它区域中被选择次数最多的曝光方式曝光。在曝光前的光刻系统中，所有区域的曝光方式都已经事先定义好，则偏移值位于临界范围内的区域若选择有掩膜曝光方式，则与偏移值小于临界范围的区域一起进行有掩膜曝光；若偏移值位于临界范围内的区域选择无掩膜曝光方式，则与偏移值大于临界范围内的区域一起进行无掩膜曝光。
其中偏移值大于临界范围的区域和小于临界范围的区域的曝光次序并不固定，如可先对偏移值大于临界范围的区域以及临界范围内需要选择无掩膜曝光方式的区域采用无掩膜方式曝光，然后对于剩下的区域采用有掩膜曝光方式曝光，曝光的同时对于已经曝光过的区域予以屏蔽处理；或者也可先对偏移值小于临界范围的区域以及临界范围内需要选择有掩膜曝光方式的区域采用有掩膜曝光方式曝光，对于剩下的区域采用无掩膜曝光方式曝光，曝光的同时对于已经曝光过的区域予以屏蔽处理。
具体方法如图19所示，具体步骤如下：
步骤2.01：对载体100的芯片布局进行位置扫描，形成芯片位置布局图；
步骤2.02：在完成芯片重新排布的载体100的芯片器件面淀积保护层材 料，形成保护层310，如图20所示；
其中，保护层310的材料可以选择介质材料或者有机材料。保护层310的淀积工艺可以采用各种气相沉积、氧化等方法。
步骤2.03：在步骤2.02形成的结构上沉积光刻胶410，如图21所示；
步骤2.04：以水平横向为X轴，以竖直方向为Z轴，以垂直于XZ平面方向为Y轴建立XYZ三维坐标系。偏移值分为X偏移值、Y偏移值和RZ偏移值，RZ为围绕Z轴旋转的方向，对电性连接点的上述任意一种偏移值大于临界范围的区域，采用无掩膜光刻功能设备进行曝光工艺，对电性连接点的上述任意一种偏移值小于临界范围的区域，采用有掩膜光刻功能设备进行曝光工艺，对于偏移值位于临界范围内的区域，选择围绕该区域的其它区域中被选择次数最多的曝光方式曝光，然后去除电性连接点所对应区域的保护层310，如图22所示；
其中无掩膜曝光和有掩膜曝光的次序并不限定，如可先对偏移值大于临界范围的区域以及临界范围内需要选择无掩膜曝光方式的区域采用无掩膜方式曝光，然后对于剩下的区域采用有掩膜曝光方式曝光，曝光的同时对于已经曝光过的区域予以屏蔽处理；或者也可先对偏移值小于临界范围的区域以及临界范围内需要选择有掩膜曝光方式的区域采用有掩膜曝光方式曝光，对于剩下的区域采用无掩膜曝光方式曝光，曝光的同时对于已经曝光过的区域予以屏蔽处理。
其中，保护层材料去除方式可通过湿法腐蚀或干法刻蚀等方式来实现。
其中，对于偏移值位于临界范围内的区域，选择围绕该区域的其它区域中被选择次数最多的曝光方式曝光包括：计算围绕当前区域的相邻区域的个数，在这些相邻区域中任意一种曝光方式被选择的次数若大于相邻区域个数的一半，则当前区域选择该曝光方式曝光。例如偏移值位于临界范围内的某 一区域周围有8个邻近区域，如果这8个邻近区域中有半数以上的区域采用无掩膜曝光方式，则该区域也采用无掩膜曝光方式；如果这8个邻近区域中有半数以上的区域采用有掩膜曝光方式，则该区域也采用有掩膜曝光方式；如果这8个邻近区域中有4个采用有掩膜曝光方式、另外4个采用无掩膜曝光方式，则该区域可以采用有掩膜曝光方式和无掩膜曝光方式中的任一种。
步骤2.05：通过与实施例一中的步骤1.05-1.06类似的方法用光刻胶定义出修正电性连接点的区域，并通过溅射金属种子层，再通过化学镀、电镀等方法，形成修正电性连接点241，如图23所示，从图23可看出，各修正电性连接点241与对应的封装体之间的相对位置是基本统一的，而与对应的芯片的中轴线的相对位置是不统一的，由此，通过修正电性连接点241的位置补偿，修正了芯片位置偏移，此外，各修正电性连接点241均连接至对应的电性连接点；
至此，通过修正电性连接点241实现了芯片上的电性连接点的位置补偿。接下来只需通过单一化处理完成后续的布线和/或植球工艺。此处的单一化处理也可以理解为统一化处理，即不需要考虑单个芯片在载体100上的位置偏移，而直接基于标准的无偏移的位置对各个芯片进行统一处理。
下面以通过单一化处理依次进行布线和植球工艺为例加以说明。
步骤2.06：在步骤2.05形成的结构上沉积保护层320，如图24所示；
步骤2.07：采用有掩膜光刻功能设备，通过光刻工艺定义出修正电性连接点241所在的区域，并去除该区域上覆盖的保护层320，如图25所示；
步骤2.08：采用有掩膜光刻功能设备通过曝光工艺定义制作上层金属布线区域。溅射金属种子层，再通过化学镀、电镀等方法，形成上层金属线路，如图26所示，容易理解的是，由于采用了单一化处理方式，步骤2.08所形成的上层金属线路在整个载体100上的分布是具有规律性的；
其中，生长金属材料可以是铜、铝、钨等金属，并不限于所述的三种金属材料。
步骤2.09：在步骤2.08形成的结构上沉积保护层330，如图27所示；
其中，保护层材料可以选择介质材料或者有机材料，保护层330的淀积工艺可以采用各种气相沉积、氧化或溅射等方法。
步骤2.10：采用有掩膜光刻功能设备，定义无偏移的植球垫600的位置和图形尺寸，去除植球垫600对应的区域上覆盖的保护层330，所暴露出的上层金属线路部分即为植球垫600，最后在植球垫600上完成焊球700制作工艺，如图28所示。
本实施例对于具有不同偏移值的不同区域针对性地采用不同的曝光方式，更好地将无掩膜光刻和有掩膜光刻相互结合，提高光刻效率，节省时间。
本发明对上述实施例进行了描述，但本发明不仅限于上述实施例，如载体100可以承载芯片以外的其它具有电性连接点的半导体器件。显然本领域的技术人员可以对发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包括这些改动和变型在内。

Claims (11)

  1. 一种半导体重布线方法，其特征在于，包括以下步骤：
    步骤1：设置承载多个半导体元件的载体，所述多个半导体元件中的每一个具有多个电性连接点；
    步骤2：测量每个电性连接点相对于所述载体的位置，将所测得的位置与该电性连接点相对于所述载体的标准位置比较，获得每个电性连接点的偏移值；
    步骤3：根据得到的偏移值，通过无掩膜光刻的方式，在每个电性连接点上形成重布线结构，以修正所述偏移值；
    步骤4：通过有掩膜曝光方式，对所述载体进行单一化处理，以在重布线结构上方形成布线层和/或形成焊球。
  2. 如权利要求1所述的半导体重布线方法，其特征在于，步骤3包括：
    淀积第一介质层；
    在第一介质层上涂覆第一光刻胶层；
    根据步骤2得到的偏移值，通过无掩膜光刻的方式在第一光刻胶层中形成多个第一光刻胶图形，其中，每个第一光刻胶图形与相应的一个电性连接点对准；
    以第一光刻胶层为掩膜，刻蚀第一介质层，在第一介质层中形成多个第一开口，每个第一开口暴露出相应的电性连接点；
    去除第一光刻胶层；
    涂覆第二光刻胶层；
    根据所述偏移值，通过无掩膜光刻的方式在第二光刻胶层中形成多个第二光刻胶图形，以定义出用于形成所述重布线结构的区域；
    在所述区域中填充金属，以形成所述重布线结构。
  3. 如权利要求2所述的半导体重布线方法，其特征在于，步骤4包括：
    淀积第二介质层；
    在第二介质层上涂覆第三光刻胶层；
    通过有掩膜曝光方式，在第三光刻胶层中形成多个第三光刻胶图形，每个第三光刻胶图形对应于一个植球垫区域；
    以第三光刻胶层为掩膜，刻蚀第二介质层，在第二介质层中形成多个第二开口，每个第二开口中暴露出部分重布线结构；
    在所暴露出的部分重布线结构上形成焊球。
  4. 如权利要求3所述的半导体重布线方法，其特征在于，所述重布线结构的区域被定义为，使得步骤4中的所述第二开口中只有重布线结构被暴露。
  5. 如权利要求1所述的半导体重布线方法，其特征在于，所述半导体元件为芯片。
  6. 一种半导体重布线方法，其特征在于，包括以下步骤：
    设置承载多个半导体元件的载体，所述多个半导体元件中的每一个具有多个电性连接点；
    测量每个电性连接点相对于所述载体的位置；
    将所测得的位置与该电性连接点相对于所述载体的标准位置比较，获得每个电性连接点的偏移值；
    将所述偏移值与预设的一临界范围进行比较，根据比较结果进行光刻，在所述电性连接点上形成重布线结构，其中，形成重布线结构包括：
    对偏移值小于所述临界范围的电性连接点，使用有掩膜曝光方式；
    对偏移值大于所述临界范围的电性连接点，使用无掩膜曝光方式；
    对偏移值位于所述临界范围内的电性连接点，选择围绕该电性连接点的 其它电性连接点使用得更多的曝光方式；
    通过有掩膜曝光方式，对所述载体进行单一化处理，以在重布线结构上方形成布线层和/或形成焊球。
  7. 如权利要求6所述的半导体重布线方法，其特征在于，选取两条相互垂直且同时平行于所述载体表面的直线方向作为X和Y方向，选取垂直于所述载体表面的直线方向作为Z方向，形成XYZ三维坐标系，所述偏移值为X偏移值、Y偏移值和RZ偏移值的至少其一，其中RZ为围绕Z轴旋转的方向。
  8. 如权利要求6所述的半导体重布线方法，其特征在于，形成重布线结构包括：
    首先对偏移值大于所述临界范围的电性连接点，使用无掩膜曝光方式曝光；
    然后对偏移值小于所述临界范围的电性连接点，使用有掩膜曝光方式曝光，曝光时对已经使用无掩膜方式曝光之处予以屏蔽；
    其中对偏移值位于所述临界范围内的电性连接点，计算围绕当前区域的相邻区域的个数，在这些相邻区域中任意一种曝光方式被选择的次数若大于相邻区域个数的一半，则当前区域选择该曝光方式曝光。
  9. 如权利要求6所述的半导体重布线方法，其特征在于，形成重布线结构包括：
    首先对偏移值小于所述临界范围的电性连接点，使用有掩膜曝光方式曝光；
    然后对偏移值大于所述临界范围的电性连接点，使用无掩膜曝光方式曝光，曝光时对已经使用有掩膜方式曝光之处予以屏蔽；
    其中对偏移值位于所述临界范围内的电性连接点，计算围绕当前区域的相邻区域的个数，在这些相邻区域中任意一种曝光方式被选择的次数若大于 相邻区域个数的一半，则当前区域选择该曝光方式曝光。
  10. 如权利要求6所述的半导体重布线方法，其特征在于，所述临界范围为5μm～7μm。
  11. 如权利要求6所述的半导体重布线方法，其特征在于，所述半导体元件为芯片。
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