CN103117261B - 封装结构及其形成方法 - Google Patents

封装结构及其形成方法 Download PDF

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CN103117261B
CN103117261B CN201210187433.3A CN201210187433A CN103117261B CN 103117261 B CN103117261 B CN 103117261B CN 201210187433 A CN201210187433 A CN 201210187433A CN 103117261 B CN103117261 B CN 103117261B
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redistribution line
redistribution
welding region
flat top
polymer areas
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CN103117261A (zh
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萧景文
郑明达
林志伟
陈承先
陈志华
郭正铮
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种器件包括再分配线,以及在该再分配线上模制的聚合物区域。该聚合物区域包括第一平坦顶面。焊接区域设置在该聚合物区域中并且与再分配线电连接。焊接区域包括不高于第一平坦顶面的第二平坦顶面。本发明提供了封装结构及其形成方法。

Description

封装结构及其形成方法
技术领域
本发明涉及集成电路制造,具体而言涉及集成电路的封装结构及其形成方法。
背景技术
现代集成电路的制造通常涉及若干步骤。首先,在半导体晶圆上制造集成电路,该半导体晶圆包含多个重复的半导体芯片,每个半导体芯片中均包含有集成电路。然后,从晶圆上切割半导体芯片,并且对半导体芯片进行封装。封装工艺具有两个主要目的:保护精细的半导体芯片,以及将内部集成电路连接到外部引脚。
在传统的封装工艺中,可以使用倒装芯片接合将半导体芯片安装在封装元件上。将底部填充剂分散到半导体芯片和封装元件之间的间隙中,以防止在焊料凸块或焊球中形成裂缝,其中,裂缝通常是由热应力引起的。封装元件可以是包括用于在相对面之间按指定路线发送电信号的金属连接件的中介层。芯片可以通过直接的金属接合、焊料接合等接合至中介层。
随着对更多功能的需求的不断增加,堆叠式封装(package-on-package,PoP)技术被用于进一步扩大封装件的集成能力。当使用PoP技术时,将封装件堆叠起来。关于如何形成PoP结构存在各种设计。通过使用PoP技术,封装设计变得更加灵活且更加简单。升级产品的上市时间也得以减少。随着高集成化程度,由于封装元件之间的连接路径缩短,所得到的封装件的电气性能也得到改善。
发明内容
一方面,本发明涉及一种器件,包括:再分配线;聚合物区域,模制在所述再分配线的上方,其中,所述聚合物区域包括第一平坦顶面;以及焊接区域,位于所述聚合物区域中并且与所述再分配线电连接,其中,所述焊接区域包括不高于所述第一平坦顶面的第二平坦顶面。
在所述的器件中,所述第二平坦顶面与所述第一平坦顶面基本上齐平。
在所述的器件中,所述第二平坦顶面低于所述第一平坦顶面。
所述的器件进一步包括:封装元件,所述封装元件位于与所述再分配线处于同一水平面的另一再分配线的上方,并且接合至所述另一再分配线,其中,所述封装元件设置在所述聚合物区域中。
在所述的器件中,所述封装元件的顶面低于所述第一平坦顶面。
在所述的器件中,所述焊接区域是具有接触所述再分配线的顶面的底面的焊球,并且其中,所述焊接区域的侧壁是圆的,并且与所述聚合物区域相接触。
在所述的器件中,所述再分配线位于多个再分配层的顶部再分配层中,并且其中,所述器件进一步包括与所述多个再分配层的底层接合的连接件。
另一方面,本发明还提供了一种器件,包括:再分配线;模塑料,模制在所述再分配线的上方,其中,所述模塑料包括第一平坦顶面;焊球,位于所述模塑料中,其中,所述焊球位于所述再分配线的上方并且接合至所述再分配线,并且其中,所述焊球包括圆侧壁以及不高于第一平坦顶面的第二平坦顶面;以及管芯,位于所述再分配线的上方并且接合至所述再分配线,其中,所述管芯位于所述模塑料中,其中,所述管芯的顶面不高于所述第一平坦顶面。
在所述的器件中,所述管芯的所述顶面低于所述第一平坦顶面。
在所述的器件中,所述管芯的所述顶面与所述第一平坦顶面齐平。
在所述的器件中,所述焊球的所述圆侧壁与所述模塑料相接触。
在所述的器件中,所述第二平坦顶面与所述第一平坦顶面齐平。
在所述的器件中,所述第二平坦顶面低于所述第一平坦顶面。
又一方面,本发明提供了一种方法,包括:在再分配线的上方形成连接件,并且将所述连接件电连接至所述再分配线,其中,所述连接件包括具有圆顶面的焊接区域;模制聚合物区域以覆盖所述连接件和所述再分配线;以及研磨所述聚合物区域和所述焊接区域,直到所述焊接区域形成与所述聚合物区域的第二顶面齐平的第一顶面。
在所述的方法中,形成所述连接件的步骤包括:在所述再分配线上放置焊球;以及对所述焊球进行回流。
所述的方法进一步包括:在研磨的步骤之后,将封装元件接合至所述连接件。
所述的方法进一步包括:蚀刻所述焊接区域以使所述第一顶面凹进至低于所述聚合物区域的所述第二顶面的水平面。
所述的方法进一步包括:在形成所述连接件的步骤之前,在释放层上方形成所述再分配线,所述再分配线进一步位于载具上;以及在研磨的步骤之后,将所述载具从包括所述再分配线的结构拆卸下来。
所述的方法进一步包括:在模制所述聚合物区域的步骤之前,将管芯接合到另一再分配线上,其中,所述再分配线与所述另一再分配线处于相同的水平面,并且其中,在模制所述聚合物区域的步骤之后,将所述管芯模制在所述聚合物区域中。
在所述的方法中,所述再分配线位于多个再分配层的顶部再分配层中,并且其中,所述方法进一步包括,在所述多个再分配层的底层上形成连接件。
附图说明
为了更充分地理解实施例及其优点,现将结合附图所进行的以下描述作为参考,其中:
图1至图10是根据各个实施例的形成封装件的中间阶段的截面图。
具体实施方式
下面,详细论述本发明实施例的制造和使用。然而,应该理解,本发明提供了许多可以在各种具体环境中实现的可应用的概念。所讨论的具体实施例仅仅是说明性的,而不限制本发明的范围。
根据各个实施例,提供了一种封装结构及其形成方法。举例说明了形成该封装结构的中间阶段。对实施例的变化进行了论述。在所有各个视图和说明性实施例中,相同的附图编号用于指示相同的元件。
图1至图10示出了根据实施例的制造封装件的中间阶段的截面图。图1示出了载具20和在载具20上形成的释放层22。载具20可以是玻璃载具、陶瓷载具等。释放层22可以由基于聚合物的材料形成,该材料随后能够被去除,从而可以将在释放层22上方形成的结构从载具20上拆卸下来。释放层22可以由热释放、化学释放、UV-释放或激光释放材料形成。在一些实施例中,释放层22作为液体分散,然后,将其固化。使释放层22的顶面变平,以具有高度的共面性。在可选实施例中,释放层22是层压膜,并且被层压到载具20上。
参考图2,在释放层22上形成再分配层24。再分配层24包括金属线26和使金属线26互连的通孔28,其中,金属线26和通孔28形成在层间电介质(ILD)30中。金属线26和通孔28在下文中被称为再分配线(RDL)26/28。再分配层24的底层可以与释放层22的顶面相接触。在实施例中,RDL 26/28可以由金属或金属合金(诸如铜、铝、铝铜、镍等)形成。ILD30可以由感光材料(诸如聚酰亚胺或聚苯并恶唑(PBO))形成。可选地,ILD 30可以由氮化物(诸如氮化硅)形成。在又一些实施例中,ILD 30可以由氧化物(诸如氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、掺硼磷硅酸盐玻璃(BPSG)等)形成。根据一些示例性实施例,RDL 26/28和ILD 30的形成可以包括形成并且图案化其中一个ILD 30,沉积金属层,以及然后图案化该金属层。可选地,可以使用镶嵌工艺,其包括形成作为空白层的ILD 30,在相应的ILD 30中形成开口,在相应的ILD 30中填充金属材料,以及实施化学机械抛光(CMP)。
在实施例中,可以任选地形成作为RDL 26/28的顶层的一部分的金属饰面32。在一些实施例中,金属饰面32可以是镍层。在其他实施例中,金属饰面32可以由包括但不限于无电镀镍浸金(ENIG)、无电镀镍无电镀金(ENEG)、无电镀镍无电镀钯浸金(ENEPIG)、直接浸金(DIG)、浸锡等等的材料和方法形成。
在可选实施例中,不是从释放层22开始形成再分配层24,而是预先形成再分配层24,再将其接合到释放层22上。在一些实施例中,封装基板可以被用作再分配层24。
参考图3,封装元件36与金属层24接合。在一些实施例中,封装元件36是其中包括有源器件(诸如晶体管(未示出))的器件管芯。在可选实施例中,封装元件36是包括与中介层、封装衬底等接合的器件管芯的封装件。可以通过连接件38将封装元件36接合至金属层24,该连接件38可以包括焊接区域、金属柱、和/或金属焊盘等等。接合可以是焊料接合、金属柱与金属柱接合、迹线上凸块(BOT)接合等等。
图4示出了Z-互连件40的形成,Z-互连件40的名称源于其在垂直于再分配层24的主顶面的方向(Z方向)上连接部件的功能。在整个说明书中,Z-互连件40被可选地称为连接件40。在得到的结构中,Z-互连件的至少顶部以及可能全部都包括具有圆顶面的焊接区域。在一些实施例中,Z-互连件40是焊球,将其放置在金属饰面32/RDL 26/28上,然后,对其进行回流。因此,相应的Z-互连件40的形成可以包括放置并回流Z-互连件40。在可选实施例中,Z-互连件40可以具有其他结构,包括,例如,金属柱和位于金属柱上的焊料帽(soldercap)。因此,相应的Z-互连件40的形成可以包括形成掩模层(未示出),在掩模层中形成开口,电镀金属柱和焊料帽,以及去除掩模层。然后,可以对焊料帽进行回流。
图5示出了聚合物区域42的模制,该聚合物区域42可以包含模塑料、模塑底部填充剂、环氧树脂等。聚合物区域42覆盖封装元件36和Z-互连件40,并且聚合物区域42的顶面42A高于封装元件36的顶面36A和Z-互连件40的顶面40A,从而使封装元件36和Z-互连件40嵌在聚合物区域42中。
参考图6,实施平坦化(诸如研磨工艺)去除聚合物区域42的顶层。在平坦化期间也去除每个Z-互连件40的顶部。结果,Z-互连件40的顶面40A是平坦的,并且与聚合物区域42的顶面42A齐平。另一方面,Z-互连件40的侧壁与聚合物区域42相接触,并且是圆形(round)。在平坦化之后,封装元件36的顶面36A可以与顶面40A和42A齐平或低于顶面40A和42A。
图7示出了Z-互连件40的任选凹进,其中,在形成图6所示的步骤之后,使用侵蚀Z-互连件40但不侵蚀聚合物区域42的蚀刻剂实施蚀刻步骤。因此,形成凹槽41,并且Z-互连件40的顶面40A低于聚合物区域42的顶面42A。在使Z-互连件40凹进之后,顶面40A仍保持基本上是平坦的。在示例性实施例中,凹进深度D1(其为顶面40A和顶面42A之间的高度差)大于例如约10μm,然而也可以采用不同的值。
图8示出了从再分配层24释放载具20以及形成连接件48。在实施例中,可以通过实施使释放层22失去粘合性的步骤(诸如,UV光照射)来实现释放,从而可以从释放层22去除载具20。然后,可以去除释放层22,形成图8所示的结构。
图8还示出了在再分配层24的底层上形成连接件48,其中,连接件48和Z-互连件40位于再分配层24的相对面上。在一些实施例中,连接件48是焊球,将其放置在再分配层24的底层上并对其进行回流。然后,可以沿着划线52进行分割,从而形成多个封装件,其中,每个封装件都可以与示出的封装件50相同。
接着,如图9和10所示,封装元件54接合至封装件50。如图9所示,首先将封装元件54放置在封装件50上,并且封装元件54的连接件56仍驻留在Z-互连件40上。在一些实施例中,封装元件54是包括与中介层(或封装基板)57接合的器件管芯55的封装件,并因此,图10中的所得结构是堆叠式封装(PoP)结构。在可选实施例中,封装元件54可以是另一类型的元件,诸如,器件管芯。用于接合的连接件56可以是具有圆表面的焊球,然而,连接件56也可以具有其他结构,诸如,金属柱和位于金属柱上的焊料帽(球)。可以看出,由于Z-互连件40的顶面是平坦的,所以连接件56不大可能在Z-互连件40上移动。而且,在其中Z-互连件40的顶面从聚合物区域42的顶面42A凹进的实施例中,连接件56被更好地限制在凹槽41中。
在连接件56的表面与Z-互连件40的顶面40A相接触之后,实施回流以形成连接件58,该连接件58将封装元件54连接至封装件50。得到的结构在图10中示出。
可以看出,在图10示出的所得结构中,如图7中的凹槽41可以在回流期间进一步限制熔化的焊料,从而提高封装工艺的组装合格率。
根据实施例,一种器件包括再分配线,以及在再分配线上方模制的聚合物区域。该聚合物区域包括第一平坦顶面。焊接区域设置在聚合物区域中并且与再分配线电连接。焊接区域包括不高于第一平坦顶面的第二平坦顶面。
根据其他实施例,一种器件包括再分配线和在再分配线上方模制的模塑料,其中,该模塑料包括第一平坦顶面。焊球设置在模塑料中,其中,该焊球位于再分配线的上方并且接合至再分配线。焊球包括圆侧壁和不高于第一平坦顶面的第二平坦顶面。管芯设置在再分配线的上方并接合至再分配线,并且该管芯位于模塑料中。管芯的顶面不高于第一平坦顶面。
根据又一些实施例,一种方法包括在再分配线的上方形成连接件,并且将该连接件电连接至再分配线,其中,连接件包括具有圆顶面的焊接区域。模制聚合物区域以覆盖连接件和再分配线。然后,对聚合物区域和焊接区域进行研磨,直到该焊接区域形成与聚合物区域的第二顶面齐平的第一顶面。
尽管已经详细地描述了实施例及其优势,但应该理解,可以在不背离所附权利要求限定的实施例主旨和范围的情况下,在其中做各种不同的改变、替换和更改。而且,本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员根据本发明将很容易理解,根据本发明可以应用现有的或今后开发的用于执行与根据本文所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造、材料组分、装置、方法或步骤。因此,所附权利要求预期在其范围内包括这样的工艺、机器、制造、材料组分、装置、方法或步骤。此外,每条权利要求构成单独的实施例,并且各个权利要求和实施例的组合在本发明的范围内。

Claims (12)

1.一种集成电路的封装器件,包括:
再分配线,形成第一凹槽和第二凹槽;
聚合物区域,模制在所述再分配线的上方并且延伸至所述第二凹槽中,其中,所述聚合物区域包括第一平坦顶面;以及
焊接区域,位于所述聚合物区域中并且与所述再分配线电连接,其中,所述焊接区域延伸至所述第一凹槽中,所述焊接区域包括低于所述第一平坦顶面的第二平坦顶面,并且所述第二平坦顶面低于所述焊接区域周围的所述聚合物区域的所有平坦顶面,并且所述第二平坦顶面上方的所述聚合物区域的未与所述焊接区域接触的侧壁呈弧形;
封装元件,设置在所述聚合物区域中,其中,所述封装元件的顶面与所述第一平坦顶面齐平。
2.根据权利要求1所述的器件,进一步包括封装元件,所述封装元件位于与所述再分配线处于同一水平面的另一再分配线的上方,并且接合至所述另一再分配线。
3.根据权利要求1所述的器件,其中,所述焊接区域是具有接触所述再分配线的顶面的底面的焊球,并且其中,所述焊接区域的侧壁是圆的,并且与所述聚合物区域相接触。
4.根据权利要求1所述的器件,其中,所述再分配线位于多个再分配层的顶部再分配层中,并且其中,所述器件进一步包括与所述多个再分配层的底层接合的连接件。
5.一种集成电路的封装器件,包括:
再分配线,形成第一凹槽和第二凹槽;
模塑料,模制在所述再分配线的上方并且延伸至所述第二凹槽中,其中,所述模塑料包括第一平坦顶面;
焊球,位于所述模塑料中,其中,所述焊球位于所述再分配线的上方并且接合至所述再分配线,所述焊球延伸至所述第一凹槽中,并且其中,所述焊球包括:
圆侧壁;以及
第二平坦顶面,低于第一平坦顶面,并且所述第二平坦顶面低于所述焊球周围的所述模塑料的所有平坦顶面,并且位于所述第二平坦顶面上方的所述模塑料的未与所述焊球接触的侧壁呈弧形;以及
管芯,位于所述再分配线的上方并且接合至所述再分配线,其中,所述管芯位于所述模塑料中,其中,所述管芯的顶面与所述第一平坦顶面齐平。
6.根据权利要求5所述的器件,其中,所述焊球的所述圆侧壁与所述模塑料相接触。
7.一种形成集成电路的封装结构的方法,包括:
在再分配线的上方形成连接件,并且将所述连接件电连接至所述再分配线,其中,所述再分配线形成第一凹槽和第二凹槽,所述连接件包括具有圆顶面的焊接区域,所述焊接区域延伸至所述第一凹槽中;以及,
在所述再分配线的上方形成管芯;
模制聚合物区域以覆盖所述连接件和所述再分配线以及所述管芯,所述聚合物区域延伸至所述第二凹槽中;
研磨所述聚合物区域和所述焊接区域,直到所述焊接区域形成与所述聚合物区域的第二顶面齐平的第一顶面,并且使所述管芯的顶面与所述第二顶面齐平;以及
蚀刻所述焊接区域但不蚀刻所述模制聚合物区域以使所述第一顶面凹进至低于所述聚合物区域的所述第二顶面的水平面,并且位于所述水平面上方的所述模制聚合物区域的未与所述焊接区域接触的侧壁呈弧形,其中,所述水平面低于所述焊接区域周围的所述聚合物区域的所有顶面。
8.根据权利要求7所述的方法,其中,形成所述连接件的步骤包括:
在所述再分配线上放置焊球;以及
对所述焊球进行回流。
9.根据权利要求7所述的方法,进一步包括,在研磨的步骤之后,将封装元件接合至所述连接件。
10.根据权利要求7所述的方法,进一步包括:
在形成所述连接件的步骤之前,在释放层上方形成所述再分配线,所述再分配线进一步位于载具上;以及
在研磨的步骤之后,将所述载具从包括所述再分配线的结构拆卸下来。
11.根据权利要求7所述的方法,进一步包括,在模制所述聚合物区域的步骤之前,将所述管芯接合到另一再分配线上,其中,所述再分配线与所述另一再分配线处于相同的水平面,并且其中,在模制所述聚合物区域的步骤之后,将所述管芯模制在所述聚合物区域中。
12.根据权利要求7所述的方法,其中,所述再分配线位于多个再分配层的顶部再分配层中,并且其中,所述方法进一步包括,在所述多个再分配层的底层上形成连接件。
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Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8922013B2 (en) * 2011-11-08 2014-12-30 Stmicroelectronics Pte Ltd. Through via package
US9679836B2 (en) 2011-11-16 2017-06-13 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods for forming the same
US9633869B2 (en) * 2013-08-16 2017-04-25 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with interposers and methods for forming the same
CN104701270B (zh) * 2013-12-04 2017-12-19 日月光半导体制造股份有限公司 半导体封装结构及半导体工艺
US9735129B2 (en) 2014-03-21 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming the same
US9318452B2 (en) 2014-03-21 2016-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming the same
US20160351522A1 (en) * 2015-05-27 2016-12-01 Freescale Semiconductor, Inc. Package-on-package device and cavity formation by solder removal for package interconnection
US10043769B2 (en) 2015-06-03 2018-08-07 Micron Technology, Inc. Semiconductor devices including dummy chips
CN110024115B (zh) * 2016-10-04 2024-02-02 天工方案公司 具有包覆模制结构的双侧射频封装
US9966341B1 (en) 2016-10-31 2018-05-08 Infineon Technologies Americas Corp. Input/output pins for chip-embedded substrate
US10304716B1 (en) 2017-12-20 2019-05-28 Powertech Technology Inc. Package structure and manufacturing method thereof
KR20220008088A (ko) 2020-07-13 2022-01-20 삼성전자주식회사 반도체 패키지
KR20220009218A (ko) 2020-07-15 2022-01-24 삼성전자주식회사 반도체 패키지, 및 이를 가지는 패키지 온 패키지

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3057130B2 (ja) * 1993-02-18 2000-06-26 三菱電機株式会社 樹脂封止型半導体パッケージおよびその製造方法
US6181569B1 (en) * 1999-06-07 2001-01-30 Kishore K. Chakravorty Low cost chip size package and method of fabricating the same
JP2001077293A (ja) * 1999-09-02 2001-03-23 Nec Corp 半導体装置
JP2003273317A (ja) 2002-03-19 2003-09-26 Nec Electronics Corp 半導体装置及びその製造方法
US6806570B1 (en) * 2002-10-24 2004-10-19 Megic Corporation Thermal compliant semiconductor chip wiring structure for chip scale packaging
US7388294B2 (en) * 2003-01-27 2008-06-17 Micron Technology, Inc. Semiconductor components having stacked dice
US7372151B1 (en) * 2003-09-12 2008-05-13 Asat Ltd. Ball grid array package and process for manufacturing same
US7268012B2 (en) * 2004-08-31 2007-09-11 Micron Technology, Inc. Methods for fabrication of thin semiconductor assemblies including redistribution layers and packages and assemblies formed thereby
US7446419B1 (en) * 2004-11-10 2008-11-04 Bridge Semiconductor Corporation Semiconductor chip assembly with welded metal pillar of stacked metal balls
US7714453B2 (en) * 2006-05-12 2010-05-11 Broadcom Corporation Interconnect structure and formation for package stacking of molded plastic area array package
SG137770A1 (en) 2006-05-12 2007-12-28 Broadcom Corp Interconnect structure and formation for package stacking of molded plastic area array package
CN101507373A (zh) * 2006-06-30 2009-08-12 日本电气株式会社 布线板、使用布线板的半导体器件、及其制造方法
TWI336502B (en) * 2006-09-27 2011-01-21 Advanced Semiconductor Eng Semiconductor package and semiconductor device and the method of making the same
US8237259B2 (en) * 2007-06-13 2012-08-07 Infineon Technologies Ag Embedded chip package
KR20090033605A (ko) 2007-10-01 2009-04-06 삼성전자주식회사 적층형 반도체 패키지, 그 형성방법 및 이를 구비하는전자장치
US7777351B1 (en) * 2007-10-01 2010-08-17 Amkor Technology, Inc. Thin stacked interposer package
US8390117B2 (en) * 2007-12-11 2013-03-05 Panasonic Corporation Semiconductor device and method of manufacturing the same
CN101630148A (zh) 2008-07-17 2010-01-20 上海普芯达电子有限公司 降低设备待机能耗的方法和具有低待机能耗的设备
US7812449B2 (en) * 2008-09-09 2010-10-12 Stats Chippac Ltd. Integrated circuit package system with redistribution layer
US7888181B2 (en) * 2008-09-22 2011-02-15 Stats Chippac, Ltd. Method of forming a wafer level package with RDL interconnection over encapsulant between bump and semiconductor die
US8546189B2 (en) * 2008-09-22 2013-10-01 Stats Chippac, Ltd. Semiconductor device and method of forming a wafer level package with top and bottom solder bump interconnection
US8592992B2 (en) * 2011-12-14 2013-11-26 Stats Chippac, Ltd. Semiconductor device and method of forming vertical interconnect structure with conductive micro via array for 3-D Fo-WLCSP
TWI499024B (zh) 2009-01-07 2015-09-01 Advanced Semiconductor Eng 堆疊式多封裝構造裝置、半導體封裝構造及其製造方法
US8501587B2 (en) * 2009-01-13 2013-08-06 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked integrated chips and methods of fabrication thereof
KR101056747B1 (ko) * 2009-04-14 2011-08-16 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조 방법
US8716873B2 (en) * 2010-07-01 2014-05-06 United Test And Assembly Center Ltd. Semiconductor packages and methods of packaging semiconductor devices
US9312218B2 (en) * 2011-05-12 2016-04-12 Stats Chippac, Ltd. Semiconductor device and method of forming leadframe with conductive bodies for vertical electrical interconnect of semiconductor die
TWI492680B (zh) * 2011-08-05 2015-07-11 Unimicron Technology Corp 嵌埋有中介層之封裝基板及其製法
US8779601B2 (en) * 2011-11-02 2014-07-15 Stmicroelectronics Pte Ltd Embedded wafer level package for 3D and package-on-package applications, and method of manufacture
US9679836B2 (en) * 2011-11-16 2017-06-13 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods for forming the same

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US20220278031A1 (en) 2022-09-01
US20130119539A1 (en) 2013-05-16
US9679836B2 (en) 2017-06-13
US20200083152A1 (en) 2020-03-12
CN103117261A (zh) 2013-05-22
US10510644B2 (en) 2019-12-17
US20170278777A1 (en) 2017-09-28
US11961791B2 (en) 2024-04-16

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