CN103107152A - 用于芯片级封装的凸块 - Google Patents

用于芯片级封装的凸块 Download PDF

Info

Publication number
CN103107152A
CN103107152A CN2012100416056A CN201210041605A CN103107152A CN 103107152 A CN103107152 A CN 103107152A CN 2012100416056 A CN2012100416056 A CN 2012100416056A CN 201210041605 A CN201210041605 A CN 201210041605A CN 103107152 A CN103107152 A CN 103107152A
Authority
CN
China
Prior art keywords
projection
semiconductor element
diameter
soldered ball
metal structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2012100416056A
Other languages
English (en)
Other versions
CN103107152B (zh
Inventor
林俊宏
陈玉芬
林宗澍
普翰屏
陈宪伟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN103107152A publication Critical patent/CN103107152A/zh
Application granted granted Critical
Publication of CN103107152B publication Critical patent/CN103107152B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0239—Material of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/024—Material of the insulating layers therebetween
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H01L2224/03462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0501—Shape
    • H01L2224/05016—Shape in side view
    • H01L2224/05018—Shape in side view being a conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05024—Disposition the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05558—Shape in side view conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0605—Shape
    • H01L2224/06051—Bonding areas having different shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06131—Square or rectangular array being uniform, i.e. having a uniform pitch across the array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06136—Covering only the central area of the surface to be connected, i.e. central arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1413—Square or rectangular array
    • H01L2224/14131—Square or rectangular array being uniform, i.e. having a uniform pitch across the array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1413—Square or rectangular array
    • H01L2224/14132—Square or rectangular array being non uniform, i.e. having a non uniform pitch across the array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1413—Square or rectangular array
    • H01L2224/14134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/14135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1413—Square or rectangular array
    • H01L2224/14134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/14136—Covering only the central area of the surface to be connected, i.e. central arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/14179—Corner adaptations, i.e. disposition of the bump connectors at the corners of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1705—Shape
    • H01L2224/17051—Bump connectors having different shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

芯片级半导体器件包括半导体管芯、第一凸块和第二凸块。具有第一直径和第一高度的第一凸块形成在半导体管芯的外部区域上。具有第二直径和第二高度的第二凸块形成在半导体管芯的内部区域上。第二直径大于第一直径，而第二高度与第一高度相同。通过改变凸块的形状，可以重新分配整个凸块的应力和应变。因此，提高了芯片级半导体器件的热循环可靠性。本发明还提供了一种用于芯片级封装的凸块。

Description

用于芯片级封装的凸块
技术领域
本发明一般地涉及半导体领域，更具体地来说，涉及用于芯片级封装的凸块。
背景技术
随着各种电子元件(例如，晶体管、二极管、电阻器、电容器等)的集成度的不断提高，半导体产业经历了快速增长。在大多数情况下，这种集成度的提高来自于最小特征尺寸的持续缩小，从而允许更多的元件集成到给定的区域。随着近期对更小的电子器件的需求的增长，加剧了对更小和更有创造性的半导体管芯封装技术的需求。
随着半导体技术的发展，作为一种有效的替代，出现了基于芯片级或芯片尺寸封装的半导体器件，以进一步缩小半导体管芯的物理尺寸。在基于芯片级封装的半导体器件中，封装产生在由多种凸块提供接触件的芯片上。采用基于芯片级封装的半导体器件可以实现更高的密度。更进一步地，基于芯片级封装的半导体器件可以实现更小的形状系数，更有效益的成本支出，更高的性能和更低的功耗。
基于芯片级封装的半导体器件可以包括在半导体管芯的多个凸块下金属(UBM)开口上形成的多个焊球。焊球可以由锡、铅形成。在回流工艺之前，半导体器件在对准之后被拾取并放置在印刷电路板(PCB)上。因此，基于芯片级封装的半导体器件上的多个焊球与PCB板上的相应的焊盘对准。通过采用热空气流动和适当的压力，使焊球加热，然后融化从而将半导体器件与PCB板连接。芯片级封装技术具有一定的优势。芯片级封装的有益特征之一是芯片级封装技术可以降低制造成本。另一个基于芯片级封装的多芯片半导体器件的有益特征是通过将凸块夹置在半导体器件和PCB板之间来减少附加损耗。
发明内容
为了解决现有技术中所存在的缺陷，根据本发明的一方面，提供了一个器件包括：半导体管芯；具有第一直径的第一凸块，所述第一凸块在所述半导体管芯上的第一区域上；以及具有第二直径的第二凸块，所述第二凸块在所述半导体管芯上的第二区域上，其中所述第二直径不同于所述第一直径。
在该器件中，所述第一直径大于所述第二直径。
在该器件中，所述第一区域是所述半导体管芯的内部区域；以及所述第二区域是所述半导体管芯的外部区域。
在该器件中，所述外部区域的宽度大约等于或小于所述内部区域的宽度的三分之一。
在该器件中，所述第一区域是所述半导体管芯的内部区域；以及所述第二区域是所述半导体管芯的角部。
在该器件中，所述第一凸块形成在所述第一凸块下金属结构上；以及所述第二凸块形成在所述第二凸块下金属结构上，其中所述第一凸块下金属结构不同于所述第二凸块下金属结构。
在该器件中，所述第二凸块下金属结构的直径大于第一凸块下金属结构的直径。
根据本发明的另一方面，提供了一个器件包括：半导体管芯；具有第一直径和第一高度的第一凸块，所述第一凸块在邻近所述半导体管芯的边缘处形成；以及具有第二直径和第二高度的第二凸块，所述第二凸块在不邻近所述半导体管芯的边缘处形成，其中所述第二凸块不同于所述第一凸块。
在该器件中，所述第一直径大于所述第二直径。
在该器件中，所述第一高度高于所述第二高度。
在该器件中，所述第一凸块形成在所述半导体管芯的外部区域上；以及所述第二凸块形成在所述半导体管芯的内部区域上。
在该器件中，所述外部区域的宽度大约等于或小于所述内部区域的宽度的三分之一。
在该器件中，所述第一凸块形成在所述半导体管芯的第一角部上；以及所述第二凸块形成在所述半导体管芯的内部区域上。
在该器件中，所述半导体管芯包括：衬底；层间介电层，所述层间介电层形成在所述衬底上；多个金属化层，所述多个金属化层形成在所述层间介电层的上方；钝化层，所述钝化层形成在所述多个金属化层的上方；聚合物层，所述聚合物层形成在所述钝化层上，其中，在所述聚合物层中形成再分布层。
根据本发明的又一方面，提供了一种结构包括：半导体管芯；具有第一直径的第一凸块下金属结构，所述第一凸块下金属结构形成在所述半导体管芯的外部区域上；以及具有第二直径的第二凸块下金属结构，所述第二凸块下金属结构形成在所述半导体管芯的内部区域上，其中所述第一凸块下金属结构不同于所述第二凸块下金属结构。
在该结构中，所述第二直径大于所述第一直径。
在该结构中，所述外部区域所具有的宽度大约等于或小于所述内部区域的宽度的三分之一。
该结构进一步包括：第一凸块，所述第一凸块形成在所述第一凸块下金属结构上；以及第二凸块，所述第二凸块形成在所述第二凸块下金属结构上。
在该结构中，所述第一凸块比所述第二凸块薄；以及所述第一凸块具有沙漏的形状。
在该结构中，所述半导体管芯包括：衬底；层间介电层，所述层间介电层形成在所述衬底上；多个金属化层，所述多个金属化层形成在所述层间介电层的上方；钝化层，所述钝化层形成在所述多个金属化层的上方；以及聚合物层，所述聚合物层形成在所述钝化层上，其中在所述聚合物层中形成再分布层。
附图说明
为了更全面地理解本发明的实施例及其优点，现将结合附图所进行的以下描述作为参考，其中：
图1示出了根据实施例具有芯片级封装部件的凸块结构的顶视图和截面图；
图2示出了根据另一个实施例具有芯片级封装部件的凸块结构的顶视图和截面图；
图3示出了根据又一个实施例具有芯片级封装部件的凸块结构的顶视图和截面图。
除非另有说明，不同附图中的相应标号和符号通常指相应部件。将附图绘制成清楚地示出实施例的相关方面而不必须成比例绘制。
具体实施方式
下面，详细讨论本发明优选实施例的制造和使用。然而，应该理解，本发明提供了许多可以在各种具体环境中实现的可应用的概念。所讨论的具体实施例仅仅示出制造和使用本发明的具体方式，而不用于限制本发明的范围。
本发明将根据在特定的背景下的实施例对用于芯片级封装的凸块设计技术进行描述。然而，本发明也可以应用于多种半导体产业的封装。
首先参考图1。图1示出了根据实施例具有芯片级封装部件的凸块结构的顶视图和截面图。如图1所示，凸块结构形成在半导体管芯100上。半导体管芯100包括衬底192。衬底192可以是硅衬底。可选地，衬底192可以是绝缘体上硅衬底。衬底192可以进一步包括多种电路(未示出)。电路形成在衬底上192上，并且可以是适用于特定应用的任何类型的电路。
根据实施例，电路可以包括各种n型金属氧化物半导体(NMOS)和/或p型金属氧化物半导体(PMOS)器件，如晶体管、电容器、电阻器、二极管、光电二极管、熔丝等。电路可以互连以执行一个或多个功能。这些功能可以包括存储结构、处理结构、传感器、放大器、配电系统、输入/输出电路等。本领域普通技术人员可以理解，上述描述性实施例仅用作进一步解释本发明的应用，并不以任何方式限制本发明。
层间介电层182形成在衬底192上。例如，层间介电层182可以由低-K介电材料(如，氧化硅)形成。层间介电层182可以通过本领域已知的任何合适的方法(如，旋涂、化学汽相沉积(CVD)和等离子体增强型化学汽相沉积(PECVD))形成。还应当指出的是，本领域的技术人员应该理解，层间介电层182可以进一步包括多个介电层。
底部金属化层172和顶部金属化层152形成在层间介电层182上。如图1所示，底部金属化层172包括第一金属线174。同样地，顶部金属化层152包括第二金属线162。金属线174和162由金属材料(如，铜或铜合金等)形成。应当指出的是，图1示出了底部金属化层172和顶部金属化层152，但本领域技术人员应该理解，一个或多个金属间介电层(未示出)和相关联的金属化层(未示出)形成在底部金属化层172和顶部金属化层152之间。通常，使用一个或多个金属间介电层和相关联的金属化层实现衬底192上电路的彼此互连并且提供外部电连接。
钝化层142形成在顶部金属化层152上。根据实施例，钝化层142由非有机材料(如，未掺杂的硅酸盐玻璃、氮化硅、氧化硅等)形成。铝焊盘160可以形成在钝化层142的顶部上。此外，铝焊盘160可以通过通孔164连接到顶部金属线162。根据实施例，通孔164被金属材料(如，铜、铜合金、铝、银、金及其任意组合)填充。通孔164可以通过合适的技术(如，CVD)形成。可选地，通孔164可以通过溅射、电镀等形成。
第一聚合物层132形成在钝化层142上。第一聚合物层132由聚合物材料(如，环氧树脂、聚酰亚胺等)形成。第一聚合物层132可以由本领域已知的任何合适的方法(如，旋涂)形成。再分配层166形成在第一聚合物层132上。如图1所示，再分配层166将铝焊盘160与半导体管芯100的顶面相连接。更具体地，再分配层166提供导电路径，该导电路径在金属线(例如，金属线162)和半导体管芯100的顶面(例如，UBM 116)之间。
第二聚合物层122形成在第一聚合物层132上。如图1所示，再分配层166和再分配层164嵌入到第二聚合物层122中。再分配层166和再分配层164由金属材料(如，铝、铝合金、铜、铜合金等)形成。第二聚合物层122被图案化，以形成多个开口。而且，多个凸块下金属(UBM)结构(例如，UBM 116)形成在开口上。UBM结构(例如，UBM116)用于将再分配层(例如，再分配层166)与多个输入和输出端子(例如，凸块106和104)相连接。每个UBM结构可以进一步包括多个子层(如，晶种层(未示出)、粘附层(未示出)等)。UBM结构可以通过的任何合适的技术(如，蒸发、电镀等)形成。
凸块104和106分别形成在UBM结构114和116上。根据实施例，凸块104和106是焊球。在整个说明书中，为简单起见，凸块104和106分别可选地称为焊球104和106。焊球104和106可以由任意合适的材料形成。根据实施例，焊球104和106包括SAC 405。SAC 405包括95.5％的锡、4.0％的银和0.5％的同。
如图1所示，在回流工艺之后，焊球104和106均被加热，随后融化，以连接半导体管芯100和印刷电路板(PCB)102。应该指出，PCB 102和半导体管芯100可以具有与焊球104和106不同的热膨胀系数。因而，不同的热膨胀系数可能会造成焊球104、106和PCB 102之间的焊点处具有较大的应力和塑性应变。而且，焊球104和106上的多个温度循环所积累的大的应力和塑性应变可能会导致在焊球104、106和PCB 102之间的焊点区产生裂纹。
为了重新分配上述应力和塑性应变使其均匀分布在整个焊球(例如，焊球104)的球体上，半导体管芯100的顶面上的焊球可以被配置为内部区域具有大焊球(例如，焊球106)以及外部区域具有小焊球(例如，焊球104)。根据实施例，半导体管芯100的顶视图示出了焊球的布局。在顶视图中，半导体管芯100具有水平长度W1和垂直长度W2。
在半导体管芯100的顶面上，多种焊球可以形成在相应的UBM结构上。如在图1所示，多个小焊球(例如，焊球104)形成在半导体管芯100的外部区域。同样地，多个大焊球(例如，焊球106)形成在半导体管芯100的内部区域。值得注意的是，根据实施例，“小焊球”的直径小于“大焊球”的直径的90％。换句话说，当大焊球的直径是大约300um时，相应的小焊球的直径等于或小于270um。使小焊料球形成在半导体管芯100的外部区域上的有益特征之一是，小焊球使得半导体管芯100具有细间距封装件以及额外的输入和输出端子。
而且，根据实施例，回流焊工艺之前的小焊球的直径应大于回流工艺之后的大焊球的高度。例如，在回流工艺之前，大焊球和小焊球的直径分别为250um和225um。在回流工艺之后，两个焊球都熔化并且夹在半导体管芯100的顶面和PCB 102之间。回流工艺之后的大焊球的高度是大约210.5um。因此，通过控制PCB 102和半导体管芯100之间的距离，焊球可以形成可靠的焊点。
可以用多种方式来界定内部区域和外部区域之间的边界。根据实施例，外部区域包括四个边缘区域。每个边缘区域都具有宽度(例如，W3和W4)，该宽度大约等于或小于相应半导体管芯100的长度(例如，W1和W2)的20％。通过在半导体管芯100顶面上采用不同的焊球，在回流工艺之后，外凸块(例如，焊球104)比其相应的内凸块(例如，焊球106)更薄。因此，由PCB 102和半导体管芯100之间的热膨胀差所产生的应力可以被重新分配的焊球104的球体上，从而减少产生裂纹的可能性。半导体管芯100的外部区域具有小焊球的有益特征之一是，小焊球有助于重新分配应力和应变，从而改进热循环的可靠性。根据实施例，在半导体管芯100和印刷电路板102之间的焊点处的温度循环测试(TCT)的一个周期过程中，累计塑性应变可减少16％。
图2示出了根据另一个实施例具有芯片级封装部件的凸块结构的顶视图和截面图。如图2所示，半导体芯200的结构与图1所示的半导体管芯100的结构类似，但是半导体管芯200的UBM结构(例如，UBM结构216)与半导体管芯100的UBM结构(例如，UBM结构116)不同。如顶视图(移除焊球以显示UBM的差异)所示，在半导体管芯200的外部区域中设置多个大的UBM结构(例如，UBM结构216)。与此相反，在内部区域中设置多个小的UBM结构。根据实施例，小的UBM结构(例如，UBM结构214)的直径小于或等于大的UBM结构(例如，UBM结构216)的直径的90％。
根据实施例，具有大致相同尺寸的焊球(例如，焊料204和206)形成在具有不同直径的UBM结构上。因此，在回流工艺之后，不同区域的焊球可以具有不同的形状。更具体地，与在小的UBM结构上形成焊球相比，形成在大的UBM结构上的焊球在回流工艺中被拉伸。如图2所示，形成在外部区域上的焊球(例如，焊球206)可以具有沙漏形状。相比之下，形成在内部区域上的焊球(例如，焊球204)可以具有球形。这种夹在半导体管芯200和PCB 102之间的沙漏形的焊料柱有助于减少半导体管芯200和PCB 102之间的焊点处的应力。
图3示出了根据又一个实施例具有芯片级封装部件的凸块结构的顶视图和截面图。图3所示的半导体管芯300的结构与图1所示的半导体管芯100相似，除了半导体管芯300的较小的焊球的分布不同于半导体管芯100的较小的焊球的分布。如顶视图所示，四个小焊球形成在集成芯片的芯片300的四角上。相比之下，大焊球形成在内部区域中。基于上述关于图1的类似原因，半导体管芯300的小焊球有助于减少小焊球和PCB 102之间的焊点处的应力和应变，以减少产生裂纹的可能性，并提高热循环的可靠性。
尽管已经详细地描述了本发明及其优势，但应该理解，可以在不背离所附权利要求限定的本发明主旨和范围的情况下，做各种不同的改变，替换和更改。
而且，本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员应理解，通过本发明，现有的或今后开发的用于执行与根据本发明所采用的所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造，材料组分、装置、方法或步骤根据本发明可以被使用。因此，所附权利要求应该包括在这样的工艺、机器、制造、材料组分、装置、方法或步骤的范围内。

Claims (10)

1.一个器件包括：
半导体管芯；
具有第一直径的第一凸块，所述第一凸块在所述半导体管芯上的第一区域上；以及
具有第二直径的第二凸块，所述第二凸块在所述半导体管芯上的第二区域上，其中所述第二直径不同于所述第一直径。
2.根据权利要求1所述的器件，其中，所述第一直径大于所述第二直径。
3.根据权利要求1所述的器件，其中：
所述第一区域是所述半导体管芯的内部区域；以及
所述第二区域是所述半导体管芯的外部区域。
4.根据权利要求3所述的器件，其中，所述外部区域的宽度大约等于或小于所述内部区域的宽度的三分之一。
5.根据权利要求4所述的器件，其中；
所述第一区域是所述半导体管芯的内部区域；以及
所述第二区域是所述半导体管芯的角部。
6.根据权利要求1所述的器件，其中：
所述第一凸块形成在所述第一凸块下金属结构上；以及
所述第二凸块形成在所述第二凸块下金属结构上，其中所述第一凸块下金属结构不同于所述第二凸块下金属结构。
7.根据权利要求6所述的器件，其中，所述第二凸块下金属结构的直径大于第一凸块下金属结构的直径。
8.一个器件包括：
半导体管芯；
具有第一直径和第一高度的第一凸块，所述第一凸块在邻近所述半导体管芯的边缘处形成；以及
具有第二直径和第二高度的第二凸块，所述第二凸块在不邻近所述半导体管芯的边缘处形成，其中所述第二凸块不同于所述第一凸块。
9.根据权利要求8所述的器件，其中，所述第一直径大于所述第二直径。
10.一种结构包括：
半导体管芯；
具有第一直径的第一凸块下金属结构，所述第一凸块下金属结构形成在所述半导体管芯的外部区域上；以及
具有第二直径的第二凸块下金属结构，所述第二凸块下金属结构形成在所述半导体管芯的内部区域上，其中所述第一凸块下金属结构不同于所述第二凸块下金属结构。
CN201210041605.6A 2011-11-11 2012-02-21 用于芯片级封装的凸块 Active CN103107152B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/294,859 US20130119532A1 (en) 2011-11-11 2011-11-11 Bumps for Chip Scale Packaging
US13/294,859 2011-11-11

Publications (2)

Publication Number Publication Date
CN103107152A true CN103107152A (zh) 2013-05-15
CN103107152B CN103107152B (zh) 2016-01-20

Family

ID=48279807

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201210041605.6A Active CN103107152B (zh) 2011-11-11 2012-02-21 用于芯片级封装的凸块

Country Status (2)

Country Link
US (2) US20130119532A1 (zh)
CN (1) CN103107152B (zh)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106847762A (zh) * 2015-12-03 2017-06-13 三星电子株式会社 半导体装置和半导体封装件
CN109637990A (zh) * 2018-11-16 2019-04-16 北京时代民芯科技有限公司 带不同直径凸点的晶圆制备方法
CN109727935A (zh) * 2016-04-08 2019-05-07 Oppo广东移动通信有限公司 一种芯片封装结构、终端设备及方法
CN110379792A (zh) * 2019-07-23 2019-10-25 中新国际联合研究院 用于温度循环的电子组件焊点
CN110660771A (zh) * 2019-10-09 2020-01-07 中新国际联合研究院 一种半导体封装中焊点形状的优化结构
CN110854029A (zh) * 2019-11-08 2020-02-28 中新国际联合研究院 自然形成的粗短沙漏形焊点的设计和成形工艺

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9768137B2 (en) * 2012-04-30 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Stud bump structure for semiconductor package assemblies
US8742578B2 (en) * 2012-07-19 2014-06-03 International Business Machines Corporation Solder volume compensation with C4 process
US8759210B2 (en) 2012-07-19 2014-06-24 International Business Machines Corporation Control of silver in C4 metallurgy with plating process
US8877554B2 (en) 2013-03-15 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices
US20150279793A1 (en) * 2014-03-27 2015-10-01 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
KR102319186B1 (ko) 2015-06-12 2021-10-28 삼성전자주식회사 반도체 장치 및 반도체 장치의 제조 방법
KR102456667B1 (ko) 2015-09-17 2022-10-20 삼성전자주식회사 재배선 패드를 갖는 반도체 소자
US9799618B1 (en) 2016-10-12 2017-10-24 International Business Machines Corporation Mixed UBM and mixed pitch on a single die
US10388730B2 (en) * 2017-03-31 2019-08-20 Palo Alto Research Center Incorporated Plurality of electrodes on a substrate having different range of spacing
KR102588125B1 (ko) 2018-02-02 2023-10-11 삼성전자주식회사 반도체 장치
KR102499476B1 (ko) 2019-08-19 2023-02-13 삼성전자주식회사 반도체 패키지
US11581280B2 (en) 2019-12-27 2023-02-14 Stmicroelectronics Pte Ltd WLCSP package with different solder volumes
JP7078868B2 (ja) * 2020-10-13 2022-06-01 日亜化学工業株式会社 発光装置の製造方法
US11784172B2 (en) * 2021-02-12 2023-10-10 Taiwan Semiconductor Manufacturing Hsinchu, Co., Ltd. Deep partition power delivery with deep trench capacitor
US12021048B2 (en) * 2021-08-30 2024-06-25 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5214308A (en) * 1990-01-23 1993-05-25 Sumitomo Electric Industries, Ltd. Substrate for packaging a semiconductor device
US5569960A (en) * 1994-05-16 1996-10-29 Hitachi, Ltd. Electronic component, electronic component assembly and electronic component unit
CN1237791A (zh) * 1998-06-02 1999-12-08 三菱电机株式会社 半导体器件
US6107685A (en) * 1998-09-25 2000-08-22 Sony Corporation Semiconductor part and fabrication method thereof, and structure and method for mounting semiconductor part
CN1299518A (zh) * 1998-09-28 2001-06-13 株式会社日立制作所 半导体封装及其倒装芯片接合法
US20050127508A1 (en) * 2003-12-12 2005-06-16 In-Young Lee Solder bump structure for flip chip package and method for manufacturing the same
US20080224283A1 (en) * 2005-09-20 2008-09-18 Siliconware Precision Industries Co., Ltd. Leadframe-based semiconductor package and fabrication method thereof
US7564130B1 (en) * 2007-07-06 2009-07-21 National Semiconductor Corporation Power micro surface-mount device package
US20090250813A1 (en) * 2005-09-23 2009-10-08 Yaojian Lin Integrated circuit solder bumping system

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3846611B2 (ja) * 1998-09-25 2006-11-15 ソニー株式会社 実装用半導体部品、実装構造及び実装方法
US20030001286A1 (en) * 2000-01-28 2003-01-02 Ryoichi Kajiwara Semiconductor package and flip chip bonding method therein
US8836146B2 (en) * 2006-03-02 2014-09-16 Qualcomm Incorporated Chip package and method for fabricating the same

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5214308A (en) * 1990-01-23 1993-05-25 Sumitomo Electric Industries, Ltd. Substrate for packaging a semiconductor device
US5569960A (en) * 1994-05-16 1996-10-29 Hitachi, Ltd. Electronic component, electronic component assembly and electronic component unit
CN1237791A (zh) * 1998-06-02 1999-12-08 三菱电机株式会社 半导体器件
US6107685A (en) * 1998-09-25 2000-08-22 Sony Corporation Semiconductor part and fabrication method thereof, and structure and method for mounting semiconductor part
CN1299518A (zh) * 1998-09-28 2001-06-13 株式会社日立制作所 半导体封装及其倒装芯片接合法
US20050127508A1 (en) * 2003-12-12 2005-06-16 In-Young Lee Solder bump structure for flip chip package and method for manufacturing the same
US20080224283A1 (en) * 2005-09-20 2008-09-18 Siliconware Precision Industries Co., Ltd. Leadframe-based semiconductor package and fabrication method thereof
US20090250813A1 (en) * 2005-09-23 2009-10-08 Yaojian Lin Integrated circuit solder bumping system
US7564130B1 (en) * 2007-07-06 2009-07-21 National Semiconductor Corporation Power micro surface-mount device package

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106847762A (zh) * 2015-12-03 2017-06-13 三星电子株式会社 半导体装置和半导体封装件
CN109727935A (zh) * 2016-04-08 2019-05-07 Oppo广东移动通信有限公司 一种芯片封装结构、终端设备及方法
CN109637990A (zh) * 2018-11-16 2019-04-16 北京时代民芯科技有限公司 带不同直径凸点的晶圆制备方法
CN109637990B (zh) * 2018-11-16 2020-12-08 北京时代民芯科技有限公司 带不同直径凸点的晶圆制备方法
CN110379792A (zh) * 2019-07-23 2019-10-25 中新国际联合研究院 用于温度循环的电子组件焊点
CN110379792B (zh) * 2019-07-23 2021-07-20 中新国际联合研究院 用于温度循环的电子组件焊点
CN110660771A (zh) * 2019-10-09 2020-01-07 中新国际联合研究院 一种半导体封装中焊点形状的优化结构
CN110854029A (zh) * 2019-11-08 2020-02-28 中新国际联合研究院 自然形成的粗短沙漏形焊点的设计和成形工艺
CN110854029B (zh) * 2019-11-08 2021-04-13 中新国际联合研究院 自然形成的粗短沙漏形焊点的成形工艺

Also Published As

Publication number Publication date
US9553065B2 (en) 2017-01-24
US20140191394A1 (en) 2014-07-10
CN103107152B (zh) 2016-01-20
US20130119532A1 (en) 2013-05-16

Similar Documents

Publication Publication Date Title
CN103107152B (zh) 用于芯片级封装的凸块
TWI502667B (zh) 半導體元件的接合結構及半導體元件的製造方法
US7242081B1 (en) Stacked package structure
US20180366432A1 (en) Semiconductor device and manufacturing method thereof
CN103855115B (zh) 衬底焊盘结构
TWI462397B (zh) 電連接器結構及其製造方法及半導體裝置
US11211332B2 (en) Molded die last chip combination
KR101366455B1 (ko) 반도체 장치, 패키징 방법 및 구조
CN102931173A (zh) 多芯片晶圆级封装
US20070164447A1 (en) Semiconductor package and fabricating method thereof
TWI622107B (zh) 具有嵌入在延伸基板和底部基板之間的半導體晶粒的半導體裝置
CN103378049B (zh) 用于ic封装的应力减小结构
WO2011086613A1 (ja) 半導体装置及びその製造方法
TWI503906B (zh) 半導體結構、半導體裝置及半導體裝置的製造方法
CN104051355A (zh) 层叠封装结构及其形成方法
CN104051390A (zh) 具有模制开口凸块的叠层封装连结结构
US20140170850A1 (en) UBM Structures for Wafer Level Chip Scale Packaging
US20130256915A1 (en) Packaging substrate, semiconductor package and fabrication method thereof
US9576888B2 (en) Package on-package joint structure with molding open bumps
TWI556394B (zh) 半導體結構及其形成方法及半導體裝置
US9478482B2 (en) Offset integrated circuit packaging interconnects
TWI638411B (zh) 電子封裝件之製法
US9355928B2 (en) Package-on-package structure

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant