CN103066059B - 具有穿过衬底通路(tsv)的半导体结构及其形成方法 - Google Patents

具有穿过衬底通路(tsv)的半导体结构及其形成方法 Download PDF

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CN103066059B
CN103066059B CN201210407786.XA CN201210407786A CN103066059B CN 103066059 B CN103066059 B CN 103066059B CN 201210407786 A CN201210407786 A CN 201210407786A CN 103066059 B CN103066059 B CN 103066059B
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doped region
substrate
tsv
depth
concentration
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CN103066059A (zh
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T·B·涛
J·E·卡亚斯
H·A·鲁尔达
P·W·桑德斯
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NXP USA Inc
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NXP USA Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/20—Inductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0221—Manufacture or treatment of FETs having insulated gates [IGFET] having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/254—Source or drain electrodes for field-effect devices for lateral devices wherein the source or drain electrodes extend entirely through the semiconductor bodies, e.g. via-holes for back side contacts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/256—Source or drain electrodes for field-effect devices for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/50—PIN diodes 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0261—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias characterised by the filling method or the material of the conductive fill
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/212—Top-view shapes or dispositions, e.g. top-view layouts of the vias
    • H10W20/2125—Top-view shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/213—Cross-sectional shapes or dispositions
    • H10W20/2134—TSVs extending from the semiconductor wafer into back-end-of-line layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/222—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/497—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/20—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]

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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
CN201210407786.XA 2011-10-24 2012-10-24 具有穿过衬底通路(tsv)的半导体结构及其形成方法 Active CN103066059B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/279,776 US8518764B2 (en) 2011-10-24 2011-10-24 Semiconductor structure having a through substrate via (TSV) and method for forming
US13/279,776 2011-10-24

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CN103066059A CN103066059A (zh) 2013-04-24
CN103066059B true CN103066059B (zh) 2018-05-22

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US (1) US8518764B2 (enExample)
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Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9275933B2 (en) * 2012-06-19 2016-03-01 United Microelectronics Corp. Semiconductor device
US9196671B2 (en) * 2012-11-02 2015-11-24 International Business Machines Corporation Integrated decoupling capacitor utilizing through-silicon via
KR101968351B1 (ko) * 2013-01-28 2019-08-13 서울대학교산학협력단 반도체 장치 및 그 제조 방법
US8927427B2 (en) * 2013-04-29 2015-01-06 International Business Machines Corporation Anticipatory implant for TSV
JP6219140B2 (ja) * 2013-11-22 2017-10-25 ルネサスエレクトロニクス株式会社 半導体装置
US9373613B2 (en) * 2013-12-31 2016-06-21 Skyworks Solutions, Inc. Amplifier voltage limiting using punch-through effect
JP6305067B2 (ja) 2014-01-09 2018-04-04 株式会社東芝 半導体装置の製造方法
EP3118892B1 (en) * 2014-03-12 2018-05-02 Thruchip Japan Inc. Laminated semiconductor integrated circuit device
CN104392993A (zh) * 2014-12-08 2015-03-04 江苏博普电子科技有限责任公司 一种基于高阻硅衬底的ldmos mmic芯片
US10242932B2 (en) 2016-06-24 2019-03-26 Infineon Technologies Ag LDMOS transistor and method
US9960229B2 (en) 2016-06-24 2018-05-01 Infineon Technologies Ag Semiconductor device including a LDMOS transistor
US9875933B2 (en) 2016-06-24 2018-01-23 Infineon Technologies Ag Substrate and method including forming a via comprising a conductive liner layer and conductive plug having different microstructures
US10622284B2 (en) 2016-06-24 2020-04-14 Infineon Technologies Ag LDMOS transistor and method
US10050139B2 (en) 2016-06-24 2018-08-14 Infineon Technologies Ag Semiconductor device including a LDMOS transistor and method
WO2018004662A1 (en) * 2016-07-01 2018-01-04 Intel Corporation Methods and apparatus to prevent through-silicon-via shorting
US10020270B2 (en) * 2016-09-29 2018-07-10 Infineon Technologies Ag Semiconductor device including a LDMOS transistor, monolithic microwave integrated circuit and method
JP7341927B2 (ja) 2020-03-12 2023-09-11 キオクシア株式会社 半導体記憶装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101183683A (zh) * 2006-11-16 2008-05-21 国际商业机器公司 用于减小mosfet器件中的浮体效应的方法和结构
CN102037562A (zh) * 2008-02-27 2011-04-27 先进模拟科技公司 隔离的晶体管和二极管、用于半导体管芯的隔离和终端结构
CN102148251A (zh) * 2011-01-10 2011-08-10 电子科技大学 Soi横向mosfet器件和集成电路

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4070485B2 (ja) * 2001-05-09 2008-04-02 株式会社東芝 半導体装置
JP2002343968A (ja) * 2001-05-14 2002-11-29 Toshiba Corp 半導体装置、半導体装置の製造方法
US6521923B1 (en) * 2002-05-25 2003-02-18 Sirenza Microdevices, Inc. Microwave field effect transistor structure on silicon carbide substrate
US6949445B2 (en) 2003-03-12 2005-09-27 Micron Technology, Inc. Method of forming angled implant for trench isolation
US7102184B2 (en) 2003-06-16 2006-09-05 Micron Technology, Inc. Image device and photodiode structure
US7087959B2 (en) * 2004-08-18 2006-08-08 Agere Systems Inc. Metal-oxide-semiconductor device having an enhanced shielding structure
US7843064B2 (en) 2007-12-21 2010-11-30 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and process for the formation of TSVs
JP2009170747A (ja) * 2008-01-18 2009-07-30 Toshiba Corp 半導体装置及びその製造方法
US7960781B2 (en) * 2008-09-08 2011-06-14 Semiconductor Components Industries, Llc Semiconductor device having vertical charge-compensated structure and sub-surface connecting layer and method
US7884016B2 (en) 2009-02-12 2011-02-08 Asm International, N.V. Liner materials and related processes for 3-D integration
JP2011009595A (ja) * 2009-06-29 2011-01-13 Renesas Electronics Corp 半導体装置および半導体装置の製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101183683A (zh) * 2006-11-16 2008-05-21 国际商业机器公司 用于减小mosfet器件中的浮体效应的方法和结构
CN102037562A (zh) * 2008-02-27 2011-04-27 先进模拟科技公司 隔离的晶体管和二极管、用于半导体管芯的隔离和终端结构
CN102148251A (zh) * 2011-01-10 2011-08-10 电子科技大学 Soi横向mosfet器件和集成电路

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JP2013093579A (ja) 2013-05-16
JP6222800B2 (ja) 2017-11-01
CN103066059A (zh) 2013-04-24
US8518764B2 (en) 2013-08-27

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