CN103050509B - 集成高低压器件的半导体芯片 - Google Patents

集成高低压器件的半导体芯片 Download PDF

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CN103050509B
CN103050509B CN201210346070.3A CN201210346070A CN103050509B CN 103050509 B CN103050509 B CN 103050509B CN 201210346070 A CN201210346070 A CN 201210346070A CN 103050509 B CN103050509 B CN 103050509B
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epitaxial loayer
conduction type
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semiconductor chip
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CN103050509A (zh
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秀明土子
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Alpha and Omega Semiconductor Cayman Ltd
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Alpha and Omega Semiconductor Inc
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Abstract

本发明涉及一种由高压器件和低压器件构成的半导体芯片。所制备的芯片具有多种不同的配置。例如，该半导体芯片可以包含NPN双极晶体管、PNP双极晶体管、二极管、N通道DMOS晶体管以及类似器件。第一掺杂阱配置成DMOS晶体管、P通道DMOS晶体管以及类似器件的基极。这些及其他实施例将在下文中详细介绍。

Description

集成高低压器件的半导体芯片
技术领域
本发明涉及高压半导体器件及其制备工艺，特别是，在现有的半导体器件工艺流程中增加高压器件的模块化技术。
背景技术
为了满足新型应用的需要，具有较高额定电压的器件通常必须与现有器件集成在一块现有器件中。将电压较高的器件集成在现有的低压器件中，通常需要对已验证过的现有的低压器件制备工艺流程和/或状态做许多改动，致使现有低压器件的性能降低，从而必须升级器件模块。为了避免新型技术改进带来的冗长设计周期以及高成本，我们研究的重点就是仅需对现有的低压器件工艺做些微调，从而使对现有低压器件性能的影响降至最低。
一般来说，在BCD（双极CMOSDMOS）或BiCMOS（双极CMOS）工艺中，最高的工作电压受到P至N结的垂直结构的穿通击穿的局限。这种垂直结击穿是外延层厚度、掺杂浓度和结深度的函数。如图1所示，表示一个形成在半导体芯片中的现有器件300的示例，现有器件300含有一个厚度为43的n-型外延层18沉积在P衬底14上。器件300的大致结构是，多个N-阱22和P-阱26和48位于N-外延层中。掩埋的P区46从N-外延层底部开始，向下延伸到P-阱48的底部边缘中，并且合并在一起。掩埋的P区也向下延伸到衬底材料14中，从而使器件300与制备其他器件的半导体芯片的其他区域绝缘。器件300还包含一个在P-阱26下方的N掩埋区35，避免在P-阱和P衬底之间穿通，P衬底限制了器件300最大的工作电压。利用一定厚度的外延层18，并且控制P-阱26的深度45，使器件300的性能达到最优，P-阱26的底部和掩埋的N区35的顶部之间的垂直距离47限制了垂直击穿电压，从而当横向击穿控制因子49（即掩埋P区46和N掩埋区35之间的横向距离）足够大，使横向击穿电压远大于垂直击穿电压时，限制器件300的工作电压。制备工艺从衬底材料14开始，然后分别在区域35和46中植入离子。在衬底材料14上方沉积外延层18，并且制备多个从外延层顶面开始向下延伸的N-阱和P-阱。通过额外的步骤，制备双极晶体管或MOSFET等具体功能的器件。当一个工作电压较高的器件需要集成在同一衬底上的不同区域中的情况下，一种提高P至N垂直击穿电压的方法就是增加外延层18的厚度。如果制备器件300的工艺和状态仍然保持不变的话，这将会影响现有器件300的性能和独立性。
另一种方法就是引入一个较轻的掺杂层，以降低掺杂浓度和浅P阱结。例如，HideakiTsuchiko在美国专利7019377中提出了一种集成电路，包含一个高压肖特基势垒二极管以及一个低压器件。肖特基势垒二极管含有一个轻掺杂的浅P-阱，作为保护环，同时利用标准的、较重掺杂的、较深的p-阱，制备低压器件。通过含有轻掺杂p-阱、标准p-阱以及增厚的N-外延层的工艺，提高高压器件的击穿电压以及最大工作电压。每种方法都能使击穿电压升高15V至30V。使用这两种方法的肖特基势垒二极管，可以使击穿电压升高30V至60V，而不会严重影响其他器件和结构的性能。
这两种方法和器件布局的同时使用，可以在同一芯片上集成高压和低压器件。然而，这些方法经常会对现有器件的性能有轻微影响。某些器件需要对SPICE模块稍作调整。尤其是对增大N-外延层的厚度有一定的限制。如果大幅增加N-外延层厚度的话，P-型掩埋区46的向上扩散和p阱48的向下扩散之间的绝缘连接就会被削弱或中断，致使不完整的器件绝缘。因此，要在低压芯片内集成高压器件，必须提出新的技术，使得仅需在现有的低压工艺流程中增加一些步骤，就能在低压芯片内集成高压器件，而不会对低压器件的性能造成影响。
发明内容
本发明提供一种集成高低压器件的半导体芯片，能在低压芯片内集成高压器件，而不会对低压器件的性能造成影响。
为实现上述目的，本发明提供一种由高压器件和低压器件构成的半导体芯片。该半导体芯片包含：一个第一导电类型的衬底层；一个在衬底层顶面上的第一导电类型的第一外延层；一个在第一外延层顶面上的与第一导电类型相反的第二导电类型的第二外延层；一个在高压器件区域中的第二导电类型的深掩埋植入区；一个在低压器件区域中的第二导电类型的掩埋植入区；一个从第二外延层顶面开始延伸到深掩埋植入区上方的第一导电类型的第一掺杂阱；以及一个从掩埋植入区上方的第二外延层顶面开始的第一导电类型的第二掺杂阱。
一种由第一器件构成的半导体芯片，其特点是，该半导体芯片还包含：
一个第一导电类型的半导体衬底层；
一个第一导电类型的第一外延层，该第一外延层在衬底层上方；
一个与第一导电类型相反的第二导电类型的第二外延层，该第二外延层在第一外延层上方；
一个第二导电类型的深掩埋植入区，该深掩埋植入区在第一器件的区域中；
一个第一导电类型的第一掺杂阱，其从第二外延层的顶面开始，向下延伸到深掩埋植入区上方；
其中上述第二导电类型的深掩埋植入区还包含一个第二导电类型的深掩埋重掺杂区，以及一个第二导电类型的深掩埋轻掺杂区，该深掩埋轻掺杂区包围着所述的深掩埋重掺杂区，并从衬底的深度开始延伸到第一外延层的顶面。
一种半导体芯片，其是由沉积在上方的高压器件和低压器件构成，其特点是，该半导体芯片还包含：
一个第一导电类型的衬底层；
一个第一导电类型的第一外延层，该第一外延层在衬底层的顶面上，第一外延层的掺杂浓度与衬底大致相同；
一个与第一导电类型相反的第二导电类型的第二外延层，该第二外延层在第一外延层的顶面上；
一个第二导电类型的深掩埋植入区，该深掩埋植入区在高压器件的区域中，该深掩埋植入区包含一个第二导电类型的深掩埋重掺杂区，以及第二导电类型的深掩埋轻掺杂区，该深掩埋轻掺杂区包围着所述的深掩埋重掺杂区；
一个第二导电类型的掩埋植入区，该掩埋植入区在低压器件的区域中；
一个第一导电类型的第一掺杂阱，其从第二外延层的顶面开始，延伸到深掩埋植入区上方；以及一个第一导电类型的第二掺杂阱，其从第二外延层的顶面开始，延伸到掩埋植入区上方；以及，
绝缘区，其包围着高压器件和所述的低压器件的有源区。
所制备的芯片具有多种不同的配置。例如，该半导体芯片可以包含NPN双极晶体管、PNP双极晶体管、二极管、N通道DMOS晶体管以及类似器件。本发明的这些及其他实施例将在下文中详细介绍。
附图说明
图1为依据本发明的一个方面，一种制备在衬底上的现有器件的剖面图；
图2为依据本发明的一个方面，一种工作电压较高的器件与图1所示的工作电压较低的器件一起制备在一个公共衬底上的剖面图；
图3为一种图2所示结构的制备方法的流程图，以及；
图4-10为图2所示的有源器件在图3所示的制备工艺的不同步骤中的剖面图。
图11为依据本发明，一种工作电压较高的垂直NPN双极晶体管的剖面图；
图12为依据本发明，一种工作电压较高的横向PNP双极晶体管的剖面图；
图13为依据本发明，一种工作电压较高的PN二极管的剖面图；
图14为依据本发明，一种工作电压较高的横向N-通道DMOS的剖面图；
图15为依据本发明，一种工作电压较高的横向P-通道DMOS的剖面图；
图16为依据本发明，一种工作电压较高的带有三重RESURF的横向N-通道DMOS的剖面图。
具体实施方式
如图2所示，依据本发明，额定工作电压不同的第一和第二器件10和11形成在具有半导体材料14的公共半导体芯片上，第一外延层16堆栈在衬底材料14上方，第二外延层18堆栈在第一外延层16上方。外延层16的掺杂浓度与衬底材料14大致相同。衬底14和外延层16首选p-型。形成在外延层1上方的第二外延层18首选n-型。层16和18限定了一个层堆栈12。
器件10的有源区20形成在n-型外延层18中。器件10的大致结构是，多个N-阱22和P-阱26和48位于N-外延层中。阱22中的n-型掺杂物浓度高于层18中的n-型掺杂物浓度。P-型阱26中的掺杂物浓度高于外延层16和衬底14中。N-型掺杂物的掩埋区，也称为掩埋区35，在p-外延层16和n-外延层18之间延伸，可控的垂直间距47小于P-阱26的底部和掩埋的N区35之间的外延层18的厚度。掩埋的N区35局限于p-外延层1和n-外延层18之间的交界面附近的区域中，使得掩埋区35中的n-型掺杂物浓度高于层18中。
绝缘区40沉积在有源区20和掩埋区35的对边上。绝缘区40形成于多个区，这些区中所具有的p-型掺杂物浓度高于衬底14或外延层16中。确切地说，每个绝缘区40都含有一个高压P阱（HVPW）48，位于n-型外延层18的顶部，并且与p-型掩埋区46的掩埋区重叠，在n-型外延层18之间延伸到p-型外延层16。除了器件10具有一个额外的外延层16形成在衬底上方之外，其他都与图1所示的器件300相同。由于外延层16的掺杂浓度与衬底材料14相同，因此器件10的性能与器件300相同，外延层16可以被视为是衬底材料14的延伸物。制备器件300的现有的制备工艺和状态都可以整体转移给制备器件10的工艺模块。
依据本发明，器件11也形成在衬底14和层堆栈12中。器件11包含一个有源区120，形成在层18中。器件11的大体结构是，多个N-阱122和P-阱126和148都在N-外延层18中。阱122中的n-型掺杂物浓度高于阱122外部的层18中的区。阱126的P-型掺杂物浓度高于层16和衬底14中的P-型掺杂物浓度。一个n-型掺杂物的深掩埋区，也称为深掩埋区134，在衬底14和层堆栈12之间延伸。深掩埋区134有两种不同的种类，包含一个重掺杂的第一n-型部分（称为深掩埋重掺杂区136），以及一个轻掺杂的第二n-型部分（称为深掩埋轻掺杂区134），第二部分134包围着第一部分136。最好是将第一n-型部分136限制在衬底材料14和p-外延层16之间的交界面附近，使重掺杂第一n-型部分136中的n-型掺杂物浓度高于层16中。第二n-型部分向上延伸，触及第二外延层18，最适宜的掺杂浓度与层18相同。
对于给定的温度，部分134中的第二n-型掺杂物扩散速度大于部分136中的第一n-型掺杂物。在本例中，区域136中的掺杂物为锑或砷，区域138中的掺杂物为磷。
绝缘区140沉积在有源区120和深掩埋区134的对边上。绝缘区140形成于多个区域，这些区中所具有的p-型掺杂物浓度高于衬底14或层堆栈12的层16中。确切地说，每个绝缘区140都由三个p-型掺杂浓度的重叠区144、146和148构成。第一掩埋区144在衬底14和第一外延层16之间延伸。第二掩埋区146与掩埋区144重叠，并且在第一外延层16和第二外延层18之间延伸。第三阱148与第二掩埋区146重叠，并且从第二层18的表面50开始，向第一层1延伸。应明确，绝缘区140的作用是使有源区120与邻近器件的有源区绝缘，邻近器件的有源区表示为形成在衬底14上和层堆栈12中的有源区20。
器件11要考虑三个击穿电压。其一，掩埋区134和136到有源区120外面的衬底材料14。该击穿电压可以通过134、136以及14的掺杂浓度和134和136的结构来控制。其二，有源区120中的横向击穿电压可以通过区域134和136以及绝缘区140之间的水平距离52、以及区域134、136、14、16和140的掺杂浓度和结构来控制。其三，有源区120中的垂直击穿电压可以通过区域136和126之间的垂直距离51、以及区域134、136、18和126的掺杂浓度和结构来控制。将绝缘区140与有源器件区120分开，可以轻松地使第二横向击穿电压远高于垂直击穿电压。因此，器件120最大的工作电压受到第三垂直击穿的限制。
为了在半导体芯片上制备器件10和11，在步骤200处，要制备一种p-型衬底14，深掩埋区100和101形成在衬底14顶面上的高压器件区中，如图3-6所示。利用人们熟知的植入和掩膜工艺，植入掺杂物，获得所需的掺杂浓度。确切地说，深掩埋区101包含两种不同类型的n-型掺杂物，在特定的温度下，具有不同速度的扩散系数。在本例中，第一n-型掺杂物为锑或砷，第二掺杂物为磷，两者通过两步植入，均植入到衬底14上的同一个深掩埋区101中。深掩埋区100含有一定浓度的p-型掺杂物。低压器件区被光致抗蚀剂覆盖，避免在该步骤中植入离子。
如图3和图7所示，在步骤202处，外延层16生长在整个区域的衬底14上方。外延层16最好是与衬底14具有相同的p-型掺杂物以及相同的掺杂浓度。在步骤204处，掩埋区104，如图8所示，形成在外延层16上，以及工作电压较高的区域中的深掩埋区100上方。在步骤204中，掩埋区90和92形成在外延层16中，有利于制备工作电压较低的器件10。掩埋区90和104包含p-型掺杂物，掩埋区92包含n-型掺杂物。区域90和104中的掺杂浓度高于层16的剩余区域中的掺杂浓度。随后通过热退火，如图7所示，使深掩埋区100和101中的掺杂物，扩散到衬底和第一外延层16中，构成区域107、108和109，如图8所示。确切地说，如上所述，锑和磷之间的扩散系数的不同，即磷扩散得比锑快，使区域109包围着区域108。
如图3和图9所示，在步骤206之后，在层16上方生长外延层18，在步骤206处。外延层18含有n-型掺杂物。
在步骤208处，参见图10，在子区114、118、214和218中，以及外延层18中，植入p-型掺杂物，随后在子区116和216中植入n-型掺杂物。在子区114、116、118、214和216和218中植入掺杂物之后，利用热循环驱使掺杂物充分进入层18，达到所需的掺杂浓度和结构。通过在区92中扩散掺杂物，形成掩埋区34。通过在区108和109中扩散掺杂物，分别形成深掩埋区134和136。在区域109中的轻掺杂磷向上延伸，将p-型外延层16转换成轻掺杂的n-型，其掺杂浓度接近于外延层18。通过在区域90中扩散掺杂物形成绝缘区40。通过将扩散的掺杂物合并到区域107、104和214中，形成绝缘区140。因此，形成掩埋区34、深掩埋区134，包含重掺杂的掩埋区136以及轻掺杂的掩埋区134；绝缘区40和140；以及有源区20和120。
如图2所示，在p-型外延层16中转换的n-型区134的作用是，如果n-型外延层向下延伸的话，那么区域136和区域126之间的有效垂直距离51大于区域35和区域26之间的垂直距离47。因此，器件120的垂直击穿电压、工作电压都高于器件20。
如图3和图10所示，在步骤208处，通过在N-阱区116和P-阱区118中植入掺杂物，形成器件10的有源区，配置器件10的具体器件结构，通过在N-阱区216和P-阱区218中植入掺杂物，形成器件11的有源区，配置器件11的具体器件结构。应明确，尽管为了便于说明，用单独的步骤表示，但是依据传统的植入和掩膜工艺，在步骤208处植入n-型和p-型掺杂物可以在多个步骤中进行。如上所述，制备器件300的成熟的工艺和状态可以整体转移到从步骤204开始。要明确的是，现有器件具有较低的额定电压，本发明所述的新增器件具有较高的额定电压，现有器件和本发明所述的新增器件将在同一衬底材料上共同存在，而不会相互影响。
如图10所示，工艺步骤208提出了一种高压器件与低压器件集成的半导体芯片。要明确的是，器件10或器件11可以是二极管、双极晶体管、MOSFET或其他器件。还要明确的是，利用本发明所述的工艺，任意器件组合都可以集成在一起，而不会相互影响。如图11所示，表示器件11的一个实施例，高压垂直NPN晶体管（VNPN）400与现有低压器件（图中没有表示出）集成。除了器件400的有源区包含一个沉积在高压P-阱126中的重掺杂N+区130之外，其他都与器件11相同。重掺杂N+区130、P-阱126以及N区包含在P-阱126下面的一部分N-外延层18以及深掩埋N区134，配置带有N+区130的垂直NPN作为发射极，P-阱126作为基极，HVPW126下方的N区作为集电极。沉积在HVPW126中的P+区128提供到基极的接触拾取，而沉积在HVPW126之外的N-外延层18顶部的N区122，提供到集电极的接触拾取。根据N区122的垂直浓度，可以沉积重掺杂N+区，以增强到金属电极（图中没有表示出）的欧姆接触。基极和集电极接触拾取可以在布局中形成环形的形状。基极区126的底部和深掩埋重掺杂区136的顶部之间的距离51，控制了NPN晶体管的垂直击穿，从而限制了NPN晶体管400的工作电压。
如图12所示，表示器件11的一个可选实施例，高压横向PNP晶体管（LPNP）410与现有低压器件（图中没有表示出）集成。除了器件410的有源区作为横向PNP，包含一个P区127作为发射极，P环125作为集电极，包围着中心P发射区127，N环123作为基极接触拾取，包围着集电极P环125和发射极P区127。基极区包含一部分N-外延层18和深掩埋N区134，还包含包围在汽车站掩埋区134之内的深掩埋重掺杂区136。P集电极区125的底部和深掩埋重掺杂区136的顶部之间的距离51控制PNP晶体管的垂直击穿，从而限制了PNP晶体管410的工作电压。
如图13所示，表示表示器件11的一个可选实施例，高压PN结二极管420与现有低压器件（图中没有表示出）集成。除了器件420的有源区配置成PN二极管之外，其他都与器件11相同，PN二极管含有一个P区162作为阳极，N区160作为阴极的接触拾取，含有一部分N-外延层18和深掩埋区134。阳极P区162的底部和深掩埋重掺杂区136的顶部之间的距离51，控制二极管的垂直击穿，从而限制了二极管420的工作电压。
如图14所示，表示器件11的一个可选实施例，高压N-通道横向DMOS（LDMOS）与现有的低压器件（图中没有表示出）集成。除了器件430的有源区配置成N-通道LDMOS之外，其他都与器件11相同，N-通道LDMOS包含一个沉积在P-阱156中的N+源极区157，以及一个沉积在N-阱154中的N+漏极接触拾取区。P-阱156作为本体，N区包含N-阱154，一部分N-外延层18和深掩埋区134作为漏极。场氧化物152形成在N-阱154的顶部，紧靠着漏极接触拾取区155，绝缘栅极150沉积在P-阱156上，N-阱154从源极区157重叠的一部分开始，延伸到场氧化物152重叠的一部分。P本体区162的底部和深掩埋重掺杂区136的顶部之间的距离51控制N-通道LDMOS的垂直击穿，从而控制LDMOS430的工作电压。
可以用与图15中相同的方法制备P-通道LDMOS440，不同之处在于，P+源极区175现在沉积在N-阱174中，作为本体，并且P+漏极接触拾取177现在沉积在P-阱176中，作为漏极。P漏极区176的底部和深掩埋重掺杂区136的顶部之间的距离51控制P-通道LDMOS的垂直击穿，从而控制LDMOS440的工作电压。
如图16所示，表示器件11的一个可选实施例，高压N-通道横向DMOS（LDMOS）与现有的低压器件（图中没有表示出）集成。除了RESURF区137在深轻掺杂N掩埋区134的顶部作为深P-阱（DPW）之外，器件450的其他部分都与器件11相同。DPW区137在反向偏置下耗尽，从而作为三重RESURF，改善了上述器件430的性能。通过植入图8中的区域104和106的同时或之后，在高压器件区中P-外延层16的顶部植入P型掺杂物，可以在步骤204附近的工艺中形成DPW区137。最好选用浮动DPW区137局限于p-外延层16和n-外延层18之间的交界面附近。P本体区156的底部和深掩埋重掺杂区136的顶部之间的距离51控制N-通道LDMOS的垂直击穿，从而控制LDMOS450的工作电压。
本发明还提出了通过在现有器件初始制备工艺中增加一些步骤，一种工作电压高于同功能的现有器件的制备方法，不会大幅影响器件的性能。确切地说，植入第二导电类型的第一和第二离子以及第一导电类型的离子之后，为了形成图5-6所示的绝缘区，要在衬底材料14上沉积第一导电类型的第一外延层16。在图8所示的区域104中植入第一导电类型的离子之后，在衬底材料14上方沉积外延层18。省略图3所示的步骤204中的大多数程序，仅在高压器件区中进行制备过程，就可以制备工作电压高于图1原有技术器件的器件。在这种情况下，第一外延层16的掺杂浓度与衬底材料14不同。依据其余的标准工艺，图11-16所示的器件具有较高的工作电压。
应明确的是，上述说明仅是本发明的一个示例，可能存在本发明的真实意图和范围内的修正，上述说明不应作为本发明范围的局限。因此，本发明的范围应由所附的权利要求书及其等效内容的全部范围决定。
尽管本发明的内容已经通过上述优选实施例作了详细介绍，但应当认识到上述的描述不应被认为是对本发明的限制。在本领域技术人员阅读了上述内容后，对于本发明的多种修改和替代都将是显而易见的。因此，本发明的保护范围应由所附的权利要求来限定。

Claims (18)

1.一种由高压器件和低压器件构成的半导体芯片，其特征在于，该半导体芯片包含：
一个第一导电类型的衬底层；
一个第一导电类型的第一外延层，其在衬底层的顶面上；
一个与第一导电类型相反的第二导电类型的第二外延层，该第二外延层在第一外延层的顶面上；
一个第二导电类型的深掩埋植入区，该深掩埋植入区在高压器件的区域中；
一个第二导电类型的掩埋植入区，该掩埋植入区在低压器件的区域中；以及，
一个第一导电类型的第一掺杂阱，其从第二外延层的顶面开始延伸到深掩埋植入区上方；以及一个第一导电类型的第二掺杂阱，其从第二外延层的顶面开始延伸到掩埋植入区上方；
所述第一外延层的掺杂浓度与衬底相同；
所述第二导电类型的深掩埋植入区还包含一个第二导电类型的深掩埋重掺杂区以及第二导电类型的深掩埋轻掺杂区，该深掩埋轻掺杂区包围着深掩埋重掺杂区。
2.如权利要求1所述的半导体芯片，其特征在于，所述深掩埋轻掺杂区从衬底的深度开始延伸到第一外延层的顶面，其掺杂浓度与第二外延层相同。
3.如权利要求2所述的半导体芯片，其特征在于，该半导体芯片还包含包围着高压器件和低压器件的有源区的绝缘区。
4.一种由第一器件构成的半导体芯片，其特征在于，所述的半导体芯片还包含：
一个第一导电类型的衬底层；
一个第一导电类型的第一外延层，该第一外延层在衬底层上方；
一个与第一导电类型相反的第二导电类型的第二外延层，该第二外延层在第一外延层上方；
一个第二导电类型的深掩埋植入区，该深掩埋植入区在第一器件的区域中；
一个第一导电类型的第一掺杂阱，其从第二外延层的顶面开始，向下延伸到深掩埋植入区上方；
所述第二导电类型的深掩埋植入区还包含一个第二导电类型的深掩埋重掺杂区，以及一个第二导电类型的深掩埋轻掺杂区，该深掩埋轻掺杂区包围着所述的深掩埋重掺杂区，并从衬底的深度开始延伸到第一外延层的顶面。
5.如权利要求4所述的半导体芯片，其特征在于，所述第二导电类型的深掩埋轻掺杂区的掺杂浓度与第二外延层相同。
6.如权利要求4所述的半导体芯片，其特征在于，所述第一导电类型的第一掺杂阱底部和第二导电类型的深掩埋重掺杂区之间的距离，控制第一器件的工作电压。
7.如权利要求4所述的半导体芯片，其特征在于，所述第一器件是由NPN双极晶体管构成，第一掺杂阱配置成NPN双极晶体管的基极。
8.如权利要求4所述的半导体芯片，其特征在于，所述第一器件是由PNP双极晶体管构成，第一掺杂阱配置成PNP双极晶体管的集电极。
9.如权利要求4所述的半导体芯片，其特征在于，所述第一器件是由PN二极管构成，第一掺杂阱配置成PN二极管的阳极。
10.如权利要求4所述的半导体芯片，其特征在于，所述第一器件是由N通道DMOS晶体管构成，第一掺杂阱配置成DMOS晶体管的基极。
11.如权利要求10所述的半导体芯片，其特征在于，所述N通道DMOS晶体管还包含一个第一导电类型的掩埋掺杂区，其沉积在第二导电类型的深掩埋重掺杂区上方，配置成RESURF层。
12.如权利要求4所述的半导体芯片，其特征在于，所述第一器件是由P通道DMOS晶体管构成，第一掺杂阱配置成DMOS晶体管的漏极。
13.如权利要求4所述的半导体芯片，其特征在于，该半导体芯片还包含包围着第一器件有源区的绝缘区。
14.如权利要求4所述的半导体芯片，其特征在于，所述第一外延层的掺杂浓度与衬底相同。
15.如权利要求14所述的半导体芯片，其特征在于，该半导体芯片还包含沉积在第二器件区上的第二器件，所述的第二器件区还包含：
一个第二导电类型的掩埋植入区，其在第一外延层和第二外延层之间的交界面处，并分别延伸入第一外延层和第二外延层内；以及，
第一导电类型的第二掺杂阱，其从第二外延层的顶面开始，向下延伸到掩埋植入区上方。
16.如权利要求15所述的半导体芯片，其特征在于，所述第一器件的工作电压高于第二器件。
17.一种半导体芯片，其是由沉积在上方的高压器件和低压器件构成，其特征在于，所述的半导体芯片还包含：
一个第一导电类型的衬底层；
一个第一导电类型的第一外延层，该第一外延层在衬底层的顶面上，第一外延层的掺杂浓度与衬底相同；
一个与第一导电类型相反的第二导电类型的第二外延层，该第二外延层在第一外延层的顶面上；
一个第二导电类型的深掩埋植入区，该深掩埋植入区在高压器件的区域中，所述的深掩埋植入区包含一个第二导电类型的深掩埋重掺杂区，以及第二导电类型的深掩埋轻掺杂区，该深掩埋轻掺杂区包围着所述的深掩埋重掺杂区；
一个第二导电类型的掩埋植入区，该掩埋植入区在低压器件的区域中；
一个第一导电类型的第一掺杂阱，其从第二外延层的顶面开始，延伸到深掩埋植入区上方；以及一个第一导电类型的第二掺杂阱，其从第二外延层的顶面开始，延伸到掩埋植入区上方；以及
绝缘区，其包围着高压器件和所述的低压器件的有源区。
18.如权利要求17所述的半导体芯片，其特征在于，所述深掩埋轻掺杂区从衬底的深度开始，延伸到第一外延层的顶面，其掺杂浓度与第二外延层相同。
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