TWI473248B - 結合高低壓元件之半導體芯片 - Google Patents

結合高低壓元件之半導體芯片 Download PDF

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TWI473248B
TWI473248B TW101134244A TW101134244A TWI473248B TW I473248 B TWI473248 B TW I473248B TW 101134244 A TW101134244 A TW 101134244A TW 101134244 A TW101134244 A TW 101134244A TW I473248 B TWI473248 B TW I473248B
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region
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epitaxial layer
semiconductor chip
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TW201314867A (zh
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Tsuchiko Hideaki
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Alpha & Omega Semiconductor
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Description

結合高低壓元件之半導體芯片
本發明是有關於一種高壓半導體元件及其製備製程，特別是有關於一種在現有的半導體元件製程流程中增加高壓元件的模組化技術。
為了滿足新型應用的需要，具有較高額定電壓的元件通常必須與現有元件結合在一塊現有元件中。將電壓較高的元件結合在現有的低壓元件中，通常需要對已驗證過的現有的低壓元件製備製程流程或狀態做許多改動，致使現有低壓元件的性能降低，從而必須升級元件模組。為了避免新型技術改進帶來的冗長設計週期以及高成本，我們研究的重點就是僅需對現有的低壓元件製程做些微調，從而使對現有低壓元件性能的影響降至最低。
一般來說，在雙極CMOS DMOS(Bipolar CMOS DMOS,BCD)或雙極CMOS(Bipolar CMOS,BiCMOS)製程中，最高的工作電壓受到P至N接面的垂直結構的穿通擊穿的侷限。這種垂直接面擊穿是外延層厚度、摻雜濃度和接面深度的函數。如第1圖所示，表示一個形成在半導體芯片中的現有元件300的示例，現有元件300 含有一個厚度43的n-型外延層18沉積在P基板14上。元件300的大致結構是，多個N-井22和P-井26和48位於N-外延層中。掩埋的P區46從N-外延層底部開始，向下延伸到P-井48的底部邊緣中，並且合併在一起。掩埋的P區也向下延伸到基板材料14中，從而使元件300與製備其他元件的半導體芯片的其他區域絕緣。元件300更包含一個在P-井26下方的N掩埋區35，避免在P-井和P基板之間穿通，P基板限制了元件300最大的工作電壓。利用一定厚度的外延層18，並且控制P-井26的深度45，使元件300的性能達到最優，P-井26的底部和掩埋的N區35的頂部之間的垂直距離47限制了垂直擊穿電壓，從而當橫向擊穿控制因子49(即掩埋P區46和N掩埋區35之間的橫向距離)足夠大，使橫向擊穿電壓遠大於垂直擊穿電壓時，限制元件300的工作電壓。製備製程從基板材料14開始，然後分別在區域35和46中植入離子。在基板材料14上方沉積外延層18，並且製備多個從外延層頂面開始向下延伸的N-井和P-井。藉由額外的步驟，製備雙極電晶體或半導體場效電晶體(MOSFET)等具體功能的元件。當一個工作電壓較高的元件需要結合在同一基板上的不同區域中的情況下，一種提高P至N垂直擊穿電壓的方法就是增加外延層18的厚度。如果製備元件300的製程和狀態仍然保持不變的話，這將會影響現有元件300的性能和獨立性。
另一種方法就是引入一個較輕的摻雜層，以降低摻雜濃度和淺P井接面。例如，Hideaki Tsuchiko在美國專利7019377中提出了一種結合電路，包含一個高壓肖特基勢壘二極體以及一個低壓元件。肖特基勢壘二極體含有一個輕摻雜的淺P-井，作為保護環， 同時利用標準的、較重摻雜的、較深的p-井，製備低壓元件。藉由含有輕摻雜p-井、標準p-井以及增厚的N-外延層的製程，提高高壓元件的擊穿電壓以及最大工作電壓。每種方法都能使擊穿電壓升高15V至30V。使用這兩種方法的肖特基勢壘二極體，可以使擊穿電壓升高30V至60V，而不會嚴重影響其他元件和結構的性能。
這兩種方法和元件佈局的同時使用，可以在同一芯片上結合高壓和低壓元件。然而，這些方法經常會對現有元件的性能有輕微影響。某些元件需要對SPICE模組稍作調整。尤其是對增大N-外延層的厚度有一定的限制。如果大幅增加N-外延層厚度的話，P-型掩埋區46的向上擴散和p井48的向下擴散之間的絕緣連接就會被削弱或中斷，致使不完整的元件絕緣。因此，要在低壓芯片內結合高壓元件，必須提出新的技術，使得僅需在現有的低壓製程流程中增加一些步驟，就能在低壓芯片內結合高壓元件，而不會對低壓元件的性能造成影響。
本發明提供一種結合高低壓元件的半導體芯片，能在低壓芯片內結合高壓元件，而不會對低壓元件的性能造成影響。
為實現上述目的，本發明提供一種由高壓元件和低壓元件構成的半導體芯片。該半導體芯片包含：第一導電類型的基板層；在基板層頂面上的第一導電類型的第一外延層；在第一外延層頂面上的與第一導電類型相反的第二導電類型的第二外延層；在高壓 元件區域中的第二導電類型的深掩埋植入區；在低壓元件區域中的第二導電類型的掩埋植入區；從第二外延層頂面開始延伸到深掩埋植入區上方的第一導電類型的第一摻雜井；以及從掩埋植入區上方的第二外延層頂面開始的第一導電類型的第二摻雜井。
一種由第一元件構成的半導體芯片，該半導體芯片更包含：第一導電類型的半導體基板層；第一導電類型的第一外延層，第一外延層在基板層上方；與第一導電類型相反的第二導電類型的第二外延層，第二外延層在第一外延層上方；第二導電類型的深掩埋植入區，深掩埋植入區在第一元件的區域中；第一導電類型的第一摻雜井，其從第二外延層的頂面開始，向下延伸到深掩埋植入區上方；其中，上述第二導電類型的深掩埋植入區更包含第二導電類型的深掩埋重摻雜區，以及第二導電類型的深掩埋輕摻雜區，深掩埋輕摻雜區包圍著所述的深掩埋重摻雜區，並從基板層的深度開始延伸到第一外延層的頂面。
一種半導體芯片，其是由沉積在上方的高壓元件和低壓元件構成，該半導體芯片更包含：第一導電類型的基板層；第一導電類型的第一外延層，第一外延層在基板層的頂面上， 第一外延層的摻雜濃度與基板大致相同；與第一導電類型相反的第二導電類型的第二外延層，第二外延層在第一外延層的頂面上；第二導電類型的深掩埋植入區，深掩埋植入區在高壓元件的區域中，深掩埋植入區包含第二導電類型的深掩埋重摻雜區，以及第二導電類型的深掩埋輕摻雜區，深掩埋輕摻雜區包圍著所述的深掩埋重摻雜區；第二導電類型的掩埋植入區，掩埋植入區在低壓元件的區域中；第一導電類型的第一摻雜井，其從第二外延層的頂面開始，延伸到深掩埋植入區上方；以及第一導電類型的第二摻雜井，其從第二外延層的頂面開始，延伸到掩埋植入區上方；以及絕緣區，其包圍著高壓元件和所述的低壓元件的主動區。
本發明所製備的芯片具有多種不同的配置。例如，半導體芯片可以包含NPN雙極電晶體、PNP雙極電晶體、二極體、N通道DMOS電晶體以及類似元件。本發明的這些及其他實施例將在下文中詳細介紹。
10‧‧‧第一元件
100、101‧‧‧深掩埋區
104、106‧‧‧掩埋區
107、108、109‧‧‧區域
11‧‧‧第二元件
114、116、118、214、216、218‧‧‧子區
12‧‧‧層堆疊
120‧‧‧主動區
122‧‧‧N-井
123‧‧‧N環
125‧‧‧P環
126、148‧‧‧P-井
127‧‧‧P區
128‧‧‧P+區
130‧‧‧N+區
134‧‧‧第二部分
136‧‧‧第一部分
137‧‧‧RESURF區
138‧‧‧區域
14‧‧‧P基板
140‧‧‧絕緣區
144、146‧‧‧重疊區
150‧‧‧絕緣閘極
152‧‧‧場氧化物
154‧‧‧N-井
155‧‧‧汲極接觸拾取區
156‧‧‧P-井
157‧‧‧N+源極區
16‧‧‧第一外延層
160‧‧‧N區
162‧‧‧P區
174‧‧‧N-井
175‧‧‧P+源極區
176‧‧‧P-井
177‧‧‧P+汲極接觸拾取
18‧‧‧外延層
20‧‧‧主動區
22‧‧‧N-井
26、48‧‧‧P-井
300‧‧‧元件
34‧‧‧掩埋區
35‧‧‧N掩埋區
40‧‧‧絕緣區
400‧‧‧元件
410‧‧‧元件
420‧‧‧元件
43‧‧‧厚度
430‧‧‧元件
440‧‧‧LDMOS
45‧‧‧深度
450‧‧‧元件
46‧‧‧P區
47‧‧‧距離
49‧‧‧控制因子
50‧‧‧表面
51‧‧‧距離
52‧‧‧水平距離
200、202、204、206、208‧‧‧步驟
90、92‧‧‧掩埋區
第1圖 係為依據本發明的一個方面，一種製備在基板上的現有元件之剖面圖；第2圖 係為依據本發明的一個方面，一種工作電壓較高的元件與 第1圖所示的工作電壓較低的元件一起製備在一個共同基板上之剖面圖；第3圖 係為一種第2圖所示結構的製備方法之流程圖；第4至10圖 係為第2圖所示的主動元件在第3圖所示的製備製程的不同步驟中之剖面圖；第11圖 係為依據本發明之一種工作電壓較高的垂直NPN雙極電晶體之剖面圖；第12圖 係為依據本發明之一種工作電壓較高的橫向PNP雙極電晶體之剖面圖；第13圖 係為依據本發明之一種工作電壓較高的PN二極體之剖面圖；第14圖 係為依據本發明之一種工作電壓較高的橫向N-通道DMOS之剖面圖；第15圖 係為依據本發明之一種工作電壓較高的橫向P-通道DMOS之剖面圖；第16圖 係為依據本發明之一種工作電壓較高的帶有三重RESURF的橫向N-通道DMOS之剖面圖。
如第2圖所示，依據本發明，額定工作電壓不同的第一和第二元件10和11形成在具有半導體材料14的共同半導體芯片上，第一外延層16堆疊在基板材料14上方，第二外延層18堆疊在第一外延層16上方。外延層16的摻雜濃度與基板材料14大致相同。基板14和外延層16首選p-型。形成在外延層1上方的第二外延層18首選n- 型。外延層16和外延層18限定了一個層堆疊12。
元件10的主動區20形成在n-型外延層18中。元件10的大致結構是，多個N-井22和P-井26和48位於N-外延層中。井22中的n-型摻雜物濃度高於外延層18中的n-型摻雜物濃度。P-型井26中的摻雜物濃度高於外延層16和基板14中。N-型摻雜物的掩埋區，也稱為掩埋區35，在p-外延層16和n-外延層18之間延伸，可控制的垂直間距47小於P-井26的底部和掩埋的N區35之間的外延層18的厚度。掩埋的N區35侷限於p-外延層16和n-外延層18之間的交界面附近的區域中，使得掩埋區35中的n-型摻雜物濃度高於層18中。
絕緣區40沉積在主動區20和掩埋區35的對邊上。絕緣區40形成於多個區，這些區中所具有的p-型摻雜物濃度高於基板14或外延層16中。確切地說，每個絕緣區40都含有一個高壓P井(High Voltage P Well,HVPw)48，位於n-型外延層18的頂部，並且與p-型掩埋區46的掩埋區重疊，在n-型外延層18之間延伸到p-型外延層16。除了元件10具有一個額外的外延層16形成在基板上方之外，其他都與第1圖所示的元件300相同。由於外延層16的摻雜濃度與基板材料14相同，因此元件10的性能與元件300相同，外延層16可以被視為是基板材料14的延伸物。製備元件300的現有的製備製程和狀態都可以整體轉移給製備元件10的製程模組。
依據本發明，元件11也形成在基板14和層堆疊12中。元件11包含一個主動區120，形成在層18中。元件11的大體結構是，多個N-井122和P-井126和148都在N-外延層18中。井122中的n-型摻雜物濃度高於井122外部的層18中的區。井126的P-型摻雜物濃度高於層16和基板14中的P-型摻雜物濃度。一個n-型摻雜物的深掩埋 區，也稱為深掩埋區134，在基板14和層堆疊12之間延伸。深掩埋區134有兩種不同的種類，包含一個重摻雜的第一n-型部分(稱為深掩埋重摻雜區136)，以及一個輕摻雜的第二n-型部分(稱為深掩埋輕摻雜區134)，第二部分134包圍著第一部分136。最好是將第一n-型部分136限制在基板材料14和p-外延層16之間的交界面附近，使重摻雜第一n-型部分136中的n-型摻雜物濃度高於層16中。第二n-型部分向上延伸，觸及第二外延層18，最適宜的摻雜濃度與層18相同。
對於給定的溫度，部分134中的第二n-型摻雜物擴散速度大於部分136中的第一n-型摻雜物。在本實施例中，區域136中的摻雜物為銻或砷，區域138中的摻雜物為磷。
絕緣區140沉積在主動區120和深掩埋區134的對邊上。絕緣區140形成於多個區域，這些區中所具有的p-型摻雜物濃度高於基板14或層堆疊12的層16中。確切地說，每個絕緣區140都由三個p-型摻雜濃度的重疊區144、146和148構成。第一掩埋區144在基板14和第一外延層16之間延伸。第二掩埋區146與掩埋區144重疊，並且在第一外延層16和第二外延層18之間延伸。第三井148與第二掩埋區146重疊，並且從第二層18的表面50開始，向第一層16延伸。應瞭解，絕緣區140的作用是使主動區120與鄰近元件的主動區絕緣，鄰近元件的主動區表示為形成在基板14上和層堆疊12中的主動區20。
元件11要考慮三個擊穿電壓。其一，掩埋區134和136到主動區120外面的基板材料14。該擊穿電壓可以藉由134、136以及14的摻雜濃度和134和136的結構來控制。其二，主動區120中的橫向 擊穿電壓可以藉由區域134和136以及絕緣區140之間的水平距離52、以及區域134、136、14、16和140的摻雜濃度和結構來控制。其三，主動區120中的垂直擊穿電壓可以藉由區域136和126之間的垂直距離51、以及區域134、136、18和126的摻雜濃度和結構來控制。將絕緣區140與主動元件區120分開，可以輕鬆地使第二橫向擊穿電壓遠高於垂直擊穿電壓。因此，元件120最大的工作電壓受到第三垂直擊穿的限制。
為了在半導體芯片上製備元件10和11，在步驟200處，要製備一種p-型基板14，深掩埋區100和101形成在基板14頂面上的高壓元件區中，如第3至6圖所示。利用人們熟知的植入和遮罩製程，植入摻雜物，獲得所需的摻雜濃度。確切地說，深掩埋區101包含兩種不同類型的n-型摻雜物，在特定的溫度下，具有不同速度的擴散係數。在本實施例中，第一n-型摻雜物為銻或砷，第二摻雜物為磷，兩者藉由兩步植入，均植入到基板14上的同一個深掩埋區101中。深掩埋區100含有一定濃度的p-型摻雜物。低壓元件區被光致抗蝕劑覆蓋，避免在該步驟中植入離子。
如第3圖和第7圖所示，在步驟202處，外延層16生長在整個區域的基板14上方。外延層16最好是與基板14具有相同的p-型摻雜物以及相同的摻雜濃度。在步驟204處，掩埋區104，如第8圖所示，形成在外延層16上，以及工作電壓較高的區域中的深掩埋區100上方。在步驟204中，掩埋區90和92形成在外延層16中，有利於製備工作電壓較低的元件10。掩埋區90和104包含p-型摻雜物，掩埋區92包含n-型摻雜物。區域90和104中的摻雜濃度高於層16的剩餘區域中的摻雜濃度。隨後藉由熱退火，如第7圖所示， 使深掩埋區100和101中的摻雜物，擴散到基板和第一外延層16中，構成區域107、108和109，如第8圖所示。確切地說，如上所述，銻和磷之間的擴散係數的不同，即磷擴散得比銻快，使區域109包圍著區域108。
如第3圖和第9圖所示，在步驟206之後，在層16上方生長外延層18，在步驟206處。外延層18含有n-型摻雜物。
在步驟208處，請參閱第10圖，在子區114、118、214和218中，以及外延層18中，植入p-型摻雜物，隨後在子區116和216中植入n-型摻雜物。在子區114、116、118、214和216和218中植入摻雜物之後，利用熱循環驅使摻雜物充分進入層18，達到所需的摻雜濃度和結構。藉由在區92中擴散摻雜物，形成掩埋區34。藉由在區108和109中擴散摻雜物，分別形成深掩埋區134和136。在區域109中的輕摻雜磷向上延伸，將p-型外延層16轉換成輕摻雜的n-型，其摻雜濃度接近於外延層18。藉由在區域90中擴散摻雜物形成絕緣區40。藉由將擴散的摻雜物合併到區域107、104和214中，形成絕緣區140。因此，形成掩埋區34、深掩埋區134，包含重摻雜的掩埋區136以及輕摻雜的掩埋區134；絕緣區40和140；以及主動區20和120。
如第2圖所示，在p-型外延層16中轉換的n-型區134的作用是，如果n-型外延層向下延伸的話，那麼區域136和區域126之間的有效垂直距離51大於區域35和區域26之間的垂直距離47。因此，元件120的垂直擊穿電壓、工作電壓都高於元件20。
如第3圖和第10圖所示，在步驟208處，藉由在N-井區116和P-井 區118中植入摻雜物，形成元件10的主動區，配置元件10的具體元件結構，藉由在N-井區216和P-井區218中植入摻雜物，形成元件11的主動區，配置元件11的具體元件結構。應瞭解，儘管為了便於說明，用單獨的步驟表示，但是依據傳統的植入和遮罩製程，在步驟208處植入n-型和p-型摻雜物可以在多個步驟中進行。如上所述，製備元件300的成熟的製程和狀態可以整體轉移到從步驟204開始。要瞭解的是，現有元件具有較低的額定電壓，本發明所述的新增元件具有較高的額定電壓，現有元件和本發明所述的新增元件將在同一基板材料上共同存在，而不會相互影響。
如第10圖所示，製程步驟208提出了一種高壓元件與低壓元件結合的半導體芯片。要瞭解的是，元件10或元件11可以是二極體、雙極電晶體、MOSFET或其他元件。更要瞭解的是，利用本發明所述的製程，任意元件組合都可以結合在一起，而不會相互影響。如第11圖所示，表示元件11的一個實施例，高壓垂直NPN電晶體(Vertical NPN,VNPN)400與現有低壓元件(圖中沒有表示出)結合。除了元件400的主動區包含一個沉積在高壓P-井126中的重摻雜N+區130之外，其他都與元件11相同。重摻雜N+區130、P-井126以及N區包含在P-井126下面的一部分N-外延層18以及深掩埋N區134，配置帶有N+區130的垂直NPN作為發射極，P-井126作為基極，HVPW 126下方的N區作為集電極。沉積在HVPW 126中的P+區128提供到基極的接觸拾取，而沉積在HVPW 126之外的N-外延層18頂部的N區122，提供到集電極的接觸拾取。根據N區122的垂直濃度，可以沉積重摻雜N+區，以增強到金屬電極(圖中沒有表示出)的歐姆接觸。基極和集電極接觸拾取可以在佈局中形成 環形的形狀。基極區126的底部和深掩埋重摻雜區136的頂部之間的距離51，控制了NPN電晶體的垂直擊穿，從而限制了NPN電晶體400的工作電壓。
如第12圖所示，表示元件11的一個較佳實施例，高壓橫向PNP電晶體(Lateral PNP,LPNP)410與現有低壓元件(圖中並未表示出)結合。除了元件410的主動區作為橫向PNP，包含一個P區127作為發射極，P環125作為集電極，包圍著中心P發射區127，N環123作為基極接觸拾取，包圍著集電極P環125和發射極P區127。基極區包含一部分N-外延層18和深掩埋N區134，更包含包圍在輕摻雜深掩埋區134之內的深掩埋重摻雜區136。P集電極區125的底部和深掩埋重摻雜區136的頂部之間的距離51控制PNP電晶體的垂直擊穿，從而限制了PNP電晶體410的工作電壓。
如第13圖所示，表示表示元件11的一個較佳實施例，高壓PN接面二極體420與現有低壓元件(圖中並未表示出)結合。除了元件420的主動區配置成PN二極體之外，其他都與元件11相同，PN二極體含有一個P區162作為陽極，N區160作為陰極的接觸拾取，含有一部分N-外延層18和深掩埋區134。陽極P區162的底部和深掩埋重摻雜區136的頂部之間的距離51，控制二極體的垂直擊穿，從而限制了二極體420的工作電壓。
如第14圖所示，表示元件11的一個較佳實施例，高壓N-通道橫向DMOS(Laterally Diffused MOS,LDMOS)與現有的低壓元件(圖中並未表示出)結合。除了元件430的主動區配置成N-通道LDMOS之外，其他都與元件11相同，N-通道LDMOS包含一個沉積在P-井156中的N+源極區157，以及一個沉積在N-井154中的N+汲極 接觸拾取區。P-井156作為本體，N區包含N-井154，一部分N-外延層18和深掩埋區134作為汲極。場氧化物152形成在N-井154的頂部，緊靠著汲極接觸拾取區155，絕緣閘極150沉積在P-井156上，N-井154從源極區157重疊的一部分開始，延伸到場氧化物152重疊的一部分。P本體區162的底部和深掩埋重摻雜區136的頂部之間的距離51控制N-通道LDMOS的垂直擊穿，從而控制LDMOS 430的工作電壓。
可以用與第15圖中相同的方法製備P-通道LDMOS 440，不同之處在於，P+源極區175現在沉積在N-井174中，作為本體，並且P+汲極接觸拾取177現在沉積在P-井176中，作為汲極。P汲極區176的底部和深掩埋重摻雜區136的頂部之間的距離51控制P-通道LDMOS的垂直擊穿，從而控制LDMOS 440的工作電壓。
如第16圖所示，表示元件11的一個較佳實施例，高壓N-通道橫向DMOS(LDMOS)與現有的低壓元件(圖中沒有表示出)結合。除了降低表面電場型(reduced surface field,RESURF)區137在深輕摻雜N掩埋區134的頂部作為深P-井(Deep P-Well,DPW)之外，元件450的其他部分都與元件11相同。DPW區137在反向偏置下耗盡，從而作為三重RESURF，改善了上述元件430的性能。藉由植入第8圖中的區域104和106的同時或之後，在高壓元件區中P-外延層16的頂部植入P型摻雜物，可以在步驟204附近的製程中形成DPW區137。最好選用浮動DPW區137侷限於p-外延層16和n-外延層18之間的交界面附近。P本體區156的底部和深掩埋重摻雜區136的頂部之間的距離51控制N-通道LDMOS的垂直擊穿，從而控制LDMOS 450的工作電壓。
本發明更提出了藉由在現有元件初始製備製程中增加一些步驟，一種工作電壓高於同功能的現有元件的製備方法，不會大幅影響元件的性能。確切地說，植入第二導電類型的第一離子和第二離子以及第一導電類型的離子之後，為了形成第5至6圖所示的絕緣區，要在基板材料14上沉積第一導電類型的第一外延層16。在第8圖所示的區域104中植入第一導電類型的離子之後，在基板材料14上方沉積外延層18。省略第3圖所示的步驟204中的大多數程序，僅在高壓元件區中進行製備過程，就可以製備工作電壓高於第1圖原有技術元件的元件。在這種情況下，第一外延層16的摻雜濃度與基板材料14不同。依據其餘的標準製程，第11至16圖所示的元件具有較高的工作電壓。
應瞭解的是，上述說明僅是本發明的一個示例，可能存在本發明的真實意圖和範圍內的修正，上述說明不應作為本發明申請專利範圍的侷限。因此，本發明的申請專利範圍應由所附的申請專利範圍及其等效內容的全部範圍決定。
儘體本發明的內容已經藉由上述較佳實施例作了詳細介紹，但應當認識到上述的描述不應被認為是對本發明的限制。在本領域技術人員閱讀了上述內容後，對於本發明的多種修改和替代都將是顯而易見的。因此，本發明的保護範圍應由所附的申請專利範圍來限定。
10‧‧‧第一元件
11‧‧‧第二元件
12‧‧‧層堆疊
120‧‧‧主動區
122‧‧‧N-井
126、148‧‧‧P-井
134‧‧‧第二部分
136‧‧‧第一部分
14‧‧‧P基板
140‧‧‧絕緣區
144、146‧‧‧重疊區
16‧‧‧第一外延層
18‧‧‧外延層
20‧‧‧主動區
22‧‧‧N-井
26、48‧‧‧P-井
35‧‧‧N掩埋區
40‧‧‧絕緣區
46‧‧‧P區
47‧‧‧距離
49‧‧‧控制因子
50‧‧‧表面
51‧‧‧距離
52‧‧‧水平距離

Claims (18)

  1. 一種由高壓元件和低壓元件構成的半導體芯片，該半導體芯片包含：一第一導電類型的基板層；一第一導電類型的第一外延層，其在該基板層的頂面上；一與第一導電類型相反的第二導電類型的第二外延層，該第二外延層在該第一外延層的頂面上；一第二導電類型的深掩埋植入區，該深掩埋植入區在該高壓元件的區域中；一第二導電類型的掩埋植入區，該掩埋植入區在該低壓元件的區域中；一第一導電類型的第一摻雜井，其從該第二外延層的頂面開始延伸到該深掩埋植入區上方；以及一第一導電類型的第二摻雜井，其從第二外延層的頂面開始延伸到該掩埋植入區上方，其中該第一外延層的摻雜濃度與基板層大致相同，以及其中該第二導電類型的深掩埋植入區更包含一第二導電類型的深掩埋重摻雜區以及一第二導電類型的深掩埋輕摻雜區，該深掩埋輕摻雜區包圍著該深掩埋重摻雜區。
  2. 如申請專利範圍第1項所述之半導體芯片，其中該深掩埋輕摻雜區從基板層的深度開始延伸到第一外延層的頂面，其摻雜濃度與第二外延層大致相同。
  3. 如申請專利範圍第2項所述之半導體芯片，其中該半導體芯片更包含包圍著高壓元件和低壓元件的一主動區的絕緣區。
  4. 一種由第一元件構成之半導體芯片，該半導體芯片更包含：一第一導電類型的基板層；一第一導電類型的第一外延層，該第一外延層在基板層上方；一與第一導電類型相反的第二導電類型的第二外延層，該第二外延層在第一外延層上方；一第二導電類型的深掩埋植入區，該深掩埋植入區在第一元件的區域中；一第一導電類型的第一摻雜井，其從第二外延層的頂面開始，向下延伸到深掩埋植入區上方；該第二導電類型的深掩埋植入區更包含一第二導電類型的深掩埋重摻雜區，以及一第二導電類型的深掩埋輕摻雜區，該深掩埋輕摻雜區包圍著該深掩埋重摻雜區，並從基板層的深度開始延伸到第一外延層的頂面。
  5. 如申請專利範圍第4項所述之半導體芯片，其中該第二導電類型的深掩埋輕摻雜區的摻雜濃度與第二外延層大致相同。
  6. 如申請專利範圍第4項所述之半導體芯片，其中該第一導電類型的第一摻雜井底部和第二導電類型的深掩埋重摻雜區之間的距離，控制第一元件的工作電壓。
  7. 如申請專利範圍第4項所述之半導體芯片，其中該第一元件是由NPN雙極電晶體構成，第一摻雜井配置成NPN雙極電晶體的基極。
  8. 如申請專利範圍第4項所述之半導體芯片，其中該第一元件是由PNP雙極電晶體構成，第一摻雜井配置成PNP雙極電晶體的集電極。
  9. 如申請專利範圍第4項所述之半導體芯片，其中該第一元件是由PN二極體構成，第一摻雜井配置成PN二極體的陽極。
  10. 如申請專利範圍第4項所述之半導體芯片，其中該第一元件是由N通道DMOS電晶體構成，第一摻雜井配置成DMOS電晶體的基極。
  11. 如申請專利範圍第10項所述之半導體芯片，其中該N通道DMOS電晶體更包含一第一導電類型的掩埋摻雜區，其沉積在第二導電類型的深掩埋重摻雜區上方，配置成RESURF層。
  12. 如申請專利範圍第4項所述之半導體芯片，其中該第一元件是由P通道DMOS電晶體構成，第一摻雜井配置成DMOS電晶體的汲極。
  13. 如申請專利範圍第4項所述之半導體芯片，其中該半導體芯片更包含包圍著第一元件主動區的絕緣區。
  14. 如申請專利範圍第4項所述之半導體芯片，其中該第一外延層的摻雜濃度與基板層大致相同。
  15. 如申請專利範圍第14項所述之半導體芯片，其中該半導體芯片更包含沉積在第二元件區上的第二元件，該的第二元件區更包含：一第二導電類型的掩埋植入區，其在第一外延層和第二外延層之間的交界面附近；以及一第一導電類型的第二摻雜井，其從第二外延層的頂面開始，向下延伸到掩埋植入區上方。
  16. 如申請專利範圍第15項所述之半導體芯片，其中該第一元件的工作電壓高於第二元件。
  17. 一種半導體芯片，其是由沉積在上方的高壓元件和低壓元件構成，該半導體芯片更包含：一第一導電類型的基板層；一第一導電類型的第一外延層，該第一外延層在基板層的頂面上 ，第一外延層的摻雜濃度與基板層大致相同；一與第一導電類型相反的第二導電類型的第二外延層，該第二外延層在第一外延層的頂面上；一第二導電類型的深掩埋植入區，該深掩埋植入區在高壓元件的區域中，該深掩埋植入區包含一第二導電類型的深掩埋重摻雜區，以及一第二導電類型的深掩埋輕摻雜區，該深掩埋輕摻雜區包圍著該深掩埋重摻雜區；一第二導電類型的掩埋植入區，該掩埋植入區在低壓元件的區域中；一第一導電類型的第一摻雜井，其從第二外延層的頂面開始，延伸到深掩埋植入區上方；以及一第一導電類型的第二摻雜井，其從第二外延層的頂面開始，延伸到掩埋植入區上方；以及一絕緣區，其包圍著高壓元件和該低壓元件的主動區。
  18. 如申請專利範圍第17項所述之半導體芯片，其中該深掩埋輕摻雜區從基板層的深度開始，延伸到第一外延層的頂面，其摻雜濃度與第二外延層大致相同。
TW101134244A 2011-09-20 2012-09-19 結合高低壓元件之半導體芯片 TWI473248B (zh)

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