CN103026472A - 环状薄膜的沉积方法 - Google Patents

环状薄膜的沉积方法 Download PDF

Info

Publication number
CN103026472A
CN103026472A CN201180036357XA CN201180036357A CN103026472A CN 103026472 A CN103026472 A CN 103026472A CN 201180036357X A CN201180036357X A CN 201180036357XA CN 201180036357 A CN201180036357 A CN 201180036357A CN 103026472 A CN103026472 A CN 103026472A
Authority
CN
China
Prior art keywords
silicon
thin film
film
substrate
containing insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201180036357XA
Other languages
English (en)
Other versions
CN103026472B (zh
Inventor
金海元
禹相浩
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Eugene Technology Co Ltd
Original Assignee
Eugene Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Eugene Technology Co Ltd filed Critical Eugene Technology Co Ltd
Publication of CN103026472A publication Critical patent/CN103026472A/zh
Application granted granted Critical
Publication of CN103026472B publication Critical patent/CN103026472B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/34—Nitrides
    • C23C16/345—Silicon nitride
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/40—Oxides
    • C23C16/401—Oxides containing silicon
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
    • C23C16/45523—Pulsed gas flow or change of composition over time
    • C23C16/45525—Atomic layer deposition [ALD]
    • C23C16/45527—Atomic layer deposition [ALD] characterized by the ALD cycle, e.g. different flows or temperatures during half-reactions, unusual pulsing sequence, use of precursor mixtures or auxiliary reactants or activations
    • C23C16/45536—Use of plasma, radiation or electromagnetic fields
    • C23C16/4554—Plasma being used non-continuously in between ALD reactions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02219—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and nitrogen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Organic Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Plasma & Fusion (AREA)
  • Inorganic Chemistry (AREA)
  • Electromagnetism (AREA)
  • Chemical Vapour Deposition (AREA)
  • Formation Of Insulating Films (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明提供一种具有优异的膜性能和阶梯覆盖的环状薄膜的沉积方法。本发明一个实施例的环状薄膜的沉积方法包括：在所述基底上形成硅薄膜的步骤，其通过重复将硅前体注入到装载了基底的腔室内部而在所述基底上沉积硅的步骤、和从所述腔室内部除去未反应的硅前体和反应副产物的第一清洗步骤；通过在腔室内部形成等离子体气氛，将所述硅薄膜形成为含硅绝缘膜的步骤。

Description

环状薄膜的沉积方法
技术领域
本发明涉及一种环状薄膜的沉积方法，更具体地，涉及一种形成含硅绝缘膜的环状薄膜的沉积方法。
背景技术
近年来，随着半导体工业的发展和用户的需求，电子设备具有更加高集成化和高性能化，因此作为电子设备的核心组件的半导体器件也需要高集成化和高性能化。然而，很难实现高集成化的半导体器件的精细结构。
例如，为实现精细结构需要更薄的绝缘膜，但是如果形成的绝缘膜为薄的厚度，则膜性能如绝缘特性退化。此外，越来越难以形成具有薄的厚度的同时获得优异的阶梯覆盖(step coverage)的薄膜。
发明内容
发明要解决的课题
本发明的目的在于解决上述现有问题，并提供一种具有优异的膜性能和阶梯覆盖的绝缘膜的沉积方法。更具体地，本发明提供一种具有优异的膜性能和阶梯覆盖的环状薄膜的沉积方法。
通过下面的详细描述和附图，将更加清楚地理解本发明的其它目的。
解决课题的方法
根据本发明的一个实施例，提供了一种环状薄膜的沉积方法，该方法包括：在所述基底上形成硅薄膜的步骤，其通过重复将硅前体注入到装载了基底的腔室内部而在所述基底上沉积硅的步骤而进行、和从所述腔室内部除去未反应的硅前体和反应副产物的第一清洗步骤；和通过在腔室内部形成等离子体气氛，将所述硅薄膜形成为含硅绝缘膜的步骤。
形成含硅绝缘膜的步骤可包括注入选自O2、O3、N2和NH3的一种或多种反应气体。
所述含硅绝缘膜可以是氧化硅膜或四氮化三硅膜。
所述形成含硅绝缘膜的步骤可以包括通过注入选自Ar、He、Kr和Xe的一种或多种点火气体（ignition gas）而形成等离子体气氛。
所述点火气体可以以100sccm至3000sccm的流速注入，且所述反应气体可以以10sccm至500sccm的流速注入。
所述形成绝缘膜的步骤可以使用O2或O3作为点火气体而形成等离子体气氛。
该方法还包括：在形成绝缘膜的步骤之后用于从腔室内部除去反应副产物的第二清洗步骤，其中，可以重复进行所述沉积硅薄膜的步骤、所述形成含硅绝缘膜的步骤和所述第二清洗步骤。
所述沉积硅薄膜的步骤可以重复进行所述硅沉积步骤和所述第一清洗步骤三次至十次。
所述沉积硅薄膜的步骤也可以在保持所述腔室内部压力为0.05Torr至10Torr的同时进行。
所述形成绝缘膜的步骤也可以在保持腔室内的压力为0.05Torr至10Torr的同时进行。
形成硅薄膜的步骤可以形成由无定形硅或具有多晶性的多晶硅而形成的硅薄膜。
发明效果
本发明一个实施例的环状薄膜的沉积方法可以形成具有优异的膜性能和阶梯覆盖的含硅绝缘膜（例如氧化硅层或四氮化三硅层）。
另外，可以缩短从硅薄膜形成含硅绝缘膜的处理时间。
因此，为了实现高集成化的半导体器件，可以形成具有薄厚度的绝缘膜，而且由于绝缘膜具有优异的阶梯覆盖，因此可以实现精细结构。另外，由于绝缘膜具有优异的膜性能，因此能满足高集成化的半导体器件所需的性能。
附图说明
图1是流程图，其表示本发明一个实施例的环状薄膜的沉积方法。
图2是剖视图，其示意性表示半导体制造装置，该半导体制造装置用于进行本发明一个实施例的环状薄膜的沉积方法。
图3是表示本发明一个实施例的环状薄膜的沉积方法的图解。
图4a至4c是剖视图，其表示本发明一个实施例的沉积硅的步骤。
图5是剖视图，其表示本发明一个实施例的形成含硅的硅薄膜的状况。
图6a是剖视图，其表示本发明一个实施例的从硅薄膜形成含硅绝缘膜的步骤。
图6b是剖视图，其表示本发明一个实施例的进行第二清洗步骤的状况。
图7是剖视图，其表示本发明另一个实施例的形成含硅绝缘膜的状况。
具体实施方式
在下文中，参照附图来更详细地说明根据本发明的发明构思的实施例。然而，本发明的发明构思的实施例可以各种形式进行修改，并且本发明的范围和精神不应受限于以下描述的实施例。提供了根据本发明的发明构思的实施方案，使得本领域的技术人员可以更完全地理解本发明。在附图中，相同的附图标记是指相同的元件。此外，在附图中的各种元件和区域被示意性地示出了。因此，本发明并不限于在附图中示出的相对大小或间隔。
图1是流程图，其表示本发明实施例的环状薄膜的沉积方法。参照图1，将基底装载在半导体制造装置的腔室内部（S100）。在上述腔室内部装载的基底上形成硅薄膜（S200），为形成硅薄膜重复进行硅沉积步骤S210和第一清洗步骤S220。
为了沉积硅，可以将硅（Si）前体注入到上述腔室内部，由此将硅沉积在基底上（S210）。将硅沉积在基底上之后，进行除去未反应的硅前体和反应副产物的第一清洗步骤（S220）。然后，通过重复硅沉积步骤S210和第一清洗步骤S220，由此在基底上形成硅薄膜（S230）。
例如，可以重复硅沉积步骤S210和第一清洗步骤S220三次至十次。在每个硅沉积步骤S210中，可以在上述基底上形成一层或多层硅原子层。因此，如果重复进行硅沉积步骤S210和第一清洗步骤S220，则可以在基底上形成由无定形硅或具有多晶性的多晶硅而形成的硅薄膜（S230）。无定形硅或具有多晶性的硅薄膜可以具有几埃或几十埃
Figure BDA00002773762700031
的厚度。
随后，将在上述基底上形成的硅薄膜形成为含硅绝缘膜（S300）。例如，含硅绝缘膜可以是氧化硅膜或四氮化三硅膜。
为了从硅薄膜形成含硅绝缘膜，可将反应气体注入腔室内以在腔室内形成等离子体气氛。例如，反应气体可以是选自O2、O3、N2和NH3的一种或多种气体。
如果含硅绝缘膜是氧化硅膜，则反应气体可以是含氧原子的气体，例如O2或O3。如果含硅绝缘膜是四氮化三硅膜，反应气体可以是含氮原子的气体，例如N2或NH3。
为了将硅薄膜形成为含硅绝缘膜例如氧化硅膜，可以通过将O2或O3用作点火气体在腔室内部形成等离子体气氛。
为了将硅薄膜形成为含硅绝缘膜例如四氮化三硅膜，可以通过将N2或NH3用作点火气体在腔室中形成等离子体气氛。
随后，可以进行从腔室内部除去反应副产物和反应气体或点火气体的第二清洗步骤（S400）。
为了获得具有所需厚度的含硅绝缘膜，根据需要可以重复进行形成硅薄膜的步骤S200、形成含硅绝缘膜的步骤S300和第二清洗步骤S400（S500）。
当形成具有所需厚度的含硅绝缘膜时，基底可以从腔室中卸载（S900）。
图2是剖视图，其示意性表示半导体制造装置，该半导体制造装置用于进行本发明一个实施例的环状薄膜的沉积方法。如图2所示，形成了将反应气体引入到半导体制造装置10的腔室11内的导入部12。经由导入部12导入的反应气体可以通过喷头13喷射至腔室11内部。
作为沉积对象的基底100置于卡盘14上，该卡盘14被卡盘支座16支撑。如果必要的话，卡盘14可以向基底100施加热，使得基底100具有规定温度。通过半导体制造装置10进行沉积，此后，通过排出部分17来排出。
此外，为了形成等离子体气氛，半导体制造装置10可包括等离子体产生部18。
图3是表示本发明一个实施例的环状薄膜的沉积方法的图解。如图3所示，反复进行硅（Si）前体的注入和清洗（purge）。在反复进行硅前体的注入和清洗之后，形成等离子体气氛。在已形成等离子体气氛的状态下，可根据需要注入反应气体。
因此，从反复进行硅前体的注入和清洗到形成等离子体气氛的步骤为止作为一个周期进行。即，在通过反复进行硅前体的注入和清洗来形成硅薄膜之后，通过形成等离子体气氛来形成含硅绝缘膜，其作为一个周期进行。
因此，环状薄膜的沉积方法可以通过重复进行硅前体的注入和清洗，并通过重复进行硅薄膜的形成和绝缘膜的形成步骤而进行。
本发明一个实施例的环状薄膜的沉积方法将基于上述说明书并参照图4a至图7进行逐步地具体描述。在图4a至图7的下述说明中，可以根据需要使用图1至图3的附图标记。
图4a至图4c是剖视图，其表示本发明一个实施例的沉积硅的步骤。图4a是剖视图，其表示本发明一个实施例的注入硅前体的步骤。
如图4a所示，硅前体50被注入到装载了基底100的腔室11内。例如，基底100可以包括半导体基底如硅或化合物半导体晶片。另外，基底100可以包括不同于半导体的基底材料如玻璃、金属、陶瓷和石英等。
硅前体50例如可以是：氨基硅烷如双乙基甲基氨基硅烷(BEMAS，bisethylmethylaminosilane)、双二甲基氨基硅烷(BDMAS，bisdimethylaminosilane)、BEDAS、四乙基甲基氨基硅烷(TEMAS，tetrakisethymethylaminosilane)、四二甲基氨基硅烷(TDMAS，tetrakisidimethylaminosilane)和TEDAS或氯基硅烷如六氯乙硅烷（HCD，hexachlorinedisilan）；含硅和氢的硅烷基前体。
为了使基底100与硅前体50反应，基底100可以维持在50℃至600℃的温度。此外，装载了基底100的腔室11内部的压力可以维持在0.05Torr至10Torr。
图4b是剖视图，其表示本发明一个实施例的将硅沉积在基底上的状况。如图4b所示，通过硅前体50的一部分与基底100反应，在基底100上沉积硅原子，因此可以形成硅层112。硅层112可以由一层或多层硅原子层形成。
硅前体50可以在与基底100反应之后，形成副产物52。此外，硅前体50中的其它部分可以以未与基板100反应的未反应状态残留。
图4c是剖视图，其表示进行本发明一个实施例的第一清洗步骤的状况。如图4c所示，在基底100上形成硅层112，然后进行从腔室11内部除去未反应状态的残留硅前体50和反应副产物52的清洗。从腔室11内部除去残留的硅前体50和反应副产物52的清洗（purge）步骤可称为第一清洗步骤。
在第一清洗步骤中，基底100可以维持在50℃至600℃的温度。此外，装载了基底100的腔室11内部的压力可以维持在0.05Torr至10Torr。即，在沉积硅层112的步骤和第一清洗步骤中，可以将基底100的温度和腔室11内的压力保持一定。
图5是剖视图，其表示本发明一个实施例的沉积硅薄膜的状况。如图5所示，通过重复进行图4a至4c的步骤，将多层硅层112、114和116沉积在基底100上，从而形成由无定形硅或具有多晶性的多晶硅形成的硅薄膜110。
硅薄膜110可以具有几埃或几十埃
Figure BDA00002773762700061
的厚度。沉积硅层112的步骤和上述第一清洗步骤可以重复进行三次至十次，使得硅薄膜110包括三至十个硅层112、114和116。
由此，如果将硅薄膜110形成为多层硅层112，则硅薄膜110可以具有优异的膜性能和阶梯覆盖（step coverage）。
图6a是剖视图，其表示本发明一个实施例的从硅薄膜形成含硅绝缘膜的步骤。如图6a所示，将等离子体施加到形成了硅薄膜110的基底100上。即，在装载了基底100的腔室11内部形成等离子体气氛。为了形成等离子体气氛，也可使用电感耦合等离子体（ICP，Inductively CoupledPlasma）、电容耦合等离子体（CCP，Capacitively Coupled Plasma）或微波（MW，Microwave）等离子体。在这个时候，为了形成等离子体气氛，可以施加100W至3kW的功率。
为了形成等离子体气氛，可以注入例如选自Ar、He、Kr和Xe的一种或多种点火气体（ignition gas）和例如选自O2、O3、N2和NH3的一种或多种反应气体60。在这种情况下，点火气体可以以100sccm至3000sccm的流速注入。
另外，为了形成等离子体气氛，可以注入选自O2、O3、N2和NH3的一种或多种反应气体60。在这种情况下，反应气体起到点火气体的作用，因此可以不注入单独的点火气体。
例如，当含氧原子的气体如O2或O3用作反应气体60时，硅薄膜110可以与反应气体60中所包含的氧原子反应，从而形成氧化硅薄膜。此外，当含氮原子的气体如N2或NH3用作反应气体60时，硅薄膜110可以与反应气体60中所包含的氮原子反应，从而形成四氮化三硅膜。
为了在等离子体气氛中将硅薄膜110转变为后述的含硅绝缘膜如氧化硅膜或四氮化三硅膜，装载了基底100的腔室11的压力可以维持在0.05Torr至10Torr。
图6b是剖视图，其表示本发明一个实施例的进行含硅第二清洗步骤的状况。如图6a和6b所示，通过进行除去残留的反应气体60和反应副产物的第二清洗步骤，可以形成含硅绝缘膜120a。含硅绝缘膜120a例如可以是氧化硅膜或四氮化三硅膜。
如果将上述含硅绝缘膜120a如氧化硅膜或四氮化三硅膜在等离子体气氛中形成，则可以获得优异的膜性能。具体地，即使形成的含硅绝缘膜120a具有薄的厚度，含硅绝缘膜120a也可以具有优异的膜性能。
另外，如上所述，由于硅薄膜110具有优异的膜性能和阶梯覆盖，因此含硅绝缘膜120a也可以具有优异的膜性能和阶梯覆盖。具体地，由于含硅绝缘膜120a在等离子体气氛中形成，因此含硅绝缘膜120a可以具有更优异的膜性能。
从腔室11内部除去未反应状态的残留反应气体60或反应副产物的清洗步骤可称为第二清洗步骤。
图7是剖视图，其表示本发明另一个实施例的形成含硅绝缘膜的状况。如图7所示，通过重复进行图4a至6b中说明的步骤，可以形成包括多层含硅绝缘膜120a、120b的绝缘膜120。
当将图6a所示的硅薄膜110形成为含硅绝缘膜120a时，硅薄膜110从暴露的表面转变为绝缘膜。因此，如果硅薄膜110是厚的，则用于与硅薄膜反应的氧或氮必须穿过在硅薄膜表面上形成的绝缘膜。因此，绝缘膜的形成速度随着硅薄膜110的厚度变厚而变得缓慢。
当欲形成的绝缘膜120相对厚时，如果在形成相对薄的硅薄膜之后通过重复进行形成含硅绝缘膜的过程，则与从相对厚的硅薄膜一次性形成绝缘膜的过程相比，可以缩短处理时间。
因此，考虑处理时间和含硅绝缘膜的所需厚度，可以确定重复图4a至图6B说明的步骤的次数。
此外，本发明的绝缘膜120表示为包括两层含硅绝缘膜120a、120b，但绝缘膜120可以包括三层以上含硅绝缘膜。
本发明已经通过优选实施例详细地进行了说明，但本发明可以以其他实施例实施。因此，下述权利要求的精神和范围并不限于优选实施例。
由于本发明在不脱离其精神或基本特征的情况下可以几种形式具体化，应理解为上述实施方案并不限于任何上述的细节，除非另有规定，而是应该在所附的权利要求中所定义的其精神和范围内广泛地解释，并且因此在权利要求的边界和范围内或这些边界和范围的等同物内的所有变化和修改旨在被所附的权利要求书保护。
产业上的可利用性
本发明可适用于如沉积过程的各种各样的半导体制造工艺中。

Claims (11)

1.一种环状薄膜的沉积方法，该方法包括：
在基底上形成硅薄膜的步骤，其通过重复将硅前体注入到装载了所述基底的腔室内部而在所述基底上沉积硅的步骤、和从所述腔室内部除去未反应的硅前体和反应副产物的第一清洗步骤而进行；
通过在腔室内部形成等离子体气氛，将所述硅薄膜形成为含硅绝缘膜的步骤。
2.权利要求1所述的方法，其特征在于，
所述形成含硅绝缘膜的步骤包括注入一种或多种选自O2、O3、N2和NH3的反应气体。
3.权利要求1或2所述的方法，其特征在于，所述含硅绝缘膜是氧化硅膜或四氮化三硅膜。
4.权利要求2所述的方法，其特征在于，
形成所述绝缘膜的步骤包括通过注入一种或多种选自Ar、He、Kr和Xe的点火气体而形成等离子体气氛。
5.权利要求4所述的方法，其特征在于，
所述点火气体以100sccm至3000sccm的流速注入，且所述反应气体以10sccm至500sccm的流速注入。
6.权利要求1所述的方法，其特征在于，
所述形成绝缘膜的步骤包括使用O2或O3作为点火气体而形成等离子体气氛。
7.权利要求1所述的方法，其特征在于，
还包括：在所述形成含硅绝缘膜的步骤之后用于从腔室内部除去反应副产物的第二清洗步骤，其中，
重复进行所述形成硅薄膜的步骤、所述形成绝缘膜的步骤和所述第二清洗步骤。
8.权利要求1所述的方法，其特征在于，
所述形成硅薄膜的步骤通过重复进行所述硅沉积步骤和所述第一清洗步骤三次至十次而进行。
9.权利要求1所述的方法，其特征在于，
所述形成硅薄膜的步骤在保持腔室内部压力为0.05Torr至10Torr的同时进行。
10.权利要求1所述的方法，其特征在于，
所述形成绝缘膜的步骤在保持腔室内部压力为0.05Torr至10Torr的同时进行。
11.权利要求1所述的方法，其特征在于，
所述形成硅薄膜的步骤形成由无定形硅或具有多晶性的多晶硅形成的硅薄膜。
CN201180036357.XA 2010-08-02 2011-08-01 环状薄膜的沉积方法 Active CN103026472B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
KR1020100074605A KR101147728B1 (ko) 2010-08-02 2010-08-02 사이클릭 박막 증착 방법
KR10-2010-0074605 2010-08-02
PCT/KR2011/005649 WO2012018210A2 (ko) 2010-08-02 2011-08-01 사이클릭 박막 증착 방법

Publications (2)

Publication Number Publication Date
CN103026472A true CN103026472A (zh) 2013-04-03
CN103026472B CN103026472B (zh) 2015-08-26

Family

ID=45559916

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201180036357.XA Active CN103026472B (zh) 2010-08-02 2011-08-01 环状薄膜的沉积方法

Country Status (6)

Country Link
US (1) US8828890B2 (zh)
JP (1) JP2013542580A (zh)
KR (1) KR101147728B1 (zh)
CN (1) CN103026472B (zh)
TW (1) TWI462156B (zh)
WO (1) WO2012018210A2 (zh)

Families Citing this family (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9997357B2 (en) 2010-04-15 2018-06-12 Lam Research Corporation Capped ALD films for doping fin-shaped channel regions of 3-D IC transistors
US8956983B2 (en) 2010-04-15 2015-02-17 Novellus Systems, Inc. Conformal doping via plasma activated atomic layer deposition and conformal film deposition
US9373500B2 (en) 2014-02-21 2016-06-21 Lam Research Corporation Plasma assisted atomic layer deposition titanium oxide for conformal encapsulation and gapfill applications
US9257274B2 (en) 2010-04-15 2016-02-09 Lam Research Corporation Gapfill of variable aspect ratio features with a composite PEALD and PECVD method
US9390909B2 (en) 2013-11-07 2016-07-12 Novellus Systems, Inc. Soft landing nanolaminates for advanced patterning
US8728956B2 (en) 2010-04-15 2014-05-20 Novellus Systems, Inc. Plasma activated conformal film deposition
US8637411B2 (en) 2010-04-15 2014-01-28 Novellus Systems, Inc. Plasma activated conformal dielectric film deposition
US9611544B2 (en) 2010-04-15 2017-04-04 Novellus Systems, Inc. Plasma activated conformal dielectric film deposition
US9892917B2 (en) 2010-04-15 2018-02-13 Lam Research Corporation Plasma assisted atomic layer deposition of multi-layer films for patterning applications
US9287113B2 (en) 2012-11-08 2016-03-15 Novellus Systems, Inc. Methods for depositing films on sensitive substrates
US9076646B2 (en) 2010-04-15 2015-07-07 Lam Research Corporation Plasma enhanced atomic layer deposition with pulsed plasma exposure
US9685320B2 (en) 2010-09-23 2017-06-20 Lam Research Corporation Methods for depositing silicon oxide
US8647993B2 (en) 2011-04-11 2014-02-11 Novellus Systems, Inc. Methods for UV-assisted conformal film deposition
US8592328B2 (en) 2012-01-20 2013-11-26 Novellus Systems, Inc. Method for depositing a chlorine-free conformal sin film
KR101416069B1 (ko) * 2012-04-02 2014-07-07 주식회사 아이브이웍스 저온 박막 증착 방법
TWI595112B (zh) 2012-10-23 2017-08-11 蘭姆研究公司 次飽和之原子層沉積及保形膜沉積
SG2013083241A (en) 2012-11-08 2014-06-27 Novellus Systems Inc Conformal film deposition for gapfill
JP6087609B2 (ja) * 2012-12-11 2017-03-01 東京エレクトロン株式会社 金属化合物膜の成膜方法、成膜装置、および電子製品の製造方法
KR101494274B1 (ko) * 2013-11-08 2015-02-17 주식회사 유진테크 사이클릭 박막 증착 방법 및 반도체 제조 방법, 그리고 비휘발성 메모리 셀
KR101551199B1 (ko) * 2013-12-27 2015-09-10 주식회사 유진테크 사이클릭 박막 증착 방법 및 반도체 제조 방법, 그리고 반도체 소자
US9214334B2 (en) 2014-02-18 2015-12-15 Lam Research Corporation High growth rate process for conformal aluminum nitride
US9478411B2 (en) 2014-08-20 2016-10-25 Lam Research Corporation Method to tune TiOx stoichiometry using atomic layer deposited Ti film to minimize contact resistance for TiOx/Ti based MIS contact scheme for CMOS
US9478438B2 (en) 2014-08-20 2016-10-25 Lam Research Corporation Method and apparatus to deposit pure titanium thin film at low temperature using titanium tetraiodide precursor
US9214333B1 (en) 2014-09-24 2015-12-15 Lam Research Corporation Methods and apparatuses for uniform reduction of the in-feature wet etch rate of a silicon nitride film formed by ALD
US9564312B2 (en) 2014-11-24 2017-02-07 Lam Research Corporation Selective inhibition in atomic layer deposition of silicon-containing films
US9589790B2 (en) 2014-11-24 2017-03-07 Lam Research Corporation Method of depositing ammonia free and chlorine free conformal silicon nitride film
US10566187B2 (en) 2015-03-20 2020-02-18 Lam Research Corporation Ultrathin atomic layer deposition film accuracy thickness control
US9502238B2 (en) 2015-04-03 2016-11-22 Lam Research Corporation Deposition of conformal films by atomic layer deposition and atomic layer etch
US10526701B2 (en) 2015-07-09 2020-01-07 Lam Research Corporation Multi-cycle ALD process for film uniformity and thickness profile modulation
US9601693B1 (en) 2015-09-24 2017-03-21 Lam Research Corporation Method for encapsulating a chalcogenide material
US9773643B1 (en) 2016-06-30 2017-09-26 Lam Research Corporation Apparatus and method for deposition and etch in gap fill
US10062563B2 (en) 2016-07-01 2018-08-28 Lam Research Corporation Selective atomic layer deposition with post-dose treatment
US10629435B2 (en) 2016-07-29 2020-04-21 Lam Research Corporation Doped ALD films for semiconductor patterning applications
US10074543B2 (en) 2016-08-31 2018-09-11 Lam Research Corporation High dry etch rate materials for semiconductor patterning applications
US10037884B2 (en) 2016-08-31 2018-07-31 Lam Research Corporation Selective atomic layer deposition for gapfill using sacrificial underlayer
US9865455B1 (en) 2016-09-07 2018-01-09 Lam Research Corporation Nitride film formed by plasma-enhanced and thermal atomic layer deposition process
US10832908B2 (en) 2016-11-11 2020-11-10 Lam Research Corporation Self-aligned multi-patterning process flow with ALD gapfill spacer mask
US10454029B2 (en) 2016-11-11 2019-10-22 Lam Research Corporation Method for reducing the wet etch rate of a sin film without damaging the underlying substrate
US10134579B2 (en) 2016-11-14 2018-11-20 Lam Research Corporation Method for high modulus ALD SiO2 spacer
US10176984B2 (en) 2017-02-14 2019-01-08 Lam Research Corporation Selective deposition of silicon oxide
US10559461B2 (en) 2017-04-19 2020-02-11 Lam Research Corporation Selective deposition with atomic layer etch reset
US10269559B2 (en) 2017-09-13 2019-04-23 Lam Research Corporation Dielectric gapfill of high aspect ratio features utilizing a sacrificial etch cap layer
US10460930B2 (en) * 2017-11-22 2019-10-29 Lam Research Corporation Selective growth of SiO2 on dielectric surfaces in the presence of copper
WO2019169335A1 (en) 2018-03-02 2019-09-06 Lam Research Corporation Selective deposition using hydrolysis
KR20200021834A (ko) * 2018-08-21 2020-03-02 주성엔지니어링(주) 박막 형성 장치 및 이를 이용한 박막 형성 방법

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080038936A1 (en) * 2002-07-19 2008-02-14 Asm America, Inc. Method to form ultra high quality silicon-containing compound layers
CN101304001A (zh) * 2007-03-15 2008-11-12 应用材料股份有限公司 在含有电介质材料的硅形成中改进的空隙填充沉积
TW200947527A (en) * 2008-03-14 2009-11-16 Tokyo Electron Ltd Film formation apparatus for semiconductor process and method for using same

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100275738B1 (ko) * 1998-08-07 2000-12-15 윤종용 원자층 증착법을 이용한 박막 제조방법
KR20020081902A (ko) 2001-04-20 2002-10-30 아남반도체 주식회사 산소 라디칼을 이용한 실리콘 산화막의 제조 방법
TWI287253B (en) * 2002-09-30 2007-09-21 Adv Lcd Tech Dev Ct Co Ltd Substrate processing apparatus and substrate processing method
JP4563113B2 (ja) * 2004-08-26 2010-10-13 株式会社日立国際電気 シリコン酸化膜の形成方法、半導体デバイスの製造方法および基板処理装置
KR100734393B1 (ko) * 2005-11-28 2007-07-02 주식회사 에이이티 실리콘 박막의 원자층 증착 방법
JP5008957B2 (ja) * 2006-11-30 2012-08-22 東京エレクトロン株式会社 シリコン窒化膜の形成方法、形成装置、形成装置の処理方法及びプログラム
US7947981B2 (en) * 2007-01-30 2011-05-24 Semiconductor Energy Laboratory Co., Ltd. Display device
US20090041952A1 (en) 2007-08-10 2009-02-12 Asm Genitech Korea Ltd. Method of depositing silicon oxide films
US7928019B2 (en) * 2007-08-10 2011-04-19 Micron Technology, Inc. Semiconductor processing
JP5233562B2 (ja) * 2008-10-04 2013-07-10 東京エレクトロン株式会社 成膜方法及び成膜装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080038936A1 (en) * 2002-07-19 2008-02-14 Asm America, Inc. Method to form ultra high quality silicon-containing compound layers
CN101304001A (zh) * 2007-03-15 2008-11-12 应用材料股份有限公司 在含有电介质材料的硅形成中改进的空隙填充沉积
TW200947527A (en) * 2008-03-14 2009-11-16 Tokyo Electron Ltd Film formation apparatus for semiconductor process and method for using same

Also Published As

Publication number Publication date
TWI462156B (zh) 2014-11-21
WO2012018210A2 (ko) 2012-02-09
CN103026472B (zh) 2015-08-26
WO2012018210A3 (ko) 2012-05-03
TW201227807A (en) 2012-07-01
KR20120012579A (ko) 2012-02-10
JP2013542580A (ja) 2013-11-21
KR101147728B1 (ko) 2012-05-25
US20130115783A1 (en) 2013-05-09
US8828890B2 (en) 2014-09-09

Similar Documents

Publication Publication Date Title
CN103026472B (zh) 环状薄膜的沉积方法
US20210035854A1 (en) Method of forming a structure using fluorine removal
TWI474399B (zh) 循環沉積薄膜之方法
US9984868B2 (en) PEALD of films comprising silicon nitride
US8076242B2 (en) Methods of forming an amorphous silicon thin film
KR20180058232A (ko) SiO 및 SiN을 포함하는 유동성 막들을 증착시키는 방법들
TWI729285B (zh) 金屬薄膜的選擇性沈積
KR20090016403A (ko) 실리콘 산화막 증착 방법
KR20170038023A (ko) ＳｉＣＯＮ의 저온 분자층 증착
TWI553143B (zh) 薄膜形成之循環性沉積方法，半導體製造方法，及半導體裝置
JP2004165668A (ja) ハフニウム化合物を利用した薄膜蒸着方法
KR20200099975A (ko) 성막 방법, 성막 처리용의 처리 용기의 클리닝 방법 및 성막 장치
WO2004044898A2 (en) Nitridation of high-k dielectrics
KR20160062370A (ko) 반도체 소자의 제조방법
JP6441494B2 (ja) 半導体装置の製造方法、基板処理装置およびプログラム
TW201443274A (zh) 使用二矽氧烷先質之膜的沉積
CN111146077A (zh) 一种改善薄膜缺陷的方法
US20230142684A1 (en) Single Precursor Low-K Film Deposition and UV Cure for Advanced Technology Node
TW201622005A (zh) 絕緣膜之沉積方法
KR20160061129A (ko) 적층막 제조방법
TW202217044A (zh) 具有抗蝕刻氮化物層之半導體元件的製備方法
KR101302592B1 (ko) 실리콘 화합물 박막의 형성방법
JP2024085397A (ja) 窒化ホウ素を成膜するための方法およびシステム
KR20060027087A (ko) 원자층 증착을 이용하여 기판 상에 하프늄 질화막을형성하는 방법
TW201606116A (zh) 具低蝕刻率之氧化薄膜之沉積方法及半導體裝置

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant