TWI474399B - 循環沉積薄膜之方法 - Google Patents

循環沉積薄膜之方法 Download PDF

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TWI474399B
TWI474399B TW100127081A TW100127081A TWI474399B TW I474399 B TWI474399 B TW I474399B TW 100127081 A TW100127081 A TW 100127081A TW 100127081 A TW100127081 A TW 100127081A TW I474399 B TWI474399 B TW I474399B
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insulating film
ruthenium
reaction
gas
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Hai Won Kim
Sang Ho Woo
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Eugene Technology Co Ltd
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Description

循環沈積薄膜之方法
本發明所揭示之內容係關於一種循環沈積薄膜之方法,且更具體地說,係指一種循環沈積薄膜之方法,其係形成一含矽絕緣膜。
隨著半導體業界之進展與近來使用者的需求,電子裝置經更高度整合並具高效率,因此,做為電子裝置主要組件之半導體裝置亦需經高度整合,並具高效率。不過,實現高度整合半導體裝置的精細結構是困難的。
例如,完成精細結構需要較薄之絕緣膜,但若要將絕緣膜形成為厚度薄之絕緣膜,則膜性質(如:絕緣特性)將會降低。而且,當獲得優異的階梯覆蓋率(step coverage)時,形成厚度薄之薄膜變得更加困難。
本發明之目的在於解決上述問題,並提供一種沈積絕緣膜方法,該絕緣膜具有優異膜性質及階梯覆蓋率。更具體地說,本發明提供一種循環沈積薄膜之方法,該環狀薄膜具有優異膜性質及階梯覆蓋率。
透過下列詳細說明及附圖,將更清楚了解本發明之其他目的。
依據一目的,本發明提供一種沈積循環沈積薄膜之方法,包含:沈積絕緣膜步驟,其係重複進行一矽沈積步驟、一第一清洗步驟、一反應步驟以及一第二清洗步驟,該矽沈積步驟,藉由將一矽前驅物注入至載有該基材之一反應室,來將矽沈積至一基材上,該第一清洗步驟,用以移除 來自該反應室之未反應矽前驅物以及反應副產物,該反應步驟,藉由供應一第一反應氣體至該反應室,來形成沈積矽作為一含矽絕緣膜,以及該第二清洗步驟,用於移除來自該反應室之未反應之第一反應氣體以及反應副產物,以及;緻密化該含矽絕緣膜,其藉由供應一電漿氣氛至該反應室來進行。
該第一反應氣體可為一種以上之氣體,其係選自於由:O2 、O3 、N2 及NH3 所組成之群。
該含矽絕緣膜可為氧化矽膜或氮化矽膜。
該緻密化該含矽絕緣膜步驟可包含:藉由注入一種以上之點火氣體形成電漿氣氛,該點火氣體選自於由:Ar、He、Kr及Xe所組成之群。
該反應步驟可使用O* (氧自由基)或O2- (氧陰離子)作為該第一反應氣體,其係由使用於O2 氣氛而形成。
該緻密化含矽絕緣膜步驟可包含:注入一種以上之第二反應氣體,該第二反應氣體係選自於由:O2 、O3 、N2 及NH3 所組成之群。
當反應室內壓力維持於0.05Torr至10Torr時,可進行沈積絕緣膜步驟。
當反應室內壓力維持於0.05Torr至10Torr時,可進行緻密化含矽絕緣膜步驟。
進行該緻密化含矽絕緣膜步驟前,可重複進行沈積步驟、第一清洗步驟、反應步驟以及第二清洗步驟3至10次。
可重複進行該沈積絕緣膜步驟及該緻密化含矽絕緣膜步驟。
以下,將參考附圖,詳細介紹根據本發明之發明構思 的實施樣態。然而,本發明之發明構思的實施樣態可以各種形式加以修飾,而且本發明的範圍和精神不應解釋為受限於下述之實施樣態。提供根據本發明之發明構思的實施樣態,該技術領域中熟習該項技術者可更充分理解本發明。在附圖中,類似參考編號係指相似元件。此外,附圖中的各種元件和區域為示意性描述。因此,本發明不僅限於附圖中描述的相對大小或間距。
第1圖係為依據本發明之一實施樣態,說明一種循環沈積薄膜之方法的流程圖。
參考第1圖,將一基材載入半導體製造設備之一反應室S100。在載入反應室之基材上沈積一絕緣膜S200,且在步驟S200中,一起進行矽沈積步驟S210、第一清洗步驟S220、反應步驟S230以及第二清洗步驟S240以沈積該絕緣膜。
在步驟S210中,藉由將一矽前驅物注入至用於沈積矽之反應室,將矽沈積於該基材上。在矽沈積於該基材上後,在步驟S220中,進行該第一清洗步驟,移除來自該反應室之未反應矽前驅物以及反應副產物。
因此,在步驟S230中,進行反應步驟,藉由將形成於基材上之矽與一反應氣體反應,來形成含矽絕緣膜。例如,該含矽絕緣膜可為氧化矽膜或氮化矽膜。
為了形成矽作為含矽絕緣膜,可將一第一反應氣體注入於該反應室中。該第一反應氣體可為一種以上之氣體,其係選自於由:O2 、O3 、N2 及NH3 所組成之群組。
當含矽絕緣膜為氧化矽膜時,該第一反應氣體可為含氧原子之氣體,如O2 或O3 。或者,該第一反應氣體可為O* (氧自由基)或O2- (氧陰離子),其係於O2 氣氛中由電漿所形成。當含矽絕緣膜為氮化矽膜時,該第一反應氣體可 為含氮原子之氣體,如N2 或NH3
因此,在步驟S240中,進行第二清洗步驟,用於自該反應室移除反應副產物及反應氣體或點火氣體。
可重複進行矽沈積步驟S210、第一清洗步驟S220、反應步驟S230以及第二清洗步驟S240。可重複進行矽沈積步驟S210、第一清洗步驟S220、反應步驟S230以及第二清洗步驟S240,如:3至10次。
沈積含矽絕緣膜步驟S200、矽沈積步驟S210、第一清洗步驟S220、反應步驟S230以及第二清洗步驟S240中,基材之溫度與反應室內之壓力維持恆定。
各矽沈積步驟S210中,可在基材上形成至少一種矽原子層。可形成含矽絕緣膜以具有數Å或10Å之厚度。形成含矽絕緣膜後,在步驟S300中,進行緻密化含矽絕緣膜步驟。
緻密化該含矽絕緣膜,可在反應室內形成電漿氣氛。而且,第二反應氣體可額外注入反應室,與電漿氣氛一起。該第二反應氣體可為一種以上之氣體,其係選自於由:O2 、O3 、N2 及NH3 所組成之群組。
為了獲得含矽絕緣膜及所需厚度,在步驟S400中,如有需要可重複進行沈積絕緣膜步驟S200及緻密化絕緣膜步驟S300。
在步驟S900中,當含矽並具所需厚度之絕緣膜形成時,可將基材自反應室卸下。
第2圖係為依據本發明之一實施樣態,說明進行一種循環沈積薄膜之方法的半導體製造設備之剖面示意圖。
參考第2圖,於一半導體製造設備10之反應室11,設有一導入單元12,以將反應氣體導入。反應氣體藉由導入單元12導入,係可透過一噴頭13噴灑進反應室11。
將用於沈積之基材100置於一夾盤(chuck)14,該夾盤14係由一夾盤座16支撐。如有需要,夾盤14係對基材100加熱,以使基材100具特定溫度。沈積作用藉由半導體製造設備10進行,並於其後以一排出單元(discharge part)17進行排出。
而且,為了形成一電漿氣氛,該半導體製造設備10可包含一電漿產生單元18。
第3圖係為依據本發明之一實施樣態,描述一種循環沈積薄膜之方法的示意圖。
參考第3圖,重複進行矽前驅物之注入及清洗和第一反應氣體之注入及清洗。可重複進行在矽前驅物注入後的清洗,以及第一反應氣體注入後的清洗,接著形成電漿氣氛。在電漿氣氛已形成之狀態中,如有需要可注入第二反應氣體。
如此一來,由重複進行矽前驅物注入及清洗步驟以及第一反應氣體注入及清洗步驟,至形成電漿氣氛步驟作為一個循環。意即,藉由重複進行矽前驅物注入及清洗,以及反應氣體注入及清洗,來形成含矽絕緣膜,並於其後,形成電漿氣氛來緻密化含矽絕緣膜。
而且,藉由重複所有上述步驟,能獲得含矽絕緣膜並具有所需厚度。
因此,可以重複進行矽前驅物注入及清洗,以及第一反應氣體注入及清洗,而且,藉由重複進行形成並緻密化含矽絕緣膜步驟,來實行循環沈積薄膜之方法。
依據本發明之一實施樣態,循環沈積薄膜之方法將基於上述說明,參考第4A至8圖,加以具體描述。以下第4A至8圖中的說明,如有需要可使用第1至3圖之參考編號。
第4A至C圖係為依據本發明之一實施樣態,說明沈積 矽步驟之剖面圖。第4A圖係為依據本發明之一實施樣態,說明注入矽前驅物步驟之剖面圖。
參考第4A圖,將一矽前驅物50注入至載有基材100之反應室11。
基材100,舉例來說,可包括:一半導體基材,如:矽或化合物半導體晶圓。或者,基材100可包括:與半導體不同之基材材料,如:玻璃、金屬、陶瓷及石英。
矽前驅物50,舉例來說,可為胺系矽烷(如:雙乙基甲胺基矽烷(bisethylmethylaminosilane,BEMAS)、雙二甲胺基矽烷(bisdimethylaminosilane,BDMAS)、BEDAS、四乙基甲胺基矽烷(tetrakisethylmethylaminosilane,TEMAS)、四二乙基甲胺基矽烷(tetrakisidimethylaminosilane,TDMAS)及TEDAS;氯系矽烷(如:六氯二矽烷(hexachlorinedisilane,HCD)。
基材100可維持於約50℃至約600℃之溫度,以與矽前驅物50反應。而且,載有基材100之反應室11,其內壓力可維持於約0.05Torr至約10Torr。
第4B圖係為依據本發明之一實施樣態,說明在基材上沈積矽步驟之剖面圖。參考第4B圖,以部分矽前驅物50與基材100反應,可將矽原子置於基材100上,因此可形成一矽層112。矽層112可由至少一種矽原子層形成。
部分矽前驅物50可與基材100反應,因而形成一種以上之反應副產物52。而且,其他部分矽前驅物50可維持在一未反應狀態,不與基材100反應。
第4C圖係為依據本發明之一實施樣態,說明進行第一清洗步驟之剖面圖。參考第4C圖,矽層112形成於基材100上,接著可進行一清洗步驟,由反應室11移除剩餘的未反應狀態矽前驅物50以及已反應之副產物52。自該反應室 11移除剩餘的未反應狀態矽前驅物50以及已反應之副產物52之清洗步驟,可稱之為第一清洗步驟。
第一清洗步驟中,基材100可維持於約50℃至約600℃之溫度。而且,載有基材100之反應室11,其內壓力維持於0.05Torr至10Torr。意即,在沈積矽層112及第一清洗步驟中,基材100之溫度與反應室11內之壓力維持恆定。
第5A至C圖係為依據本發明之一實施樣態,描述形成含矽絕緣膜步驟之剖面圖。第5A圖係為依據本發明之一實施樣態,描述反應氣體注入步驟之剖面圖。
參考第5A圖,將一第一反應氣體60注入至載有基材100之反應室11。該第一反應氣體60可為一種以上之氣體,其係選自於由:O2 、O3 、N2 及NH3 所組成之群組。或者,該第一反應氣體60,舉例來說,可為O* (氧自由基)或O2- (氧陰離子),其係在O2 氣氛中使用電漿所形成。
基材100可維持於約50℃至約600℃之溫度,以與第一反應氣體60反應。而且,載有基材100之反應室11,其內壓力可維持於約0.05Torr至約10Torr。
第5B圖係為依據本發明之一實施樣態,說明在基材上沈積含矽絕緣膜步驟之剖面圖。參考第5B圖,以部分第一反應氣體60與矽層112反應,可在基材100上形成絕緣膜122a。
第一反應氣體60可與矽層112反應,因而形成副產物62。而且,其他部分第一反應氣體60可維持在一未反應狀態,不與矽層112反應。
如,當含氧原子之氣體,如O2 或O3 作為第一反應氣體60時,或將在O2 氣氛中,由電漿所形成的O* (氧自由基)或O2- (氧陰離子)作為第一反應氣體60時,矽層112可與第一反應氣體60中所含氧原子反應,因而形成氧化矽 層。或者,當含氮原子之氣體,如N2 或NH3 作為第一反應氣體60時,矽層112可與第一反應氣體60中所含氮原子反應,因而形成氮化矽層。
第5C圖係為依據本發明之一實施樣態,說明進行第二清洗步驟之剖面圖。參考第5C圖,矽層112形成於基材100上,接著可進行一清洗步驟,由反應室11移除剩餘的,處於未反應狀態之第一反應氣體60,以及已反應之副產物62。自該反應室11移除剩餘的第一反應氣體60,以及已反應之副產物62之清洗步驟,可稱之為第二清洗步驟。
第二清洗步驟中,基材100可維持於約50℃至約600℃之溫度。而且,載有基材100之反應室11,其內壓力維持於0.05Torr至10Torr。
第6圖係為依據本發明之一實施樣態,說明形成複數含矽絕緣膜之剖面圖。參考第6圖,藉由重複第4A圖至第5C圖之步驟,形成絕緣膜122,其包括複數含矽絕緣膜122a至122c。
絕緣膜122可具有數Å或10Å之厚度。沈積各含矽絕緣膜122a、122b或122c之步驟可重複進行3至10次,以使絕緣膜122包含3至10層含矽絕緣膜122a至122c。
以此方式,若形成包括複數含矽絕緣膜122a至122c之絕緣膜122,則絕緣膜122可具有優異膜性質及階梯覆蓋率。
第7A及B圖係為依據本發明之一實施樣態,說明緻密化絕緣膜步驟之剖面圖。第7A圖係為依據本發明之一實施樣態,說明供應電漿氣氛至絕緣膜步驟之剖面圖。
參考第7A圖,將電漿施用於形成絕緣膜122之基材100上。意即,載有基材100之反應室11內形成一電漿氣氛。為了形成電漿氣氛,可使用電感耦合電漿(Inductively Coupled Plasma,ICP)、電容耦合電漿(Capacitively Coupled Plasma,CCP)或微波(Microwave,MW)電漿。此時,可施予約100W至約3kW的功率來形成電漿氣氛。
為了形成電漿氣氛,可注入一種以上之點火氣體,該點火氣體選自於由:Ar、He、Kr及Xe所組成之群組。在此例中,點火氣體可以約100sccm至約3000sccm之流速注入。
在電漿氣氛下,第二反應氣體64可額外注入反應室,以使絕緣膜122更加緻密化。第二反應氣體64,舉例來說,可為一種以上之氣體,其係選自於由:O2 、O3 、N2 及NH3 所組成之群組,或者為在O2 氣氛中,由電漿所形成的O* (氧自由基)或O2- (氧陰離子)。
例如,當絕緣膜122為氧化矽膜時,含氧原子之氣體可作為第二反應氣體64,如O2 或O3 ,或者在O2 氣氛中由電漿所形成的O* (氧自由基)或O2- (氧陰離子),或者氫可作為第二反應氣體64。
例如:當含矽絕緣膜為氮化矽膜時,該反應氣體可作為第二反應氣體64,如N2 或NH3 ,或者,氫可作為第二反應氣體64。
第7B圖係為依據本發明之一實施樣態,說明形成緻密化絕緣膜122D步驟之剖面圖。參考第7A及B圖,絕緣膜122可在電漿氣氛中緻密化,並因此形成緻密化絕緣膜122D。為了形成緻密化絕緣膜122D,載有基材100之反應室11,其內壓力維持於約0.05Torr至10Torr。
而且,藉由在電漿氣氛中處理絕緣膜122,所獲得之緻密化絕緣膜122D,可於絕緣特性中具良好的膜性質。特別是,即使當形成具薄厚度的緻密化絕緣膜122D時,緻密化絕緣膜122D仍可具良好的膜性質。
第8圖係為依據本發明之一實施樣態,說明含矽絕緣膜之剖面圖。參考圖8,藉由重複上述第4A圖至第7B圖之步驟,可形成絕緣膜120,其包括複數緻密化絕緣膜122D及124D。
若第7A圖所示之絕緣膜122相對較厚時,電漿或第二反應氣體64對絕緣膜122較低部分之影響相對較小。因此,為了更增進絕緣膜120之膜性質,形成絕緣膜120,其包括複數緻密化絕緣膜122D及124D,以具有相對較薄厚度。
而且,儘管以包括兩個緻密化絕緣膜122D及124D來說明絕緣膜120,但絕緣膜120仍可包括三個以上的緻密化絕緣膜。意即,考量絕緣膜120所需厚度,可決定絕緣膜120中所包含的緻密化絕緣膜數目。換言之,考量絕緣膜120所需厚度,可決定重複第4A圖至第7B圖之步驟的次數。
依據本發明之一實施樣態,循環沈積薄膜之方法可形成具有優異膜性質及階梯覆蓋率的絕緣膜(如:氧化矽層或氮化矽層)。
因此,可形成厚度薄的絕緣膜完成高度整體之半導體裝置,而且由於絕緣膜具有優異的階梯覆蓋率,因此可實現精細結構。而且,由於絕緣膜具良好的膜性質,因此循環沈積薄膜之方法可滿足高度整合之半導體裝置所需之效能。
本發明已透過較佳實施樣態加以描述,但本發明也可以其他實施樣態加以實施。因此,下述申請專利範圍的技術精神和範圍並不限於較佳實施樣態。
由於本發明可以不悖離其精神和必要特徵之方式具體化,亦應理解為上述實施樣態並未被前述說明之任何細節 所限制,除非另有說明,而是如所附申請專利範圍所定義的,在其精神和範圍內應寬廣解釋,並且因此落入申請專利範圍界限與範圍的所有變化和修飾,或此等界限與範圍的均等物因而成為由所附申請專利範圍所涵蓋。
S100‧‧‧載入基材
S200‧‧‧沉積絕緣膜
S210‧‧‧沉積矽
S220‧‧‧第一清洗
S230‧‧‧反應
S240‧‧‧第二清洗
S250‧‧‧重複
S300‧‧‧緻密化
S400‧‧‧重複
S900‧‧‧卸下基材
10‧‧‧半導體製造設備
11‧‧‧反應室
12‧‧‧導入單元
13‧‧‧噴頭
14‧‧‧夾盤
16‧‧‧夾盤座
17‧‧‧排出單元
18‧‧‧電漿產生單元
100‧‧‧基材
112‧‧‧矽層
120,122‧‧‧絕緣膜
120a,120b,120c‧‧‧含矽絕緣膜
122D,124D‧‧‧緻密化絕緣膜
50‧‧‧矽前驅物
52‧‧‧副產物
60‧‧‧第一反應氣體
62‧‧‧副產物
64‧‧‧第二反應氣體
第1圖係為依據本發明之一實施樣態,說明一種循環沈積薄膜之方法的流程圖。
第2圖係為依據本發明之一實施樣態,說明進行一種循環沈積薄膜之方法的半導體製造設備之剖面示意圖。
第3圖係為依據本發明之一實施樣態,描述一種循環沈積薄膜之方法的示意圖。
第4A至C圖係為依據本發明之一實施樣態,說明沈積矽步驟之剖面圖。
第5A至C圖係為依據本發明之一實施樣態,說明形成含矽絕緣膜步驟之剖面圖。
第6圖係為依據本發明之一實施樣態,說明由複數矽所形成之絕緣膜之剖面圖。
第7A至B圖係為依據本發明之一實施樣態,說明緻密化絕緣膜步驟之剖面圖。
第8圖係為依據本發明之另一實施樣態,說明由矽形成之絕緣膜之剖面圖。
S100‧‧‧載入基材
S200‧‧‧沉積絕緣膜
S210‧‧‧沉積矽
S220‧‧‧第一清洗
S230‧‧‧反應
S240‧‧‧第二清洗
S250‧‧‧重複
S300‧‧‧緻密化
S400‧‧‧重複
S900‧‧‧卸下基材

Claims (8)

  1. 一種循環沈積薄膜之方法,該方法包含步驟:沈積一絕緣膜,其係重複進行一矽沈積步驟、一第一清洗步驟、一反應步驟以及一第二清洗步驟,該矽沈積步驟,藉由將一矽前驅物注入至載有該基材之一反應室,來將矽沈積至一基材上,該第一清洗步驟,用以移除來自該反應室之未反應矽前驅物以及反應副產物,該反應步驟,藉由供應一第一反應氣體至該反應室,來形成沈積矽為一含矽絕緣膜,以及該第二清洗步驟,係用於移除來自該反應室之未反應之第一反應氣體以及反應副產物,以及緻密化該含矽絕緣膜,其藉由供應一電漿氣氛至該反應室來進行;其中該緻密化含矽絕緣膜步驟進一步包含:注入一種以上之第二反應氣體,當該含矽絕緣膜為氧化矽膜時,該第二反應氣體係選自於由:O2 及O3 所組成之群,或者當該含矽絕緣膜為氮化矽膜時,該第二反應氣體係選自於由:N2 及NH3 所組成之群組。
  2. 如申請專利範圍第1項所述之方法,其中該第一反應氣體可為一種以上之氣體,其係選自於由:O2 、O3 、N2 及NH3 所組成之群組。
  3. 如申請專利範圍第2項所述之方法,其中該緻密化步驟包含:藉由注入一種以上之點火氣體形成電漿氣氛,該點火氣體選自於由:Ar、He、Kr及Xe所組成之群組。
  4. 如申請專利範圍第1項所述之方法,其中該反應步驟係由使用於O2 氣氛,來形成O* (氧自由基)或O2- (氧陰離子),以作為該第一反應氣體。
  5. 如申請專利範圍第1項所述之方法,其中當反應室內壓力維持於0.05Torr至10Torr時,進行該沈積絕緣膜步 驟。
  6. 如申請專利範圍第1項所述之方法,其中當室內壓力維持於0.05Torr至10Torr時,進行該緻密化含矽絕緣膜步驟。
  7. 如申請專利範圍第1項所述之方法,其中進行該緻密化含矽絕緣膜步驟前,重複進行該沈積步驟、該第一清洗步驟、該反應步驟以及該第二清洗步驟3至10次。
  8. 如申請專利範圍第1項所述之方法,其中該沈積絕緣膜步驟及該緻密化含矽絕緣膜步驟係重複進行。
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Families Citing this family (10)

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KR101494274B1 (ko) * 2013-11-08 2015-02-17 주식회사 유진테크 사이클릭 박막 증착 방법 및 반도체 제조 방법, 그리고 비휘발성 메모리 셀
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KR101576637B1 (ko) * 2014-07-15 2015-12-10 주식회사 유진테크 고종횡비를 가지는 오목부 상에 절연막을 증착하는 방법
TW201606116A (zh) * 2014-08-08 2016-02-16 尤金科技有限公司 具低蝕刻率之氧化薄膜之沉積方法及半導體裝置
KR101576639B1 (ko) * 2014-09-18 2015-12-10 주식회사 유진테크 절연막 증착 방법
KR102362534B1 (ko) * 2014-12-08 2022-02-15 주성엔지니어링(주) 기판 처리방법
JP2017139297A (ja) * 2016-02-02 2017-08-10 東京エレクトロン株式会社 成膜方法及び成膜装置
KR102125474B1 (ko) * 2016-12-05 2020-06-24 주식회사 원익아이피에스 박막 증착 방법
SG11202010449RA (en) * 2018-06-19 2021-01-28 Applied Materials Inc Pulsed plasma deposition etch step coverage improvement
KR102671466B1 (ko) * 2018-11-13 2024-06-03 주성엔지니어링(주) 저온 결정질 실리콘 형성방법

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070065578A1 (en) * 2005-09-21 2007-03-22 Applied Materials, Inc. Treatment processes for a batch ALD reactor
TW200814205A (en) * 2006-07-12 2008-03-16 Applied Materials Inc A method for fabricating a gate dielectric layer utilized in a gate structure

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6140246A (en) * 1997-12-18 2000-10-31 Advanced Micro Devices, Inc. In-situ P doped amorphous silicon by NH3 to form oxidation resistant and finer grain floating gates
KR20020081902A (ko) * 2001-04-20 2002-10-30 아남반도체 주식회사 산소 라디칼을 이용한 실리콘 산화막의 제조 방법
US7297641B2 (en) * 2002-07-19 2007-11-20 Asm America, Inc. Method to form ultra high quality silicon-containing compound layers
JP4257576B2 (ja) * 2003-03-25 2009-04-22 ローム株式会社 成膜装置
DE10319540A1 (de) * 2003-04-30 2004-11-25 Infineon Technologies Ag Verfahren zur ALD-Beschichtung von Substraten sowie eine zur Durchführung des Verfahrens geeignete Vorrichtung
US7192849B2 (en) * 2003-05-07 2007-03-20 Sensor Electronic Technology, Inc. Methods of growing nitride-based film using varying pulses
KR100734393B1 (ko) * 2005-11-28 2007-07-02 주식회사 에이이티 실리콘 박막의 원자층 증착 방법
JP4550778B2 (ja) * 2006-07-07 2010-09-22 株式会社東芝 磁気抵抗効果素子の製造方法
US7947981B2 (en) * 2007-01-30 2011-05-24 Semiconductor Energy Laboratory Co., Ltd. Display device
US7723771B2 (en) * 2007-03-30 2010-05-25 Qimonda Ag Zirconium oxide based capacitor and process to manufacture the same
US20090041952A1 (en) * 2007-08-10 2009-02-12 Asm Genitech Korea Ltd. Method of depositing silicon oxide films
JP2009206312A (ja) * 2008-02-28 2009-09-10 Mitsui Eng & Shipbuild Co Ltd 成膜方法および成膜装置
JP5190307B2 (ja) * 2008-06-29 2013-04-24 東京エレクトロン株式会社 成膜方法、成膜装置及び記憶媒体

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070065578A1 (en) * 2005-09-21 2007-03-22 Applied Materials, Inc. Treatment processes for a batch ALD reactor
TW200814205A (en) * 2006-07-12 2008-03-16 Applied Materials Inc A method for fabricating a gate dielectric layer utilized in a gate structure

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