CN103026471A - 环状薄膜的沉积方法 - Google Patents
环状薄膜的沉积方法 Download PDFInfo
- Publication number
- CN103026471A CN103026471A CN2011800362952A CN201180036295A CN103026471A CN 103026471 A CN103026471 A CN 103026471A CN 2011800362952 A CN2011800362952 A CN 2011800362952A CN 201180036295 A CN201180036295 A CN 201180036295A CN 103026471 A CN103026471 A CN 103026471A
- Authority
- CN
- China
- Prior art keywords
- silicon
- deposition process
- annular membrane
- film
- densification
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 8
- 238000000151 deposition Methods 0.000 title abstract description 18
- 125000004122 cyclic group Chemical group 0.000 title abstract 3
- 239000010409 thin film Substances 0.000 title abstract 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 60
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 60
- 239000010703 silicon Substances 0.000 claims abstract description 57
- 239000000758 substrate Substances 0.000 claims abstract description 40
- 238000000280 densification Methods 0.000 claims abstract description 35
- 238000006243 chemical reaction Methods 0.000 claims abstract description 34
- 239000012686 silicon precursor Substances 0.000 claims abstract description 20
- 230000008021 deposition Effects 0.000 claims abstract description 14
- 239000006227 byproduct Substances 0.000 claims abstract description 13
- 239000007789 gas Substances 0.000 claims description 66
- 238000004140 cleaning Methods 0.000 claims description 37
- 238000005137 deposition process Methods 0.000 claims description 26
- 239000012528 membrane Substances 0.000 claims description 24
- 239000007924 injection Substances 0.000 claims description 14
- 238000002347 injection Methods 0.000 claims description 14
- 239000001301 oxygen Substances 0.000 claims description 14
- 229910052760 oxygen Inorganic materials 0.000 claims description 14
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- 239000012212 insulator Substances 0.000 claims description 2
- 238000009413 insulation Methods 0.000 abstract description 5
- 238000010926 purge Methods 0.000 abstract description 5
- 239000010408 film Substances 0.000 abstract 4
- 239000012495 reaction gas Substances 0.000 abstract 2
- 239000004065 semiconductor Substances 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 9
- 125000004433 nitrogen atom Chemical group N* 0.000 description 4
- 125000004430 oxygen atom Chemical group O* 0.000 description 4
- 238000009616 inductively coupled plasma Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000008676 import Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 239000002243 precursor Substances 0.000 description 2
- FZHAPNGMFPVSLP-UHFFFAOYSA-N silanamine Chemical compound [SiH3]N FZHAPNGMFPVSLP-UHFFFAOYSA-N 0.000 description 2
- WEKIJJOSGXVNNE-UHFFFAOYSA-N CC[SiH2]NC Chemical compound CC[SiH2]NC WEKIJJOSGXVNNE-UHFFFAOYSA-N 0.000 description 1
- 239000005046 Chlorosilane Substances 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- KOPOQZFJUQMUML-UHFFFAOYSA-N chlorosilane Chemical compound Cl[SiH3] KOPOQZFJUQMUML-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000008358 core component Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 125000002147 dimethylamino group Chemical group [H]C([H])([H])N(*)C([H])([H])[H] 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- IFVRUKGTKXWWQF-UHFFFAOYSA-N methylaminosilicon Chemical compound CN[Si] IFVRUKGTKXWWQF-UHFFFAOYSA-N 0.000 description 1
- -1 oxygen anion Chemical class 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- GIRKRMUMWJFNRI-UHFFFAOYSA-N tris(dimethylamino)silicon Chemical compound CN(C)[Si](N(C)C)N(C)C GIRKRMUMWJFNRI-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B05—SPRAYING OR ATOMISING IN GENERAL; APPLYING FLUENT MATERIALS TO SURFACES, IN GENERAL
- B05D—PROCESSES FOR APPLYING FLUENT MATERIALS TO SURFACES, IN GENERAL
- B05D3/00—Pretreatment of surfaces to which liquids or other fluent materials are to be applied; After-treatment of applied coatings, e.g. intermediate treating of an applied coating preparatory to subsequent applications of liquids or other fluent materials
- B05D3/14—Pretreatment of surfaces to which liquids or other fluent materials are to be applied; After-treatment of applied coatings, e.g. intermediate treating of an applied coating preparatory to subsequent applications of liquids or other fluent materials by electrical means
- B05D3/141—Plasma treatment
- B05D3/145—After-treatment
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/34—Nitrides
- C23C16/345—Silicon nitride
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/40—Oxides
- C23C16/401—Oxides containing silicon
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
- C23C16/45523—Pulsed gas flow or change of composition over time
- C23C16/45525—Atomic layer deposition [ALD]
- C23C16/45527—Atomic layer deposition [ALD] characterized by the ALD cycle, e.g. different flows or temperatures during half-reactions, unusual pulsing sequence, use of precursor mixtures or auxiliary reactants or activations
- C23C16/45536—Use of plasma, radiation or electromagnetic fields
- C23C16/4554—Plasma being used non-continuously in between ALD reactions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
Abstract
本发明提供一种可以具有优异的膜性能和阶梯覆盖的环状薄膜的沉积方法。本发明一个实施例的环状薄膜的沉积方法包括:绝缘膜沉积步骤,其重复进行:通过将硅前体注入至装载了基底的腔室内部而将硅沉积在基底上的步骤;从腔室内部移除未反应的硅前体和反应副产物的第一清洗步骤;通过向腔室内部提供第一反应气体而将沉积的硅形成为含硅绝缘膜的反应步骤;和从腔室内部移除未反应的反应气体和反应副产物的第二清洗步骤;以及致密化步骤,其对通过向腔室内部提供等离子气氛来形成的含硅绝缘膜进行致密化。
Description
技术领域
本发明涉及一种环状薄膜的沉积方法,更具体而言,涉及一种形成含硅绝缘膜的环状薄膜的沉积方法。
背景技术
近年来,随着半导体工业的发展和用户的需求,电子设备更加高集成化和高性能化,因此作为电子设备的核心组件的半导体器件也需要高集成化和高性能化。然而,很难实现高集成化的半导体器件的精细结构。
例如,为实现精细结构需要更薄的绝缘膜,但是如果形成的绝缘膜为薄的厚度,则膜性能例如绝缘特性降低。同样,越来越难以形成具有薄的厚度的同时获得优异的阶梯覆盖(step coverage)的薄膜。
发明内容
本发明的目的在于解决上述现有问题,并且提供一种具有优异的膜性能和阶梯覆盖的绝缘膜的沉积方法。特别地,本发明提供一种具有优异的膜性能和阶梯覆盖的环状薄膜的沉积方法。
本发明的其他目的通过以下详细的说明和附图可以更清楚地理解。
根据本发明一个实施例的环状薄膜的沉积方法,该方法包括:绝缘膜沉积步骤,其重复进行:通过将硅前体注入至装载了基底的腔室内部而将硅沉积在所述基底上的步骤;从所述腔室内部移除未反应的硅前体和反应副产物的第一清洗步骤;通过向腔室内部提供第一反应气体而将沉积的硅形成为含硅绝缘膜的反应步骤;和从所述腔室内部移除未反应的第一反应气体和反应副产物的第二清洗步骤;以及致密化步骤,其通过向腔室内部提供等离子体气氛来对形成的含硅绝缘膜进行致密化。
所述第一反应气体可以是选自O2、O3、N2和NH3的一种或多种气体。
所述含硅绝缘膜可以为氧化硅膜或四氮化三硅膜。
在所述致密化步骤中,可以通过注入选自Ar、He、Kr和Xe的一种或多种点火气体(ignition gas)而形成等离子体气氛。
在所述反应步骤中,可以将在O2气氛中使用等离子体而形成的O*(氧自由基)或O2-(氧阴离子)作为第一反应气体。
在所述致密化步骤中,可以与所述点火气体一起进一步注入选自O2、O3、N2和NH3的一种或多种第二反应气体。
所述绝缘膜的沉积步骤可以在保持所述腔室内的压力为0.05Torr至10Torr的同时进行。
在所述致密化步骤中,可以将腔室内的压力保持为0.05Torr至10Torr。
在所述致密化步骤之前,可以将所述沉积步骤、所述第一清洗步骤、所述反应步骤和所述第二清洗步骤重复进行三次至十次。
所述绝缘膜的沉积步骤和所述致密化步骤可以重复进行。
发明效果
根据本发明一个实施例的环状薄膜的沉积方法可以形成具有优异的膜性能和阶梯覆盖的绝缘膜(例如氧化硅膜或四氮化三硅膜)。
因此,为了实现高集成化的半导体器件,可以形成具有薄厚度的绝缘膜,而且由于绝缘膜具有优异的阶梯覆盖,因此可以实现精细结构。另外,由于绝缘膜具有优异的膜性能,因此能满足高集成化的半导体器件所需的性能。
附图说明
图1是流程图,其表示本发明一个实施例的环状薄膜的沉积方法。
图2是剖视图,其示意性表示半导体制造装置,该半导体制造装置用于进行本发明一个实施例的环状薄膜的沉积方法。
图3是表示本发明一个实施例的环状薄膜的沉积方法的图解。
图4a至图4c是剖视图,其表示本发明一个实施例的沉积硅的步骤。
图5a至图5c是剖视图,其表示本发明一个实施例的形成含硅绝缘膜的步骤。
图6是剖视图,其表示本发明一个实施例的形成多个含硅绝缘膜的状况。
图7a至图7c是剖视图,其表示本发明一个实施例的对绝缘膜进行致密化的步骤。
图8是剖视图,其表示本发明另一个实施例的形成含硅绝缘膜的状况。
具体实施方式
在下文中,参考附图更详细地描述根据本发明的发明概念的实施例。然而,本发明的发明概念的实施例可以以各种方式进行改进,并且本发明的范围和实质不应理解为被下面描述的实施例所限制。提供根据本发明的发明概念的实施方案,以使本领域技术人员可以更完全地理解本发明。在附图中,相同的附图标记是指相同的元件。此外,在附图中各种元件和区域为示例性地表示。因此,本发明不限于附图中表示的相对大小或间隔。
图1是流程图,其表示本发明一个实施例的环状薄膜的沉积方法。
参考图1,将基底装载于半导体制造装置的腔室内部(S100)。在上述腔室内部装载的基底上沉积绝缘膜(S200),为了沉积绝缘膜,一起进行硅沉积步骤S210、第一清洗步骤S220、反应步骤S230和第二清洗步骤S240。
为了沉积硅,可以将硅(Si)前体注入至腔室内部,由此将硅沉积于基底上(S210)。在将硅沉积于基底上之后,进行移除未反应的硅前体和反应副产物的第一清洗步骤(S220)。
随后,通过使在基底上形成的硅与反应气体反应形成含硅绝缘膜的反应步骤在步骤S230中进行。例如,含硅绝缘膜可以为氧化硅膜或四氮化三硅膜。
为将硅形成为含硅绝缘膜,将第一反应气体注入至上述腔室内部。第一反应气体例如可以为选自O2、O3、N2和NH3的一种或多种气体。
当含硅绝缘膜为氧化硅膜时,上述第一反应气体可以为含氧原子的气体例如O2或O3的气体,或者可以为在O2气氛中使用等离子体而形成的O*(氧自由基)或O2-(氧阴离子)。当含硅绝缘膜为四氮化三硅膜时,上述第一反应气体可以为包含氮原子的气体例如N2或NH3的气体。
随后,可以进行从腔室内部移除反应副产物和反应气体或点火气体的第二清洗步骤(S240)。
可以将硅沉积步骤S210、第一清洗步骤S220、反应步骤S230和第二清洗步骤S240重复进行(S250)。例如,可以将硅沉积步骤S210、第一清洗步骤S220、反应步骤S230和第二清洗步骤S240重复三次至十次。
在包括硅沉积步骤S210、第一清洗步骤S220、反应步骤S230和第二清洗步骤S240的所述步骤S200中,可以将基底的温度和腔室内部的压力保持恒定。
为了对含硅绝缘膜进行致密化,可以在腔室内形成等离子体气氛。另外,与等离子体气氛一起,可以将第二反应气体另外注入至腔室内。例如,第二反应气体可以为选自O2、O3、N2和NH3的一种或多种气体。
为了获得具有所需厚度的含硅绝缘膜,可以根据需要将沉积绝缘膜的步骤S200和致密化步骤S300重复进行(S400)。
当形成具有所需厚度的含硅绝缘膜时,基底可以从腔室卸载(S900)。
图2为剖视图,其示意性表示半导体制造装置,该半导体制造装置用于进行本发明一个实施例的环状薄膜的沉积方法。
如图2所示,在半导体制造装置10的腔室11内形成有用于导入反应气体的导入部12。经由导入部12导入的反应气体可以通过喷头13喷射至腔室11内部。
作为沉积对象的基底100置于卡盘14上,其通过卡盘支座16支撑。如果需要,卡盘14可以向基底100施加热量,使得基底100具有规定温度。通过半导体制造装置10进行沉积,此后,通过排出部17来排出。
此外,为了形成等离子体气氛,半导体制造装置10可以包括等离子体产生部18。
图3是表示本发明一个实施例的环状薄膜的沉积方法的图解。
如图3所示,重复进行硅(Si)前体的注入和清洗(purge)以及第一反应气体的注入和清洗。重复进行硅前体的注入后的清洗和第一反应气体的注入后的清洗,然后形成等离子体气氛。在已形成等离子体气氛的状态下,可根据需要注入第二反应气体。
从重复进行硅前体的注入和清洗以及第一反应气体的注入和清洗到形成等离子体气氛的步骤为止,作为一个周期进行。即,在通过重复进行硅前体的注入和清洗以及反应气体的注入和清洗来形成含硅绝缘膜之后,通过形成等离子体气氛来对含硅绝缘膜进行致密化。
此外,通过重复上述所有过程,可以获得具有所需厚度的含硅绝缘膜。
因此,环状薄膜的沉积方法可以通过重复进行硅前体的注入和清洗以及第一反应气体的注入和清洗来进行,并且可以重复进行含硅绝缘膜的形成和致密化。
参考图4a至图8并基于所述的内容,对本发明一个实施例的环状薄膜的沉积方法逐步具体地进行描述。在图4a至图8的以下说明中,可以根据需要使用图1至图3的附图标记。
图4a至图4c是剖视图,其表示根据本发明一个实施例的沉积硅的步骤。图4a是剖视图,其表示本发明一个实施例的注入硅前体的步骤。
如图4a所示,硅前体50被注入至装载了基底100的腔室11内。
例如,基底100可以包括半导体基底例如硅或化合物半导体晶片。另外,基底100可以包括不同于半导体的基底材料等,该基底材料例如玻璃、金属、陶瓷和石英。
例如,硅前体50可以是:氨基硅烷例如双乙基甲基氨基硅烷(BEMAS,bisethylmethylaminosilane)、双二甲基氨基硅烷(BDMAS,bisdimethylaminosilane)、BEDAS、四乙基甲基氨基硅烷(TEMAS,tetrakisethymethylaminosilane)、四二甲基氨基硅烷(TDMAS,tetrakisidimethylaminosilane)和TEDAS或氯基硅烷例如六氯乙硅烷(HCD,hexachlorinedisilan)。
为了使基底100与硅前体50反应,基底100可以保持在50℃至600℃。此外,装载了基底100的腔室11内部的压力可以保持在0.05Torr至10Torr。
图4b是剖视图,其表示本发明一个实施例的将硅沉积在基底上的状况。如图4b所示,通过硅前体50的一部分与基底100反应,可以在基底100上沉积硅原子,并且因此可以形成硅层112。硅层112可以由至少一个硅原子层形成。
硅前体50可以在与基底100反应之后,形成反应副产品52。此外,硅前体50的其他部分可以以未与基底100反应的未反应状态残留。
图4c是剖视图,其表示进行本发明一个实施例的第一清洗步骤的状况。如图4c所示,在基底100上形成硅层112,然后进行从腔室11移除以未反应状态残留的硅前体50和反应副产物52的清洗。该清洗(purge)步骤可以称为第一清洗步骤,所述步骤从腔室11内部移除残留的硅前体50和反应的副产物52。
在第一清洗步骤中,基底100可以保持在50℃至600℃的温度。此外,装载了基底100的腔室11内部的压力可以保持在0.05Torr至10Torr。即,在沉积硅层112和第一清洗步骤中,可以将基底100的温度和腔室11内部的压力保持恒定。
图5a至图5c为剖视图,其表示本发明一个实施例的形成含硅绝缘膜的步骤。图5a是剖视图,其表示本发明一个实施例的注入反应气体的步骤。
如图5a所示,将第一反应气体60注入至装载了基底100的腔室11内。例如第一反应气体60可以为选自O2、O3、N2和NH3的一种或多种气体。或者,例如第一反应气体60可以为在O2气氛中使用等离子体而形成的O*(氧自由基)或O2-(氧阴离子)。
为了使基底100可以与第一反应气体60反应,基底100可以保持在50℃至600℃的温度。此外,装载了基底100的腔室11内部的压力可以保持在0.05Torr至10Torr。
图5b是剖视图,其表示本发明一个实施例的在基底上沉积含硅绝缘膜的状况。如图5b所示,通过第一反应气体60的一部分与硅层112反应,可以在基底100上形成含硅绝缘膜112a。
第一反应气体60可以在与硅层112反应之后形成反应副产物62。此外,第一反应气体60的其他部分可以以未与硅层112反应的状态残留。
例如,当将含氧原子的气体例如O2或O3或在O2气体中使用等离子体形成的O*(氧自由基)或O2-(氧阴离子)用作第一反应气体60时,硅层112可以与包含于第一反应气体60中的氧原子反应而形成为氧化硅层。或者,当将含氮原子的气体例如N2或NH3用作第一反应气体60时,硅层112可以与包含于第一反应气体60中的氮原子反应而形成为四氮化三硅层。
图5c是剖视图,其表示本发明一个实施例的进行第二清洗步骤的状况。如图5c所示,在基底100上形成含硅绝缘膜112a,然后进行清洗(purge)步骤,该清洗步骤移除以未反应状态残留的第一反应气体60和反应副产物62。该清洗步骤可以称为第二清洗步骤,该步骤从腔室11中移除未反应状态的第一反应气体60和反应副产物62。
在进行第二清洗步骤期间,基底100可以保持在50℃至600℃的温度。此外,装载了基底100的腔室11内部的压力可以保持在0.05Torr至10Torr。
图6是剖视图,其表示本发明一个实施例的形成多个含硅绝缘膜的状况。如图6所示,通过重复进行图4a至图5c的步骤,形成由多个含硅绝缘膜122a、122b、122c而形成的绝缘膜122。
绝缘膜122可以具有数个或数十个的厚度。沉积各个含硅绝缘膜122a、122b或122c的过程可以重复进行三次至十次,使得绝缘膜122包括三个至十个的含硅绝缘膜122a、122b、122c。
以此方式,如果将绝缘膜122形成为多个含硅绝缘膜122a、122b、122c,则绝缘膜122可以具有优异的膜性能和阶梯覆盖(step coverage)。.
图7a和图7b是剖视图,其表示本发明一个实施例的对绝缘膜进行致密化的步骤。图7a是剖视图,其表示向本发明一个实施例的绝缘膜提供等离子体气氛的状况。
如图7a所示,将等离子体施加于形成有绝缘膜122的基底100上。即,将装载了基底100的腔室11内部形成为等离子体气氛。为了形成等离子体气氛,可以使用电感耦合等离子体(ICP,Inductively CoupledPlasma)、电容耦合等离子体(CCP,Capacitively Coupled Plasma)或微波(MW,Microwave)等离子体。在这个时候,为了形成等离子气氛,可以施加100W至3kW的功率。
为了形成等离子体气氛,例如可以注入选自Ar、He、Kr和Xe的一种或多种点火气体。在该情况下,点火气体可以以100sccm至3000sccm的流速注入。
为了在等离子体气氛中进一步对绝缘膜122进行致密化,可以另行注入第二反应气体64。例如第二反应气体64可以为选自O2、O3、N2和NH3的一种或多种气体或在O2气氛中使用等离子体形成的O*(氧自由基)或O2-(氧阴离子)。
例如,当绝缘膜122为氧化硅膜时,第二反应气体64可以采用:含氧原子的气体例如O2或O3;在O2气氛中使用等离子体形成的O*(氧自由基)或O2-(氧阴离子);或H2。
例如,当绝缘膜122为四氮化三硅膜时,第二反应气体64可以使用:含氮原子的气体例如N2或NH3;或H2。
图7b为剖视图,其表示本发明一个实施例的形成致密化的绝缘膜122D的状况。如图7a和7b所示,绝缘膜122可以在等离子气氛中致密化,由此可以形成被致密化的绝缘膜122D。为了形成被致密化的绝缘膜122D,装载了基底100的腔室11的压力可以保持在0.05Torr至10Torr。
此外,通过在等离子体气氛中处理绝缘膜122而获得的被致密化的绝缘膜可以具有优良的绝缘特性等膜性能。特别地,即使形成的被致密化的绝缘膜122D具有薄的厚度,被致密化的绝缘膜122D也可以具有优良的膜性能。
图8是剖视图,其表示本发明另一个实施例的形成含硅绝缘膜的状况。如图8所示,通过重复进行图4a至图7b所述的步骤,可以形成包括薄的多个被致密化的绝缘膜122D、124D的绝缘膜120。
如果图7a所示的绝缘膜122相对较厚,则等离子体或第二反应气体64对绝缘膜122的下部的影响相对小。因此,为了进一步改善绝缘膜120的膜性能,可以形成包括薄的被致密化的绝缘膜122D、124D的绝缘膜120。
此外,绝缘膜120表示为包括两个被致密化的绝缘膜122D、124D,但绝缘膜120可以包括三个或更多被致密化的绝缘膜。即,根据绝缘膜120的所需厚度,可以确定绝缘膜120包括的被致密化的绝缘膜的数量。换句话说,根据绝缘膜120的所需厚度,可以确定重复图4a至图7b所述的步骤的次数。
通过优选实施例详细地说明了本发明,但本发明还可以以其他实施例实施。因此,下述权利要求的技术宗旨和范围不限于优选的实施例。
产业上的可利用性
本发明可适用于如沉积过程的各种各样的半导体制造工艺中。
Claims (10)
1.一种环状薄膜的沉积方法,该方法包括:
绝缘膜沉积步骤,其重复进行:通过将硅前体注入至装载了基底的腔室内部而将硅沉积在所述基底上的步骤;从所述腔室内部移除未反应的硅前体和反应副产物的第一清洗步骤;通过向腔室内部提供第一反应气体而将沉积的硅形成为含硅绝缘膜的反应步骤;和从所述腔室内部移除未反应的第一反应气体和反应副产物的第二清洗步骤;以及
致密化步骤,其对通过向腔室内部提供等离子体气氛来形成的含硅绝缘膜进行致密化。
2.权利要求1所述的环状薄膜的沉积方法,其特征在于,
所述第一反应气体为选自O2、O3、N2和NH3的一种或多种气体。
3.权利要求2所述的环状薄膜的沉积方法,其特征在于,所述含硅绝缘膜为氧化硅膜或四氮化三硅膜。
4.权利要求2所述的环状薄膜的沉积方法,其特征在于,
在所述致密化步骤中,通过注入选自Ar、He、Kr和Xe的一种或多种点火气体而形成等离子体气氛。
5.权利要求1所述的环状薄膜的沉积方法,其特征在于,
在所述反应步骤中,将在O2气氛中使用等离子体而形成的O*(氧自由基)或O2-(氧阴离子)作为第一反应气体。
6.权利要求4所述的环状薄膜的沉积方法,其特征在于,
在所述致密化步骤中,与所述点火气体一起,还注入选自O2、O3、N2和NH3的一种或多种第二反应气体。
7.权利要求1所述的环状薄膜的沉积方法,其特征在于,
在所述绝缘膜的沉积步骤中,将所述腔室内部的压力保持为0.05Torr至10Torr。
8.权利要求1所述的环状薄膜的沉积方法,其特征在于,
在致密化步骤中,所述腔室内部的压力保持为0.05Torr至10Torr。
9.权利要求1所述的环状薄膜的沉积方法,其特征在于,
在所述致密化步骤之前,将沉积步骤、第一清洗步骤、反应步骤和第二清洗步骤重复进行三次至十次。
10.权利要求1所述的环状薄膜的沉积方法,其特征在于,
将所述绝缘膜的沉积步骤和所述致密化步骤重复进行。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020100074608A KR101147727B1 (ko) | 2010-08-02 | 2010-08-02 | 사이클릭 박막 증착 방법 |
KR10-2010-0074608 | 2010-08-02 | ||
PCT/KR2011/005650 WO2012018211A2 (ko) | 2010-08-02 | 2011-08-01 | 사이클릭 박막 증착 방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN103026471A true CN103026471A (zh) | 2013-04-03 |
CN103026471B CN103026471B (zh) | 2016-01-13 |
Family
ID=45559917
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201180036295.2A Active CN103026471B (zh) | 2010-08-02 | 2011-08-01 | 环状薄膜的沉积方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US20130101752A1 (zh) |
JP (1) | JP2013542581A (zh) |
KR (1) | KR101147727B1 (zh) |
CN (1) | CN103026471B (zh) |
TW (1) | TWI474399B (zh) |
WO (1) | WO2012018211A2 (zh) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104752165A (zh) * | 2013-12-27 | 2015-07-01 | 株式会社Eugene科技 | 用于形成薄膜的循环沉积法、半导体制造方法和半导体器件 |
CN105612604A (zh) * | 2013-11-08 | 2016-05-25 | 株式会社Eugene科技 | 薄膜循环蒸镀方法、半导体制造方法及半导体元件 |
CN106489190A (zh) * | 2014-07-15 | 2017-03-08 | 株式会社Eugene科技 | 在具有高纵横比的凹陷部上蒸镀绝缘膜的方法 |
CN107924820A (zh) * | 2014-12-08 | 2018-04-17 | 周星工程股份有限公司 | 基板处理方法 |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW201606116A (zh) * | 2014-08-08 | 2016-02-16 | 尤金科技有限公司 | 具低蝕刻率之氧化薄膜之沉積方法及半導體裝置 |
KR101576639B1 (ko) * | 2014-09-18 | 2015-12-10 | 주식회사 유진테크 | 절연막 증착 방법 |
JP2017139297A (ja) * | 2016-02-02 | 2017-08-10 | 東京エレクトロン株式会社 | 成膜方法及び成膜装置 |
KR102125474B1 (ko) * | 2016-12-05 | 2020-06-24 | 주식회사 원익아이피에스 | 박막 증착 방법 |
WO2019245702A1 (en) | 2018-06-19 | 2019-12-26 | Applied Materials, Inc. | Pulsed plasma deposition etch step coverage improvement |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20020081902A (ko) * | 2001-04-20 | 2002-10-30 | 아남반도체 주식회사 | 산소 라디칼을 이용한 실리콘 산화막의 제조 방법 |
KR100734393B1 (ko) * | 2005-11-28 | 2007-07-02 | 주식회사 에이이티 | 실리콘 박막의 원자층 증착 방법 |
US20080038936A1 (en) * | 2002-07-19 | 2008-02-14 | Asm America, Inc. | Method to form ultra high quality silicon-containing compound layers |
KR20080071515A (ko) * | 2007-01-30 | 2008-08-04 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 표시 장치 |
KR20090016403A (ko) * | 2007-08-10 | 2009-02-13 | 에이에스엠지니텍코리아 주식회사 | 실리콘 산화막 증착 방법 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6140246A (en) * | 1997-12-18 | 2000-10-31 | Advanced Micro Devices, Inc. | In-situ P doped amorphous silicon by NH3 to form oxidation resistant and finer grain floating gates |
JP4257576B2 (ja) * | 2003-03-25 | 2009-04-22 | ローム株式会社 | 成膜装置 |
DE10319540A1 (de) * | 2003-04-30 | 2004-11-25 | Infineon Technologies Ag | Verfahren zur ALD-Beschichtung von Substraten sowie eine zur Durchführung des Verfahrens geeignete Vorrichtung |
US7192849B2 (en) * | 2003-05-07 | 2007-03-20 | Sensor Electronic Technology, Inc. | Methods of growing nitride-based film using varying pulses |
US20070065578A1 (en) * | 2005-09-21 | 2007-03-22 | Applied Materials, Inc. | Treatment processes for a batch ALD reactor |
JP4550778B2 (ja) * | 2006-07-07 | 2010-09-22 | 株式会社東芝 | 磁気抵抗効果素子の製造方法 |
US20080014759A1 (en) * | 2006-07-12 | 2008-01-17 | Applied Materials, Inc. | Method for fabricating a gate dielectric layer utilized in a gate structure |
US7723771B2 (en) * | 2007-03-30 | 2010-05-25 | Qimonda Ag | Zirconium oxide based capacitor and process to manufacture the same |
JP2009206312A (ja) * | 2008-02-28 | 2009-09-10 | Mitsui Eng & Shipbuild Co Ltd | 成膜方法および成膜装置 |
JP5190307B2 (ja) * | 2008-06-29 | 2013-04-24 | 東京エレクトロン株式会社 | 成膜方法、成膜装置及び記憶媒体 |
-
2010
- 2010-08-02 KR KR1020100074608A patent/KR101147727B1/ko active IP Right Grant
-
2011
- 2011-07-29 TW TW100127081A patent/TWI474399B/zh active
- 2011-08-01 CN CN201180036295.2A patent/CN103026471B/zh active Active
- 2011-08-01 US US13/808,111 patent/US20130101752A1/en not_active Abandoned
- 2011-08-01 WO PCT/KR2011/005650 patent/WO2012018211A2/ko active Application Filing
- 2011-08-01 JP JP2013521723A patent/JP2013542581A/ja active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20020081902A (ko) * | 2001-04-20 | 2002-10-30 | 아남반도체 주식회사 | 산소 라디칼을 이용한 실리콘 산화막의 제조 방법 |
US20080038936A1 (en) * | 2002-07-19 | 2008-02-14 | Asm America, Inc. | Method to form ultra high quality silicon-containing compound layers |
KR100734393B1 (ko) * | 2005-11-28 | 2007-07-02 | 주식회사 에이이티 | 실리콘 박막의 원자층 증착 방법 |
KR20080071515A (ko) * | 2007-01-30 | 2008-08-04 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 표시 장치 |
KR20090016403A (ko) * | 2007-08-10 | 2009-02-13 | 에이에스엠지니텍코리아 주식회사 | 실리콘 산화막 증착 방법 |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105612604A (zh) * | 2013-11-08 | 2016-05-25 | 株式会社Eugene科技 | 薄膜循环蒸镀方法、半导体制造方法及半导体元件 |
CN105612604B (zh) * | 2013-11-08 | 2019-07-12 | 株式会社Eugene科技 | 薄膜循环蒸镀方法、半导体制造方法及半导体元件 |
CN104752165A (zh) * | 2013-12-27 | 2015-07-01 | 株式会社Eugene科技 | 用于形成薄膜的循环沉积法、半导体制造方法和半导体器件 |
CN106489190A (zh) * | 2014-07-15 | 2017-03-08 | 株式会社Eugene科技 | 在具有高纵横比的凹陷部上蒸镀绝缘膜的方法 |
CN106489190B (zh) * | 2014-07-15 | 2019-06-25 | 株式会社Eugene科技 | 在具有高纵横比的凹陷部上蒸镀绝缘膜的方法 |
CN107924820A (zh) * | 2014-12-08 | 2018-04-17 | 周星工程股份有限公司 | 基板处理方法 |
CN107924820B (zh) * | 2014-12-08 | 2022-05-27 | 周星工程股份有限公司 | 基板处理方法 |
Also Published As
Publication number | Publication date |
---|---|
US20130101752A1 (en) | 2013-04-25 |
TW201220397A (en) | 2012-05-16 |
CN103026471B (zh) | 2016-01-13 |
KR101147727B1 (ko) | 2012-05-25 |
WO2012018211A2 (ko) | 2012-02-09 |
KR20120012582A (ko) | 2012-02-10 |
WO2012018211A3 (ko) | 2012-05-03 |
JP2013542581A (ja) | 2013-11-21 |
TWI474399B (zh) | 2015-02-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN103026472B (zh) | 环状薄膜的沉积方法 | |
CN103026471B (zh) | 环状薄膜的沉积方法 | |
US8076242B2 (en) | Methods of forming an amorphous silicon thin film | |
KR20210095050A (ko) | 박막 형성 방법 및 박막 표면 개질 방법 | |
CN113493906A (zh) | 形成薄膜的方法 | |
KR20180058232A (ko) | SiO 및 SiN을 포함하는 유동성 막들을 증착시키는 방법들 | |
KR101576637B1 (ko) | 고종횡비를 가지는 오목부 상에 절연막을 증착하는 방법 | |
KR101551199B1 (ko) | 사이클릭 박막 증착 방법 및 반도체 제조 방법, 그리고 반도체 소자 | |
KR20230006032A (ko) | 규소-함유 막의 증착을 위한 조성물 및 이를 사용하는 방법 | |
JP2005534179A (ja) | アミノシランとオゾンを用いる低温誘電体蒸着法 | |
JP2004047956A (ja) | 多層ナノラミネート構造を有する半導体装置の絶縁膜及びその形成方法 | |
WO2015073188A1 (en) | Method of depositing a low-temperature, no-damage hdp sic-like film with high wet etch resistance | |
KR20160062370A (ko) | 반도체 소자의 제조방법 | |
KR101576639B1 (ko) | 절연막 증착 방법 | |
KR101008490B1 (ko) | 저온 화학기상증착에 의한 산화막 증착 방법 | |
US20230142684A1 (en) | Single Precursor Low-K Film Deposition and UV Cure for Advanced Technology Node | |
KR20050018641A (ko) | 아미노실란 및 오존을 이용한 저온 유전체 증착 | |
US20240071749A1 (en) | Substrate processing method | |
US20240063053A1 (en) | Substrate processing method | |
CN117594419A (zh) | 衬底处理方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant |