CN102782838B - 嵌入式芯片封装体 - Google Patents
嵌入式芯片封装体 Download PDFInfo
- Publication number
- CN102782838B CN102782838B CN201080060570.XA CN201080060570A CN102782838B CN 102782838 B CN102782838 B CN 102782838B CN 201080060570 A CN201080060570 A CN 201080060570A CN 102782838 B CN102782838 B CN 102782838B
- Authority
- CN
- China
- Prior art keywords
- substrate
- semiconductor die
- rank
- attached
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49894—Materials of the insulating layers or coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/07—Polyamine or polyimide
- H01L2924/07025—Polyimide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/1579—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16151—Cap comprising an aperture, e.g. for pressure control, encapsulation
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Geometry (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
Claims (21)
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US26419109P | 2009-11-24 | 2009-11-24 | |
US61/264,191 | 2009-11-24 | ||
US12/942,918 US9070679B2 (en) | 2009-11-24 | 2010-11-09 | Semiconductor package with a semiconductor die embedded within substrates |
US12/942,918 | 2010-11-09 | ||
PCT/US2010/056251 WO2011066106A1 (en) | 2009-11-24 | 2010-11-10 | Embedded chip packages |
Publications (2)
Publication Number | Publication Date |
---|---|
CN102782838A CN102782838A (zh) | 2012-11-14 |
CN102782838B true CN102782838B (zh) | 2016-01-20 |
Family
ID=44061489
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201080060570.XA Expired - Fee Related CN102782838B (zh) | 2009-11-24 | 2010-11-10 | 嵌入式芯片封装体 |
Country Status (5)
Country | Link |
---|---|
US (2) | US9070679B2 (zh) |
KR (1) | KR101801307B1 (zh) |
CN (1) | CN102782838B (zh) |
TW (1) | TWI458028B (zh) |
WO (1) | WO2011066106A1 (zh) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8513119B2 (en) | 2008-12-10 | 2013-08-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming bump structure having tapered sidewalls for stacked dies |
US20100171197A1 (en) | 2009-01-05 | 2010-07-08 | Hung-Pin Chang | Isolation Structure for Stacked Dies |
US8900994B2 (en) | 2011-06-09 | 2014-12-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for producing a protective structure |
KR101394033B1 (ko) | 2012-10-10 | 2014-05-09 | 현대자동차 주식회사 | 차량용 자동변속기의 유성기어트레인 |
US9564408B2 (en) * | 2014-03-28 | 2017-02-07 | Intel Corporation | Space transformer |
JP6350759B2 (ja) * | 2015-08-18 | 2018-07-04 | 三菱電機株式会社 | 半導体装置 |
KR101688081B1 (ko) | 2016-02-05 | 2016-12-20 | 앰코 테크놀로지 코리아 주식회사 | Ets 구조 |
US10797007B2 (en) * | 2017-11-28 | 2020-10-06 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure and manufacturing method thereof |
CN110729255A (zh) * | 2019-08-08 | 2020-01-24 | 厦门云天半导体科技有限公司 | 一种键合墙体扇出器件的三维封装结构和方法 |
CN212086589U (zh) * | 2019-12-31 | 2020-12-04 | 华为技术有限公司 | 一种电子设备 |
CN113276359B (zh) * | 2020-02-19 | 2022-11-08 | 长鑫存储技术有限公司 | 注塑模具及注塑方法 |
KR20220072169A (ko) | 2020-11-25 | 2022-06-02 | 삼성전자주식회사 | 반도체 패키지 및 그 제조 방법 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5357672A (en) * | 1993-08-13 | 1994-10-25 | Lsi Logic Corporation | Method and system for fabricating IC packages from laminated boards and heat spreader |
US5736780A (en) * | 1995-11-07 | 1998-04-07 | Shinko Electric Industries Co., Ltd. | Semiconductor device having circuit pattern along outer periphery of sealing resin and related processes |
CN1519931A (zh) * | 2003-02-07 | 2004-08-11 | ������������ʽ���� | 半导体器件、电子设备及它们的制造方法和电子仪器 |
CN1592968A (zh) * | 2002-02-19 | 2005-03-09 | 松下电器产业株式会社 | 模块化器件 |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2748592B2 (ja) * | 1989-09-18 | 1998-05-06 | セイコーエプソン株式会社 | 半導体装置の製造方法および半導体封止用成形金型 |
US5324888A (en) * | 1992-10-13 | 1994-06-28 | Olin Corporation | Metal electronic package with reduced seal width |
US5808874A (en) | 1996-05-02 | 1998-09-15 | Tessera, Inc. | Microelectronic connections with liquid conductive elements |
US6678167B1 (en) * | 2000-02-04 | 2004-01-13 | Agere Systems Inc | High performance multi-chip IC package |
US7009297B1 (en) * | 2000-10-13 | 2006-03-07 | Bridge Semiconductor Corporation | Semiconductor chip assembly with embedded metal particle |
JP2002270638A (ja) * | 2001-03-06 | 2002-09-20 | Nec Corp | 半導体装置および樹脂封止方法および樹脂封止装置 |
JP4039298B2 (ja) * | 2003-04-08 | 2008-01-30 | 株式会社デンソー | 樹脂封止型半導体装置およびその製造方法ならびに成形型 |
US6873040B2 (en) | 2003-07-08 | 2005-03-29 | Texas Instruments Incorporated | Semiconductor packages for enhanced number of terminals, speed and power performance |
KR100817073B1 (ko) * | 2006-11-03 | 2008-03-26 | 삼성전자주식회사 | 휨방지용 보강부재가 기판에 연결된 반도체 칩 스택 패키지 |
US8174119B2 (en) * | 2006-11-10 | 2012-05-08 | Stats Chippac, Ltd. | Semiconductor package with embedded die |
KR20090032845A (ko) * | 2007-09-28 | 2009-04-01 | 삼성전자주식회사 | 반도체 패키지 및 그의 제조방법 |
US20090108431A1 (en) * | 2007-10-29 | 2009-04-30 | Analog Devices, Inc. | Inverted package-on-package (POP) assemblies and packaging methods for integrated circuits |
US20090108433A1 (en) | 2007-10-30 | 2009-04-30 | Kenji Masumoto | Multilayer semiconductor device package assembly and method |
KR20090061996A (ko) * | 2007-12-12 | 2009-06-17 | 삼성전자주식회사 | 칩 뒷면 보호 필름, 그 제조 방법 및 이를 이용한 반도체패키지의 제조 방법 |
US8618669B2 (en) | 2008-01-09 | 2013-12-31 | Ibiden Co., Ltd. | Combination substrate |
TWI355731B (en) * | 2008-02-26 | 2012-01-01 | Powertech Technology Inc | Chips-between-substrates semiconductor package and |
TW200947666A (en) * | 2008-05-02 | 2009-11-16 | Hon Hai Prec Ind Co Ltd | Imaging sensor package structure and imaging device using same |
KR101486420B1 (ko) * | 2008-07-25 | 2015-01-26 | 삼성전자주식회사 | 칩 패키지, 이를 이용한 적층형 패키지 및 그 제조 방법 |
US8021930B2 (en) * | 2009-08-12 | 2011-09-20 | Stats Chippac, Ltd. | Semiconductor device and method of forming dam material around periphery of die to reduce warpage |
-
2010
- 2010-11-09 US US12/942,918 patent/US9070679B2/en not_active Expired - Fee Related
- 2010-11-10 WO PCT/US2010/056251 patent/WO2011066106A1/en active Application Filing
- 2010-11-10 CN CN201080060570.XA patent/CN102782838B/zh not_active Expired - Fee Related
- 2010-11-10 KR KR1020127015803A patent/KR101801307B1/ko active IP Right Grant
- 2010-11-23 TW TW099140338A patent/TWI458028B/zh not_active IP Right Cessation
-
2015
- 2015-06-25 US US14/750,141 patent/US20150311147A1/en not_active Abandoned
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5357672A (en) * | 1993-08-13 | 1994-10-25 | Lsi Logic Corporation | Method and system for fabricating IC packages from laminated boards and heat spreader |
US5736780A (en) * | 1995-11-07 | 1998-04-07 | Shinko Electric Industries Co., Ltd. | Semiconductor device having circuit pattern along outer periphery of sealing resin and related processes |
CN1592968A (zh) * | 2002-02-19 | 2005-03-09 | 松下电器产业株式会社 | 模块化器件 |
CN1519931A (zh) * | 2003-02-07 | 2004-08-11 | ������������ʽ���� | 半导体器件、电子设备及它们的制造方法和电子仪器 |
Also Published As
Publication number | Publication date |
---|---|
KR20120112464A (ko) | 2012-10-11 |
TW201131667A (en) | 2011-09-16 |
US20150311147A1 (en) | 2015-10-29 |
CN102782838A (zh) | 2012-11-14 |
WO2011066106A1 (en) | 2011-06-03 |
TWI458028B (zh) | 2014-10-21 |
KR101801307B1 (ko) | 2017-11-24 |
US9070679B2 (en) | 2015-06-30 |
US20110121444A1 (en) | 2011-05-26 |
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C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
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