CN102651363B - 在导电层之间用于提高可靠性的通孔 - Google Patents

在导电层之间用于提高可靠性的通孔 Download PDF

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Publication number
CN102651363B
CN102651363B CN201210048097.4A CN201210048097A CN102651363B CN 102651363 B CN102651363 B CN 102651363B CN 201210048097 A CN201210048097 A CN 201210048097A CN 102651363 B CN102651363 B CN 102651363B
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China
Prior art keywords
conductive
layer
hole
semiconductor device
silk thread
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CN201210048097.4A
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English (en)
Chinese (zh)
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CN102651363A (zh
Inventor
T·S·黄
P·莎玛
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NXP USA Inc
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Freescale Semiconductor Inc
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Publication of CN102651363A publication Critical patent/CN102651363A/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs

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  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)
CN201210048097.4A 2011-02-28 2012-02-28 在导电层之间用于提高可靠性的通孔 Active CN102651363B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/036,461 2011-02-28
US13/036,461 US8847393B2 (en) 2011-02-28 2011-02-28 Vias between conductive layers to improve reliability

Publications (2)

Publication Number Publication Date
CN102651363A CN102651363A (zh) 2012-08-29
CN102651363B true CN102651363B (zh) 2017-05-03

Family

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CN201210048097.4A Active CN102651363B (zh) 2011-02-28 2012-02-28 在导电层之间用于提高可靠性的通孔

Country Status (4)

Country Link
US (1) US8847393B2 (https=)
EP (1) EP2492960A3 (https=)
JP (1) JP2012182455A (https=)
CN (1) CN102651363B (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9041209B2 (en) 2011-11-18 2015-05-26 Freescale Semiconductor, Inc. Method and apparatus to improve reliability of vias
US10861808B2 (en) 2018-11-21 2020-12-08 Taiwan Semiconductor Manufacturing Company, Ltd. Bonding structure of dies with dangling bonds
DE102019109844B4 (de) 2018-11-21 2025-03-20 Taiwan Semiconductor Manufacturing Co., Ltd. Bondstruktur von dies mit hängenden bonds und verfahren zu deren herstellung
US11036911B2 (en) * 2019-09-26 2021-06-15 Taiwan Semiconductor Manufacturing Co., Ltd. Charging prevention method and structure

Citations (1)

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Publication number Priority date Publication date Assignee Title
CN101322238A (zh) * 2005-11-30 2008-12-10 先进微装置公司 通过设置假通孔而增加金属化层的附着力的技术

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US5849637A (en) * 1996-06-10 1998-12-15 Wang; Chin-Kun Integration of spin-on gap filling dielectric with W-plug without outgassing
US6734472B2 (en) * 2002-04-25 2004-05-11 Synplicity, Inc. Power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device
US7943436B2 (en) * 2002-07-29 2011-05-17 Synopsys, Inc. Integrated circuit devices and methods and apparatuses for designing integrated circuit devices
JP2005064226A (ja) 2003-08-12 2005-03-10 Renesas Technology Corp 配線構造
US6864171B1 (en) * 2003-10-09 2005-03-08 Infineon Technologies Ag Via density rules
JP4047324B2 (ja) 2003-12-03 2008-02-13 松下電器産業株式会社 半導体装置及びその製造方法
JP2005268748A (ja) * 2004-02-18 2005-09-29 Nec Electronics Corp 半導体装置及びその製造方法
US7157365B2 (en) 2004-05-10 2007-01-02 Agere Systems Inc. Semiconductor device having a dummy conductive via and a method of manufacture therefor
US7272814B2 (en) * 2004-09-20 2007-09-18 Lsi Corporation Reconfiguring a RAM to a ROM using layers of metallization
JP2007012773A (ja) * 2005-06-29 2007-01-18 Nec Electronics Corp 多層配線を有する半導体装置
JP4671814B2 (ja) * 2005-09-02 2011-04-20 パナソニック株式会社 半導体装置
US7301236B2 (en) 2005-10-18 2007-11-27 International Business Machines Corporation Increasing electromigration lifetime and current density in IC using vertically upwardly extending dummy via
JP2007129030A (ja) * 2005-11-02 2007-05-24 Seiko Epson Corp 半導体装置及びその製造方法
JP2007305713A (ja) * 2006-05-10 2007-11-22 Matsushita Electric Ind Co Ltd 半導体装置及び配線補助パターン生成方法
JP5050413B2 (ja) 2006-06-09 2012-10-17 富士通株式会社 設計支援プログラム、該プログラムを記録した記録媒体、設計支援方法、および設計支援装置
US7566652B2 (en) 2006-07-24 2009-07-28 Texas Instruments Incorporated Electrically inactive via for electromigration reliability improvement
JP4303280B2 (ja) * 2006-12-06 2009-07-29 Ｎｅｃエレクトロニクス株式会社 半導体集積回路のレイアウト方法、レイアウトプログラム
JP2010003712A (ja) * 2007-08-09 2010-01-07 Renesas Technology Corp 半導体装置、半導体装置の配置配線方法、及びデータ処理システム
JP2009060034A (ja) 2007-09-03 2009-03-19 Rohm Co Ltd 半導体装置
US20090085120A1 (en) * 2007-09-28 2009-04-02 Texas Instruments Incorporated Method for Reduction of Resist Poisoning in Via-First Trench-Last Dual Damascene Process
JP4642908B2 (ja) * 2008-03-11 2011-03-02 パナソニック株式会社 半導体集積回路装置
US8307321B2 (en) * 2009-03-20 2012-11-06 Taiwan Semiconductor Manufacturing Company, Ltd. Method for dummy metal and dummy via insertion
KR20120138875A (ko) * 2011-06-16 2012-12-27 삼성전자주식회사 배선 구조물 및 이의 제조 방법

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101322238A (zh) * 2005-11-30 2008-12-10 先进微装置公司 通过设置假通孔而增加金属化层的附着力的技术

Also Published As

Publication number Publication date
US20120217646A1 (en) 2012-08-30
EP2492960A2 (en) 2012-08-29
EP2492960A3 (en) 2014-08-13
CN102651363A (zh) 2012-08-29
JP2012182455A (ja) 2012-09-20
US8847393B2 (en) 2014-09-30

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Address after: Texas in the United States

Patentee after: NXP America Co Ltd

Address before: Texas in the United States

Patentee before: Fisical Semiconductor Inc.