、發明說明： 【發明所屬之技術領域】 本發明係有關於半導體接觸窗結構，特別是指三維積 體電路之半導體裝置結構。 【先前技術】 在習知的半導體製造上，積體電路係使用單層之電晶 體’以平面方式建造。新發展之半導體製造允許晶圓垂直 的堆豎。垂直積體電路意指一層上接一層地垂直放置數層 傳統平面技術產生的半導體電路，而形成三維積體電路。 這允許積體電路具有較高的裝置密度及較小的晶片面積。 二維積體電路典型地具有數層以一或多個介電層隔 離的導體層。配置在介電層内介層開口中之接觸窗結構提 供傳導路徑，以使得電信號能自一導體層通過至另一導 體層。 圖1A及圖1B分別顯示習知技術三維積體電路其中 一層接觸窗結構之側視及俯視圖。貫穿基板介層11〇 (TSV ’ through-substrate-via)係建於基板 100 内以提供 垂直連結至另一層。複數個接觸窗結構120覆蓋於貫穿基 板介層110之頂部表面，可透過金屬線13〇而電性連結至 建於基板100上之裝置。目前由於沒有特別的接觸窗結構 設計應用於三維貫穿基板介層晶圓，接觸窗結構12〇的尺 1375297 寸、形狀及組態沿用如圖1B傳統平面程序之設計規則。 因此製程範圍（process window)之接觸窗蝕刻會被限制。 此外，定義於傳統設計規則之電流通常遠小於通過貫穿基 板介層110之電流。因此三維積體電路之電流會被限制， 且在接觸窗界面有潛在的電遷移問題，這會限制產品的 型式。 # 因此虽進展至二維設計後’需要一種新的接觸窗結構 以解決上述問題。 【發明内容】 為解決上述問題，本發供_種_接觸窗結構， 以及-__於三_體電路之傳輸錢結構。本發明 2免除潛在的電遷移問題以及擴大製程範圍之接觸窗 钱刻。[Technical Field] The present invention relates to a semiconductor contact window structure, and more particularly to a semiconductor device structure of a three-dimensional integrated circuit. [Prior Art] In the conventional semiconductor fabrication, an integrated circuit is constructed in a planar manner using a single layer of electro-crystals. Newly developed semiconductor manufacturing allows wafer vertical stacking. The vertical integrated circuit means a semiconductor circuit generated by a plurality of layers of conventional planar technology placed vertically on a layer to form a three-dimensional integrated circuit. This allows the integrated circuit to have a higher device density and a smaller wafer area. Two-dimensional integrated circuits typically have several layers of conductor layers separated by one or more dielectric layers. The contact window structure disposed in the via opening in the dielectric layer provides a conductive path to enable electrical signals to pass from one conductor layer to another. 1A and 1B are side and top views, respectively, showing a structure of a contact window of a conventional three-dimensional integrated circuit. A TSV' through-substrate-via is built into the substrate 100 to provide vertical bonding to another layer. A plurality of contact window structures 120 are overlaid on the top surface of the substrate via 110, and are electrically connected to the device built on the substrate 100 through the metal wires 13A. At present, there is no special contact window structure. The design is applied to the three-dimensional through-substrate via wafer. The dimension of the contact window structure is 1375297 inch, and the shape and configuration follow the design rule of the traditional planar program as shown in Fig. 1B. Therefore, the contact window etching of the process window is limited. Moreover, the current defined by conventional design rules is typically much smaller than the current through the substrate via 110. Therefore, the current of the three-dimensional integrated circuit is limited, and there is a potential electromigration problem at the contact window interface, which limits the type of product. # Therefore, although progressing to two-dimensional design, a new contact window structure is needed to solve the above problem. SUMMARY OF THE INVENTION In order to solve the above problems, the present invention provides a structure for transmitting a money, and a structure for transmitting money of a three-body circuit. The present invention 2 eliminates potential electromigration problems and expands the contact window of the process range.
一面向，提供一種用於三 ;:=基板;定義於基板内且自第-=4 接觸=結構。複數個第-接觸窗結構之各_第數 仃之截面具有第一側及第二側，且 =表面千 長側與較賴之比制大於2:】。’-側中之較 -6- 1375297 根據本發明的另-面向，提供一種用於三維積體電路 之半導體裝置結構。半導體裝置結構包含：具有第一表面 及第二表面之基板；定義祕㈣且自第—表面延伸至第 二表面之介/f ;以及位於第-表面與介層接觸之賴個第 -接觸窗結構。複數個第-接觸s結構之各個 平行之截面具有第，及第二側，且第—舰第二側^較 長側與較短側之比值約大於2 : !，且複數個接觸窗結構之 二積與平行於第-表面之介層之面積的比值约大於 二❶。貝穿基板介層之直徑約小於5微米。較短側之最小 ^度^、於0.4微米’且接觸窗結構之間隔約小於〇5微 飢’較知側之最小長度與間隔合併成接觸窗結構之最小節 距(pitch)約小於〇.9微米。 根據本發明更進一步的面 體結構。多晶片半導體結構包含二== 於第一晶 表面及第中二晶片包含··具有第--表面延伸於第一基板内且自第 接複數個第—接觸窗結構。複數個第一 第一侧個與第一表面平行之截面具有第一側及 之笛接觸®、、，D構之面積與平行於第-表面 =第一"層之_的比值約大於25%1—介層之靜One aspect provides a substrate for three;:=; defined in the substrate and from the -=4 contact = structure. The cross section of each of the plurality of first-contact window structures has a first side and a second side, and the ratio of the surface length to the surface is greater than 2:]. </ RTI> -6- 1375 297 According to another aspect of the present invention, a semiconductor device structure for a three-dimensional integrated circuit is provided. The semiconductor device structure includes: a substrate having a first surface and a second surface; a medium defining a secret (4) and extending from the first surface to the second surface; and a first contact window contacting the first surface and the dielectric layer structure. Each of the parallel cross sections of the plurality of first contact s structures has a first side and a second side, and the ratio of the longer side to the shorter side of the second side of the first ship is greater than about 2:!, and a plurality of contact window structures The ratio of the area of the second product to the interlayer parallel to the first surface is greater than about two. The shell-through substrate layer has a diameter of less than about 5 microns. The minimum length of the shorter side is 0.4 μm and the spacing between the contact window structures is less than 〇5. The minimum length and spacing of the known side are merged into a contact window structure with a minimum pitch of less than 〇. 9 microns. A further surface structure in accordance with the present invention. The multi-wafer semiconductor structure comprises two == on the first crystal surface and the second wafer comprises: a first surface extending in the first substrate and a plurality of first contact window structures. The plurality of first first sides are parallel to the first surface and have a first side and a flute contact, and the ratio of the area of the D structure to the __ parallel to the first surface of the first " layer is greater than about 25 %1 - the static of the layer
於5微米m最小長度約小於0.4微米，I 1375297 複數個第一接觸窗結構之間隔約小於05微来，第二側 之最小長度與卩純合併成複油第—接觸窗結構之最小 節距(pitch)約小於0.9微米。 ’、 本發明之目的、實施例、特徵及優點在下列較佳實施 例之特別說明，以及本發明之圖式中將顯而易見。 【實施方式】 本發明係有關於三維積體電路之半導體接觸窗社 構。參照圖2-6 ’在此本發明將被更詳細地說明。本發^ 所提供之半導體裝置結構及多晶片半導體結構，在具有接 觸齒結構後咸大幅提尚接觸窗面積比例，且避免可能的電 遷移(electro-migration)問題’接觸窗蝕刻之製程範圍也因 此被放大了。然而在在下列敘述中的裝置、元件、及方法 是用以說明本發明，而非用以限制之意。 圖2A係根據本發明用於三維積體電路之接觸窗_ 之側視圖，且圖2B-2E係顯示根據本發明之不同實施例之 數種接觸窗結構之佈局圖案。 參考圖2A ’提供-基板200，具有定義於基板内之貫 穿基板介層（TSV) 21G。基板可包含#、鍺、_、或 ^它可運用之半導體材料。複數個接觸窗結構22〇係位於 貝穿基板介層210之頂部表面，並連接至金屬線23〇。半 1375297 導體元件（例如邏輯元件）可利用習知技術之常見的方法 於基板200上形成，且透過金屬線23〇及接觸窗結構 耦合至貫穿基板介層210。貫穿基板介層210可包含鎢、 多晶矽、銅、釕、或其組合，且接觸窗結構22〇可包含鎢、 鋁、銅、釕、或其組合，而金屬線23〇可包含鎢、鋁、銅、 舒、或其組合。 參考圖2B-2E，提供新的三維積體電路接觸窗結構以 克服習知技術之問題。這些結構沿用現有的設計規則因 此本發明得以被直接實施而無額外的程序問題。須注意的 是在圖2B-2E中，貫穿基板介層21〇之形狀可包含但不限 於正方形。例如貫穿基板介層210之形狀可為圓形或長方 形。在一實施例中貫穿基板介層210可為圓形，且例如貫 穿基板介層21G之直徑介於次微級至微米級^穿基板 介層210之較佳雜介於約2齡至約5微米間，如圖 2B所示。 在圖2B’各個接觸窗結構22G為—具有長側⑴及 短侧（s)之長方形’且長側與短側之外觀比值（L/s)約 大於2 : 1。短側之最小長度及接觸窗結構22〇之節距受使 用的設計規則所限制。圖3A至冑3C中已定義在用於不 同技術節點（technology node)時，使用相同或或縮小之 貫穿基板介層尺寸，貫穿基板介層尺寸（D)與接觸窗臨 界尺寸（CD)及間隔間的關係。 側與^窗結構220具有較小的長 形。圖2D顯亍一，A 層之頂部表面被設計為圓 窗結構220之長‘3^；接觸窗結構220 ’其中接觸 形式之細ίΓ有 寸。圖2E _另一組合 長侧，且可&tn220，其中接觸窗結構220可具有不同 例可帶來不Π 排歹卜圖2Β·2Ε中所顯示的實施 瓜2Ε僅積比取从不151要求。圖 這此㈣/ 構之可能_，J'本發明不限於 口 L，，肩不1界尺寸、間隔、及貫穿基 保二其之定義。在圖3A ’當技術節點縮小時， _ I Ξ貝穿板介層尺寸’以及在圖3B，當技術節 j小時，縮小貫穿基板介層尺和參考圖从，對於技 ’、且A ’接觸窗之臨界尺寸及接觸窗結構22〇之間隔係 ^據貫穿基板介層尺寸⑼來定義，例如_D及01D。、 當技術節點自群組A縮小至群組B時，保持相同的貫穿 ，板介層尺寸D ’接觸窗臨界尺寸及接觸窗結構22〇之間 隔分別自0.08D及0.1D縮小至〇.〇6D及〇‘_。繼續參考 圖从’在群組A，貫穿基板介層之直徑為d，各接觸窗 臨界尺寸為0.08D，相鄰兩接觸窗之最小間隔為〇JD，且 取大接觸S為36。如圖1B習知技術之接職結構，其總 接觸窗面積與貫穿基板介層面積的比值為23.04%，本^ 之接觸窗結翻為4《44%。根據本發明與如_ 1Β習知技 術之接觸窗結構概，棘g與貫穿基板介層的面藉比 增加了㈣％。在群㈣及戦c，麟組“比，縮 小了接觸絲界尺寸但仍具有_貫穿基板介層尺寸D， =根據本伽來使祕觸窗結構設計，歧善複數個接觸 窗結構之面積與介層之頂部表面面積的比值從小於25% 至大於25%。 , 由於貫穿基板介層210之直徑d約小於5微米，在 -實施例中，對於圖3A群組A之技術節點，短側之最小 長度約小於0.4微米’且接觸窗結構22〇之間隔約小於〇 $ 微米，因此短側之最小長度與間隔合併成接觸窗結構22〇 約小於0.9微米之最小節距。在另一實施例中，對於緊端 設計規則的縮小技術節點（圖3A群組B)，具有相同約小 於5微米之貫穿基板介層尺寸D，賴之最小長度約小於 0.3微米，接觸窗結構220之間隔約小於〇·4微米，因此短 側之最小長度與間隔合併成接觸窗結構22〇約小於〇 7微 米之最小節距。 ' 參考圖3Β，在群組β及群組c，當技術節點縮小時， 貫穿基板介層尺寸分別自D縮小至〇 8D及〇 9D，且在群 組B及群組C ’本發明之面積的比值與習知技術相比分別 增加21.08%及23.63%。在一實施例中，對於更緊繃的設 計規則的縮小技術節點（圖3B群組B)，貫穿基板介層210 之直徑約小於4.5微米（自D縮小至0.9D) ’短側之最小 長度約小於0.3微米，且接觸窗結構220之間隔約小於〇.4 微米’因此短側之最小長度與間隔合併成接觸窗結構22〇 約小於0.7微米之最小節距。 參考圖4A及4B，本發明之接觸窗結構可應用於貫穿 基板400之介層410之上，且可應用於嵌入基板4〇2之介 層412之上。圖4A所示之結構可應用於製造傳輸線、法 拉第屏蔽（faraday cage)、或電感。圖4 B所示之結構可 應用於散開熱量。 圖5A及5B係顯示根據本發明之半導體裝置結構之 俯視圖。參考圖5A，介層510透過複數個接觸窗結構52〇 耦合至金屬線530，其中介層51〇及金屬線53〇為實質相 同尺寸。金屬線530可包含鎢、鋁、銅、釕、或以上之化 合物。圖5A所示之結構可應用於遭受大電流之結構，例 如電遷移測試結構或輪入輸出結構。參考圖，介層512 分別透過接觸窗結構522及接觸窗結構524耦合至金屬線 532及金屬線534 ’其中介層512之尺寸遠大於金屬線532 或金屬線534。金屬線532可包含鎢、鋁、銅、釕、或以 上之化合物。圖5B所不之結構可應用於一般的傳輸線。 1375297 圖6係根據本發明之一實施例之多晶片半導體結構之 一側視圖’包含：第一晶片600，附著於第一晶片600之 第二晶片610’以及附著於第二晶>} 610之第三晶片62〇。 第一晶片600包含：接合整602、基板603、介層604、接 觸窗結構606及金屬線608。第二晶片610包含：接合墊 612、基板613、介層614、接觸窗結構616及金屬線618。 弟二晶月620包含：接合塾622、基板623、介層624、接 觸囪結構626及金屬線628。介層604、614、及624可分 別貫穿基板603、613、及623。在另一實施例中，晶片6〇Λ〇 可包含嵌入基板603之介層605。金屬線608、618、及628 可包含鶴、IS、銅、釕、或以上之化合物。各接觸窗結構 606、616、及626具有複數個接觸窗結構，且各接觸窗結 構具有第一側及第二側。如上所述，其第一側及第二側之 較長側與較短側之士值約大於2 : !。最少一晶片其複數個 搂觸窗結構之面積與介層頂部表面面積的比值約大於 乃％ ’且更佳為大於30%。介層之直徑約小於5微米。第 二側之最小長度約小於G.4微米’轉數個接觸窗結構之 ，隔約小於0.5财’鼠第二側之最小長度與間隔合併 成複數個接觸窗結構約小於〇.9微米之最小節距。 的接供—種驗三維積體電路，獨—且容易檢查 本發明之接觸窗結構可在接觸窗及深介層 =體^U面上避免潛在的電遷移問題，且可加強傳輸互 連之電流而可使不_三維晶圓產品成為可能。 13 變或調整皆應被包含於所附申物所實施的改 【圖式簡單說明】 ^ 1A及圖1B係根據習知技術而分別顯示三維積體 電路/、t -層接觸g結構之侧視及俯視圖； 、 圖2A係根據本發明用於三維積體電路之接觸窗結 之侧視圖； ® 2B-2E係顯示根據本發明之實施例之數種接觸窗姓 構之佈局圖案； 'σ 圖3Α-3Β列出不同三維積體電路（3DIC)方案之接 觸窗面積比例的表格，圖3C顯示臨界尺寸、間隔、及貫 穿基板介層（TSV)尺寸D之定義； 圖4A-4B顯示本發明之介層應用於不同實施上； 圖5A-5B係顯示根據本發明之半導體裝置結構之俯 視圖；以及 圖6係根據本發明之一實施例之多晶片半導體結構之 一側視圖。 1375297The minimum length of 5 micrometers m is less than 0.4 micrometers, and the interval between the plurality of first contact window structures of I 1375297 is less than about 05 micrometers, and the minimum length of the second side is combined with the minimum length of the pure oil first-contact window structure. (Pitch) is less than about 0.9 microns. The objectives, embodiments, features, and advantages of the present invention will be apparent from the description of the preferred embodiments of the invention. [Embodiment] The present invention relates to a semiconductor contact window structure for a three-dimensional integrated circuit. Referring to Figures 2-6', the invention will be described in greater detail herein. The semiconductor device structure and the multi-wafer semiconductor structure provided by the present invention have a contact-tooth structure and greatly increase the proportion of the contact window area, and avoid possible electro-migration problems. The process range of the contact window etching is also Therefore it has been enlarged. However, the devices, elements, and methods in the following description are illustrative of the invention and are not intended to be limiting. 2A is a side view of a contact window for a three-dimensional integrated circuit in accordance with the present invention, and FIGS. 2B-2E show a layout pattern of several contact window structures in accordance with various embodiments of the present invention. Referring to Figure 2A' provides a substrate 200 having a through substrate via (TSV) 21G defined within the substrate. The substrate may comprise #, 锗, _, or ^ a semiconductor material to which it can be applied. A plurality of contact window structures 22 are located on the top surface of the via substrate via 210 and are connected to the metal lines 23A. Half 1375297 conductor elements (e.g., logic elements) may be formed on substrate 200 using conventional methods of the prior art and coupled to through substrate via 210 via metal lines 23 and contact structures. The through substrate via 210 may comprise tungsten, polysilicon, copper, tantalum, or a combination thereof, and the contact structure 22 may include tungsten, aluminum, copper, tantalum, or a combination thereof, and the metal line 23 may include tungsten, aluminum, Copper, Shu, or a combination thereof. Referring to Figures 2B-2E, a new three-dimensional integrated circuit contact window structure is provided to overcome the problems of the prior art. These structures follow existing design rules and thus the present invention can be implemented directly without additional procedural issues. It should be noted that in Figures 2B-2E, the shape of the through substrate via 21 can include, but is not limited to, a square. For example, the shape of the through substrate via 210 may be circular or rectangular. In one embodiment, the through substrate via 210 may be circular, and the diameter of the through-substrate via 21G is, for example, between the second to the micron-sized substrate via 210, preferably between about 2 and about 5 Between microns, as shown in Figure 2B. In Fig. 2B', each of the contact window structures 22G has a rectangular shape having a long side (1) and a short side (s) and an appearance ratio (L/s) of the long side to the short side is greater than about 2:1. The minimum length of the short side and the pitch of the contact window structure 22〇 are limited by the design rules used. 3A to 3C have been defined to use the same or reduced through-substrate via size, through-substrate via dimension (D) and contact window critical dimension (CD) and spacing when used in different technology nodes. Relationship between. The side and window structure 220 has a small elongated shape. As shown in Fig. 2D, the top surface of the A layer is designed to have the length '32 of the round window structure 220; the contact window structure 220' in which the contact form is thin. 2E _ another combined long side, and can be & tn220, wherein the contact window structure 220 can have different examples can bring the 歹 歹 歹 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 151 151 151 151 151 Claim. Figure (4) / Structure possible _, J' The present invention is not limited to the mouth L, the shoulder is not a boundary size, spacing, and the definition of the basics. In Figure 3A 'When the technology node is zoomed out, _I mussels pass through the via size' and in Figure 3B, when the technical section is j, the through-substrate via and the reference map are reduced, for the technique ', and A' contact The critical dimension of the window and the spacing of the contact window structure 22 are defined by the through-substrate via size (9), such as _D and 01D. When the technology node is reduced from group A to group B, the same penetration is maintained, and the interface dimension D' contact window critical dimension and the contact window structure 22 are reduced from 0.08D and 0.1D to 〇.〇. 6D and 〇'_. With continued reference to the figure from 'group A, the diameter of the through-substrate via is d, the critical dimension of each contact window is 0.08D, the minimum spacing between adjacent two contact windows is 〇JD, and the large contact S is 36. As shown in the prior art structure of the prior art, the ratio of the total contact window area to the area of the through-substrate via layer is 23.04%, and the contact window of this ^ is turned to 4 "44%. According to the contact window structure of the conventional technique of the present invention, the ratio of the spine g to the surface of the through-substrate via is increased by (4)%. In the group (four) and 戦c, the Lin group "ratio narrows the size of the contact wire boundary but still has the size of the through-substrate interlayer D, = according to the design of the secret contact window structure according to the gamma, the area of the multiple contact window structure The ratio of the surface area to the top surface of the via is from less than 25% to more than 25%. Since the diameter d through the substrate via 210 is less than about 5 microns, in the embodiment, for the technical node of group A of Figure 3A, short The minimum length of the sides is less than about 0.4 microns' and the spacing of the contact window structures 22 is less than about 〇$ microns, so the minimum length of the short sides and the spacing merge into a minimum pitch of the contact structure 22 that is less than about 0.9 microns. In an embodiment, the shrinking technology node for the tight end design rule (Group B of FIG. 3A) has the same through-substrate via size D of less than about 5 microns, and the minimum length is less than about 0.3 microns, and the spacing of the contact window structures 220 It is less than 〇·4 μm, so the minimum length of the short side and the interval are merged into a contact window structure 22, which is less than the minimum pitch of 〇7 μm. 'Refer to Figure 3Β, in group β and group c, when the technology node is reduced Through the substrate The layer sizes are reduced from D to 〇8D and 〇9D, respectively, and the ratio of the area of the invention in Group B and Group C' is increased by 21.08% and 23.63%, respectively, compared to the prior art. In an embodiment, The tighter design rule of the shrinking technology node (Fig. 3B Group B), the diameter of the through substrate via 210 is less than about 4.5 microns (from D to 0.9D). The short side has a minimum length of less than about 0.3 microns and is in contact. The spacing of the window structures 220 is less than about 4.4 microns' such that the minimum length of the short sides and the spacing merge into a minimum pitch of the contact window structure 22 of less than about 0.7 microns. Referring to Figures 4A and 4B, the contact window structure of the present invention can be applied. It is applied over the via 410 of the substrate 400 and can be applied over the via 412 embedded in the substrate 4. The structure shown in FIG. 4A can be applied to fabricate transmission lines, faraday cages, or inductors. 4A and 5B are top views showing the structure of a semiconductor device in accordance with the present invention. Referring to FIG. 5A, a via 510 is coupled to a metal line 530 through a plurality of contact structures 52. Interposer 51 and metal 53〇 is substantially the same size. The metal wire 530 may comprise a compound of tungsten, aluminum, copper, tantalum, or the like. The structure shown in FIG. 5A can be applied to a structure that is subjected to a large current, such as an electromigration test structure or a wheel-in output structure. Referring to the drawing, the via 512 is coupled to the metal line 532 and the metal line 534 ' through the contact structure 522 and the contact structure 524, respectively, wherein the via 512 is much larger than the metal line 532 or the metal line 534. The metal line 532 may comprise tungsten. A compound of aluminum, copper, tantalum, or the like. The structure of Figure 5B can be applied to a general transmission line. 1375297 Figure 6 is a side view of a multi-wafer semiconductor structure according to an embodiment of the present invention. The wafer 600 is attached to the second wafer 610 ′ of the first wafer 600 and to the third wafer 62 附着 attached to the second crystal 610 . The first wafer 600 includes a bonding 602, a substrate 603, a via 604, a contact window structure 606, and a metal line 608. The second wafer 610 includes a bonding pad 612, a substrate 613, a via 614, a contact window structure 616, and a metal line 618. The second crystal moon 620 includes a bonding pad 622, a substrate 623, a via 624, a contact via structure 626, and a metal line 628. The vias 604, 614, and 624 may extend through the substrates 603, 613, and 623, respectively. In another embodiment, the wafer 6A can include a via 605 embedded in the substrate 603. Metal lines 608, 618, and 628 can comprise a compound of crane, IS, copper, ruthenium, or the like. Each of the contact window structures 606, 616, and 626 has a plurality of contact window structures, and each contact window structure has a first side and a second side. As described above, the longer side and the shorter side of the first side and the second side have a value greater than about 2:. The ratio of the area of the plurality of erbium structures to the top surface area of the at least one wafer is greater than about %' and more preferably greater than 30%. The via is about less than 5 microns in diameter. The minimum length of the second side is less than about G.4 micrometers. The number of contact window structures is less than 0.5%. The minimum length and spacing of the second side of the mouse are combined into a plurality of contact window structures of less than 〇.9 μm. Minimum pitch. The connection of the three-dimensional integrated circuit, independent and easy to check the contact window structure of the present invention can avoid potential electromigration problems in the contact window and deep interlayer = body surface, and can enhance the transmission interconnection Current can make non-three-dimensional wafer products possible. 13 Changes or adjustments should be included in the attached application. [Simplified description of the drawings] ^ 1A and Figure 1B show the side of the three-dimensional integrated circuit /, t - layer contact g structure according to the prior art. 2A is a side view of a contact window junction for a three-dimensional integrated circuit according to the present invention; ® 2B-2E shows a layout pattern of several contact window surnames according to an embodiment of the present invention; 'σ Figure 3Α-3Β lists the contact window area ratios for different 3D integrated circuits (3DIC) schemes, and Figure 3C shows the definitions of critical dimensions, spacing, and through-substrate vias (TSV) dimensions D; Figures 4A-4B show this The inventive layers are applied to different implementations; Figures 5A-5B are top views showing the structure of a semiconductor device in accordance with the present invention; and Figure 6 is a side view of a multi-wafer semiconductor structure in accordance with an embodiment of the present invention. 1375297
【主要元件符號說明】 100基板 120接觸窗結構 200基板 220接觸窗結構 400基板 410基板 510介層 520接觸窗結構 524接觸窗結構 532金屬線 600第一晶片 603基板 605介層 608金屬線 612接合墊 614介層 618金屬線 622接合墊 624介層 628金屬線 110貫穿基板介層 130金屬線 210貫穿基板介層 230金屬線 402介層 412介層 512介層 522接觸窗結構 530金屬線 534金屬線 602接合墊 604介層 606接觸窗結構 610第二晶片 613基板 616接觸窗結構 620第三晶片 623基板 626接觸窗結構 •15-[Main component symbol description] 100 substrate 120 contact window structure 200 substrate 220 contact window structure 400 substrate 410 substrate 510 via 520 contact window structure 524 contact window structure 532 metal line 600 first wafer 603 substrate 605 via 608 metal line 612 bonding Pad 614 via 618 metal line 622 bond pad 624 via 628 metal line 110 through substrate via 130 metal line 210 through substrate via 230 metal line 402 via 412 via 512 via 522 contact window structure 530 metal line 534 metal Line 602 bond pad 604 via 606 contact window structure 610 second wafer 613 substrate 616 contact window structure 620 third wafer 623 substrate 626 contact window structure • 15-