CN102569401B - 半导体装置及半导体包装 - Google Patents

半导体装置及半导体包装 Download PDF

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CN102569401B
CN102569401B CN201110415695.6A CN201110415695A CN102569401B CN 102569401 B CN102569401 B CN 102569401B CN 201110415695 A CN201110415695 A CN 201110415695A CN 102569401 B CN102569401 B CN 102569401B
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semiconductor layer
groove
semiconductor device
area
transistor
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CN102569401A (zh
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吉持贤
吉持贤一
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Rohm Co Ltd
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Rohm Co Ltd
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Abstract

本申请提供一种在一个芯片内形成着晶体管及肖特基势垒二极管的构成中，能够确保晶体管的耐压并降低肖特基势垒二极管的顺向电压的半导体装置、以及用树脂包装覆盖半导体装置而成的半导体包装。半导体装置1包含半导体层22、形成在半导体层22上且构成晶体管11的晶体管区域D、及形成在半导体层22上且构成肖特基势垒二极管10的二极管区域C，且二极管区域C的半导体层22比晶体管区域D的半导体层22薄。

Description

半导体装置及半导体包装
技术领域
本发明涉及一种半导体装置及使用树脂包装覆盖此半导体装置而成的半导体包装。
背景技术
专利文献1中公开的半导体装置中内置了连接在源极、汲极间的肖特基势垒二极管。更详细来说，所述半导体装置中，在层叠于n型半导体基板上的n型半导体层的表层部，形成着p型基极层。并且，形成从n型半导体层表面掘入而贯穿p型基极层的沟槽，且于沟槽的侧壁及底面上形成着栅极绝缘膜。沟槽内嵌入着栅极电极。在p型基极层的表层部形成着n型扩散层。
借此，在所述半导体装置中形成沟槽栅极型晶体管。在所述晶体管中，n型扩散层为源极区域，n型半导体层为汲极区域，在n型扩散层与n型半导体层之间的p型基极层和栅极绝缘膜的界面附近形成通道，由此在源极区域与汲极区域之间流通电流。
在n型半导体层的表面层叠着金属层。金属层通过与n型扩散层接触而发挥源极电极的功能，并且通过在n型半导体层的表面与p型基极层外的区域接触，而在该区域与金属层之间形成肖特基接合。这样，所述半导体装置中，在一个芯片内形成晶体管和肖特基势垒二极管。
先行技术文献
专利文献
专利文献1：日本专利特开2009-59860号公报
发明内容
为了确保晶体管的耐压，n型半导体层的厚度需要为特定以上的厚度。所述n型半导体层的厚度在专利文献1的半导体装置中，形成着晶体管的区域、和形成着肖特基势垒二极管的区域内是相等的。因此，虽然能够确保晶体管的耐压，但是在肖特基势垒二极管的区域，n型半导体层设为必要以上的厚度，所以肖特基势垒二极管的直流电阻变大。因此，难以降低肖特基势垒二极管的顺向电压(VF)。
所以，本发明的目的在于提供一种在一个芯片内形成着晶体管及肖特基势垒二极管的构成中，能够确保晶体管的耐压，并降低肖特基势垒二极管的顺向电压的半导体装置、以及用树脂包装覆盖所述半导体装置而成的半导体包装。
本发明的半导体装置包含半导体层、形成在所述半导体层上且构成晶体管的晶体管区域、及形成在所述半导体层上且构成肖特基势垒二极管的二极管区域，且所述二极管区域的所述半导体层比所述晶体管区域的所述半导体层薄(技术方案1)。
根据所述构成，在晶体管区域中，半导体层的厚度为了确保晶体管的耐压而设为必要厚度，另一方面，二极管区域中可以将半导体层的厚度设为必要最小限度。借此，可以降低肖特基势垒二极管的直流电阻，从而能够降低其顺向电压。也就是说，能够使半导体层的厚度在晶体管区域及二极管区域中分别最佳化，因此在一个芯片内形成着晶体管及肖特基势垒二极管的构成中，能够确保晶体管的耐压，并降低肖特基势垒二极管的顺向电压。
优选为所述二极管区域的所述半导体层比所述晶体管区域的所述半导体层薄1μm以上(技术方案2)。
优选为所述二极管区域的所述半导体层的厚度为2.5μm以上(技术方案3)。
根据所述构成，可以确保肖特基势垒二极管的最低限度的耐压。
优选为当所述晶体管是具有从所述晶体管区域的所述半导体层表面掘入的第1沟槽的沟槽型晶体管时，所述第1沟槽的底面、与所述二极管区域的所述半导体层的表面，在所述半导体层的厚度方向上位于相同位置上(技术方案4)。
根据所述构成，可以在同一步骤中同时执行形成第1沟槽的步骤、以及从表面侧研磨二极管区域的半导体层而使其变薄的步骤，因此可以通过削减制造步骤数来降低半导体装置的制造成本。这样一来，能够提供廉价且高性能的半导体装置。
然而，在所述半导体层的厚度方向上，与所述二极管区域的所述半导体层表面相比，所述第1沟槽的底面也可以位于距所述半导体层的背面更远的位置上(技术方案5)，还可以位于距所述半导体层的背面更近的位置上(技术方案6)。
优选为所述第1沟槽的深度为1μm以上(技术方案7)。
优选为所述第1沟槽的内表面上形成着含有SiO2的栅极绝缘膜(技术方案8)。优选为在所述第1沟槽的所述栅极绝缘膜的内侧，嵌入含有多晶硅的栅极电极(技术方案9)。
优选为当所述晶体管包含主体区域、汲极区域及源极区域时，所述半导体层上形成着用于与所述源极区域实现接触的第2沟槽，该第2沟槽是从所述晶体管区域的所述半导体层表面掘入而形成，且所述二极管区域的所述半导体层表面位于比所述第2沟槽的底面更深的位置上(技术方案10)。
优选为从所述半导体层的厚度方向观察而俯视时，所述第1沟槽及所述第2沟槽是交替地配置(技术方案11)。这种情况下，所述第1沟槽及所述第2沟槽既可以形成为条状(技术方案12)，也可以是所述第1沟槽形成为在内侧具有配置着所述第2沟槽的网目状区域的网目状(技术方案13)。
所述晶体管也可以是平面型晶体管(技术方案14)。
优选为从所述半导体层的厚度方向观察而俯视时，所述晶体管区域包围所述二极管区域(技术方案15)。
当晶体管区域的晶体管接通(ON)时二极管区域的肖特基势垒二极管断开(OFF)，借此可以利用二极管区域实现半导体层的散热。而且，当晶体管断开时，可以利用晶体管区域实现半导体层的散热。这样可以阻止半导体装置的温度上升。尤其是，通过将晶体管区域配置为包围二极管区域，可以透过其中一个区域来实现另一区域的散热，因此能够有效地抑制半导体装置的温度上升。并且，当二极管区域有多个时，若将这些二极管区域分散配置为隔开特定间隔而均匀分布，则可更有效地抑制半导体装置的温度上升。
优选为还包含金属膜，该金属膜与所述晶体管电性连接，并且与所述二极管区域的所述半导体层肖特基接合(技术方案16)。这种情况下，所述金属膜优选含有钛、钼、钯或氮化钛(技术方案17)。
优选为所述半导体层是通过从半导体基板表面磊晶成长而形成的层(技术方案18)。
优选为所述半导体装置还包含背面电极，该背面电极与所述半导体基板的背面欧姆接触(技术方案19)。
本发明的半导体包装包含所述半导体装置、及覆盖所述半导体装置的树脂包装(技术方案20)。
附图说明
图1是本发明一实施方式的半导体装置的示意性平面图。
图2是本发明其他实施方式的半导体装置的示意性平面图。
图3是图1或图2的半导体装置的主要部的放大图。
图4是表示图3的半导体装置的主要部的变形例的图。
图5是图3或图4的切断面线V-V的截面图。
图6A是表示图5所示的半导体装置的制造方法的图解性截面图。
图6B是表示图6A的下一步骤的图解性截面图。
图6C是表示图6B的下一步骤的图解性截面图。
图6D是表示图6C的下一步骤的图解性截面图。
图6E是表示图6D的下一步骤的图解性截面图。
图6F是表示图6E的下一步骤的图解性截面图。
图6G是表示图6F的下一步骤的图解性截面图。
图6H是表示图6G的下一步骤的图解性截面图。
图6I是表示图6H的下一步骤的图解性截面图。
图6J是表示图6I的下一步骤的图解性截面图。
图6K是表示图6J的下一步骤的图解性截面图。
图6L是表示图6K的下一步骤的图解性截面图。
图6M是表示图6L的下一步骤的图解性截面图。
图7是本发明的其他实施方式的半导体装置的图解性截面图。
图8是本发明的其他实施方式的半导体装置的图解性截面图。
图9是本发明一实施方式的半导体包装的示意性透视图。
图10是应用本发明的半导体装置的DC-DC转换器的电路图。
[符号的说明]
1 半导体装置
10 肖特基势垒二极管
11 晶体管
12 第1沟槽
12A 底面
13 第2沟槽
13A 底面
21 背面电极
22 半导体层
22A 表面
22B 背面
23 栅极绝缘膜
24 栅极电极
27 第1金属膜
31 p-型半导体层
32 n+型半导体层
34 n-型半导体层
41 金属膜
53 金属膜
60 半导体包装
65 树脂包装
C 二极管区域
D 晶体管区域
具体实施方式
下面，参照附图，而详细说明本发明的实施方式。
图1是本发明一实施方式的半导体装置的示意性平面图。图2是本发明其他实施方式的半导体装置的示意性平面图。
本发明一实施方式的半导体装置1是形成为俯视四边形的芯片状。俯视时半导体装置1的四边各自的长度例如为数mm左右。
在半导体装置1的俯视四边形的表面上，其一边附近沿着该一边而形成着外部连接区域A，在外部连接区域A以外的区域内形成着活动区域B。半导体装置1具备：配置在外部连接区域A的多个外部电极2；包围活动区域B的护圈3；配置在活动区域B的多个二极管区域C；及活动区域B内除了二极管区域C以外的晶体管区域D。
多个(此处为7个)外部电极2是沿着四边形的一边而排列配置。各外部电极2是通过接线(未图示)而连接于引线(未图示)(下文叙述)。护圈3将外部连接区域A与活动区域B分离绝缘。
多个二极管区域C以在整个活动区域B均匀分布的方式分散配置(离散配置)。具体来说，多个二极管区域C可以相互隔开间隔，像图1所示那样排列为锯齿状，也可以像图2所示那样排列成矩阵状。
图3是图1或图2的半导体装置的主要部的放大图。图4是表示图3的半导体装置的主要部的变形例的图。
图3将图1或图2中以虚线围住的部分(一个二极管区域C及其周围的晶体管区域D)抽选出来进行表示。
各二极管区域C在俯视时为正方形状。俯视时，各二极管区域C是被晶体管区域D包围。
二极管区域C内形成着肖特基势垒二极管10，晶体管区域D内形成着多个晶体管单元11A。多个晶体管单元11A相互连接，整体形成为一个晶体管11(参照图1)。晶体管11中内置着多个肖特基势垒二极管10(参照图1)。这样，在半导体装置1的活动区域B内，以包围多个肖特基势垒二极管10的方式而形成晶体管11(参照图1)。
关于多个晶体管单元11A(晶体管11)，下述第1沟槽12及第2沟槽13是遍及晶体管区域D的半导体装置1表面(严格来说是下述半导体层22的表面)的大致整个区域而掘入。第1沟槽12及第2沟槽13在俯视时均沿着第1方向Y呈直线状延伸，且在与第1方向Y正交的第2方向X上隔开间隔而在该第2方向X上交替配置。也就是说，第1沟槽12及第2沟槽13分别形成为条状。
第1沟槽12及第2沟槽13中，第2沟槽13还形成在最接近二极管区域C的位置上。位于最接近二极管区域C的位置上的第2沟槽13是包围整个二极管区域C的四边形环状。而且，与位于最接近二极管区域C的位置上的第2沟槽13邻接的第1沟槽12是包围所述整个第2沟槽13的四边形环状。
关于第1沟槽12及第2沟槽13的配置，还可以如图4所示，第1沟槽12通过具有网目状图案而划分为多个矩形网目状区域，在各矩形网目状区域内，将第2沟槽13相对于第1沟槽12隔开间隔而呈直线状延伸。这种情况下，位于最接近二极管区域C的位置上的第2沟槽13也是包围整个二极管区域C的四边形环状，且与所述第2沟槽13邻接的第1沟槽12也是包围所述整个第2沟槽13的四边形环状。
图5是图3或图4的切断面线V-V的截面图。
如图5所示，半导体装置1具备半导体基板20、背面电极21、半导体层22、栅极绝缘膜23、栅极电极24、氧化膜25、绝缘层26、第1金属膜27、第2金属膜29、源极电极28、及配线层30。
半导体基板20包含n+型半导体(例如硅)。
背面电极21覆盖半导体基板20的整个背面(图5的下表面)。背面电极21包含与n型硅欧姆接触的金属(例如金、硅化镍、硅化钴)。因此，背面电极21与半导体基板20的背面欧姆接触。
半导体层22是层叠在半导体基板20的表面(图5的上表面)上。半导体层22包含浓度低于半导体基板20的n-型半导体。在图5的半导体层22中，将上表面称为表面22A，将下表面称为背面22B。整个半导体层22的厚度为例如4μm。
半导体层22上形成着所述二极管区域C及晶体管区域D。
图5中表示了二极管区域C与晶体管区域D的边界附近的半导体层22，二极管区域C的半导体层22比晶体管区域D的半导体层22薄。因此，二极管区域C的半导体层22的表面22A位于比晶体管区域D的半导体层22的表面22A更靠近半导体基板20侧的深位置上。所以，半导体层22的表面22A在二极管区域C内是向半导体基板20侧凹下。另一方面，半导体层22的背面22B遍及二极管区域C及晶体管区域D的整个区域而平坦，且与半导体层22的表面22A平行而延伸。
将晶体管区域D内的半导体层22的表面22A与背面22B之间的间隔称为间隔P，将二极管区域C内的半导体层22的表面22A与背面22B之间的间隔称为间隔Q。间隔P是晶体管区域D内的半导体层22的厚度。间隔Q是二极管区域C内的半导体层22的厚度。间隔P大于间隔Q。间隔P与间隔Q的差为例如1μm以上。也就是说，二极管区域C的半导体层22比晶体管区域D的半导体层22薄1μm以上。
晶体管区域D的半导体层22的整个表层部上，形成着p-型半导体层31。半导体层22上比p-型半导体层31更靠背面22B侧的区域是n-型半导体层34。在p-型半导体层31的表层部选择性形成着n+型半导体层32。n+型半导体层32的表面、与未形成n+型半导体层32的区域的p-型半导体层31的表面位于同一面内，形成晶体管区域D的半导体层22的表面22A。
晶体管区域D的半导体层22上形成着所述第1沟槽12。第1沟槽12是从晶体管区域D的半导体层22的表面22A向背面22B侧掘入。第1沟槽12将n+型半导体层32及p-型半导体层31一起贯穿而到达n-型半导体层34的中间层厚为止。第1沟槽12的底面12A(参照实线表示的底面12A)和半导体层22的背面22B之间的间隔R小于所述间隔P，其大小与间隔Q相同。也就是说，第1沟槽12的底面12A、和二极管区域C的半导体层22的表面22A在半导体层22的厚度方向上位于相同位置，且处于同一面内。第1沟槽12的深度为例如1μm以上。
栅极绝缘膜23含有氧化硅(SiO2)，形成为与第1沟槽12的整个内表面(侧壁面及底壁面)相接。
栅极电极24含有例如多晶硅。栅极电极24在第1沟槽12内是嵌入于栅极绝缘膜23的内侧。
氧化膜25含有SiO2，且覆盖晶体管区域D的半导体层22的大体整个表面22A。
绝缘层26含有BPSG(Boron Phosphor Silicate Glass，硼磷硅玻璃)等玻璃，且层叠于氧化膜25上。
所述第2沟槽13从绝缘层26的表面(图1中的上表面)开始掘入，贯穿绝缘层26及氧化膜25后，进一步在半导体层22贯穿n+型半导体层32而到达p-型半导体层31的中间层厚。第2沟槽13在晶体管区域D的半导体层22上，是形成在避开第1沟槽12的位置上，且从所述位置的半导体层22的表面22A开始掘入而形成。第2沟槽13的底面13A与半导体层22的背面22B之间的间隔S小于所述间隔P，且大于间隔Q及间隔R。也就是说，二极管区域C的半导体层22的表面22A位于比第2沟槽13的底面13A更深的位置上。
在p-型半导体层31的第2沟槽13周围，形成着p+型半导体层33。
第1金属膜27包含通过与n-型硅接合而形成肖特基接合的金属(例如钛(Ti)、钼(Mo)、钯(Pd)或氮化钛(TiN))。第1金属膜27系以与第2沟槽13整个内表面相接的方式形成，且在此状态下，与n+型半导体层32及p+型半导体层33电性连接(欧姆接触)。这样，第2沟槽13变成用来与n+型半导体层32及p+型半导体层33实现接触的部件。
另外，第1金属膜27覆盖绝缘层26的表面及阶差面、氧化膜25的阶差面、晶体管区域D的半导体层22的表面22A上未被氧化膜25覆盖的部分、半导体层22上形成二极管区域C与晶体管区域D的边界的阶差面22C、及二极管区域C的半导体层22的表面22A。第1金属膜27相对于二极管区域C的半导体层22(n-型半导体层34)的表面22A、及n-型半导体层34的阶差面22C而肖特基接合。阶差面22C是与表面22A正交。
源极电极28含有例如钨。源极电极28是镶嵌在内表面形成着第1金属膜27的第2沟槽13的内侧。
第2金属膜29含有钛或氮化钛，覆盖第1金属膜27的整个表面、和源极电极28中从第2沟槽13露出的面(图5中的上表面)。
配线层30含有例如铝和铜的合金(AlCu合金)。配线层30是层叠在第2金属膜29上，覆盖第2金属膜29的整个表面(图5中的上表面)。配线层30与所述多个外部电极2中对应的外部电极电性连接(参照图1及图2)。而且，栅极电极24透过未图示的转接配线而与对应的外部电极2电性连接。
在晶体管区域D内，配线层30、第2金属膜29、源极电极28、第1金属膜27、n+型半导体层32、及p+型半导体层33是电性连接。而且，背面电极21、半导体基板20、半导体层22上比p-型半导体层31更靠半导体基板20侧的n-型半导体层34是电性连接。
借此，在晶体管区域D内，构成各个晶体管单元11A。晶体管单元11A中，p-型半导体层31为主体区域，半导体基板20及n-型半导体层34为汲极区域，n+型半导体层32为源极区域。晶体管单元11A(晶体管11)具有嵌入着栅极电极24的第1沟槽12，所以它是所谓的沟槽栅极型MOSFET(Metal Oxide Semiconductor Field Effect Transistor，金属氧化物半导体-场效晶体管)。而且，在晶体管单元11A内，通过p-型半导体层31及n-型半导体层34而构成寄生二极管。
例如，在源极电极28(配线层30)接地、背面电极21上施加了正电压的状态下，对栅极电极24施加阈值以上的电压。这样，在p-型半导体层31与栅极电极24外侧的栅极绝缘膜23的界面附近的通道区域X内形成通道，透过此通道而从背面电极21向源极电极28流通电流。
而且，在二极管区域C内，背面电极21与半导体基板20欧姆接触，并且第1金属膜27与半导体层22的表面22A及阶差面22C肖特基接合，从而构成肖特基势垒二极管10。
二极管区域C的半导体层22的表面22A与背面22B的间隔Q越小，则晶体管区域D的半导体层22的表面22A与背面22B的间隔P之间的间隔Q的差就越大。这种情况下，能够降低肖特基势垒二极管10的半导体层22的直流电阻，并且能够增大所述阶差面22C的肖特基接合面，所以能够降低肖特基势垒二极管10的顺向电压，从而提高肖特基势垒二极管10的性能。但是，为了将肖特基势垒二极管10的耐压确保为最低限度，间隔Q优选为2.5μm以上。
图6A～图6M是表示图5所示的半导体装置的制造方法的图解性截面图。
首先，如图6A所示，利用众所周知的方法来制作半导体基板20。
接着，如图6B所示，从半导体基板20表面进行磊晶成长，由此在半导体基板20上形成半导体层22。
然后，向半导体层22的表层部离子注入p型杂质(例如硼)。之后，通过退火处理使p型杂质活化，如图6C所示，在半导体层22的表层部形成p-型半导体层31。半导体层22上比p-型半导体层31更靠半导体基板20侧的部分是n-型半导体层34。
接下来，向p-型半导体层31的表层部选择性离子注入n型杂质(例如砷化磷)。然后通过退火处理使n型杂质活化，如图6D所示，在p-型半导体层31的表层部形成n+型半导体层32。
接下来，将抗蚀剂图案(未图示)作为遮罩进行蚀刻，由此从半导体层22的表面22A侧开始掘入。借此，如图6E所示，在二极管区域C的半导体层22上，形成向背面22B侧凹下的凹部35，而在晶体管区域D的半导体层22上形成第1沟槽12。凹部35的底面35A、和第1沟槽12的底面12A在半导体层22的厚度方向上位于相同位置，且处于同一面内。
接着，通过例如CVD(Chemical Vapor Deposition：化学气相成长)法，如图6F所示，在第1沟槽12的整个内表面，形成含有SiO2的栅极绝缘膜23。
接下来，如图6G所示，在第1沟槽12的栅极绝缘膜23内侧，嵌入含有多晶硅的栅极电极24。
然后，通过例如CVD法，如图6H所示，在二极管区域C及晶体管区域D两者的半导体层22的表面22A、和二极管区域C及晶体管区域D的边界部分的半导体层22的阶差面22C的整个区域上，形成含有SiO2的膜(SiO2膜)36。
然后，如图6I所示，通过例如高密度中的CVD，在SiO2膜36上层叠含有BPSG等玻璃的层(玻璃层)37。
接着，将抗蚀剂图案(未图示)作为遮罩进行蚀刻，由此在晶体管区域D内，依次掘入玻璃层37、SiO2膜36及半导体层22。借此，如图6J所示，在晶体管区域D内形成第2沟槽13。
之后，透过第2沟槽13，向半导体层22的表层部选择性离子注入p型杂质(例如硼)。然后，通过退火处理使p型杂质活化，如图6K所示，在p-型半导体层31上的第2沟槽13附近的区域内形成p+型半导体层33。
接着，将抗蚀剂图案(未图示)作为遮罩进行蚀刻，由此选择性除去SiO2膜36及玻璃层37，如图6L所示，在晶体管区域D残留着SiO2膜36及玻璃层37。残留的SiO2膜36是氧化膜25，残留的玻璃层37是绝缘层26。
接下来，如图6M所示，在第2沟槽13的整个内表面、绝缘层26的表面及阶差面、氧化膜25的阶差面、和二极管区域C及晶体管区域D的半导体层22的表面22A及阶差面22C露出的整个区域上，形成含钛的第1金属膜27。
然后，在第2沟槽13的第1金属膜27内侧，嵌入含有钨的源极电极28。
接着，在第1金属膜27的整个表面、源极电极28从第2沟槽13露出的面上，形成含钛的第2金属膜29，另外，在第2金属膜29上层叠含铝的配线层30。并且，在半导体基板20的背面形成背面电极21后，完成图5所示的半导体装置1。还有，本实施方式中，是形成第1沟槽12时同时形成凹部35(参照图6E)，但这只是一个示例，也可以变更制造步骤，例如在形成第2沟槽13时(参照图6J)，同时形成凹部35。
图7及图8是本发明其他实施方式的半导体装置的图解性截面图。
接下来，说明与所述实施方式不同的其他实施方式，但以下实施方式中是对与所述实施方式中说明的部分对应的部分，附上相同参照符号，并省略其详细说明。无论是图7还是图8的情况下，俯视时晶体管区域D均包围二极管区域C(参照图1及图2)。
图7所示的半导体装置1与所述实施方式同样地也是沟槽栅极型MOSFET，但其不具有所述第2沟槽13(参照图5)。
图7所示的半导体装置1具备所述半导体基板20、背面电极21、半导体层22、栅极绝缘膜23及栅极电极24、绝缘层40、以及金属膜41。
半导体基板20含有n+型半导体。背面电极21覆盖半导体基板20的整个背面(图7中的下表面)，且与半导体基板20的背面欧姆接触。
半导体层22通过磊晶成长而层叠在半导体基板20的表面(图7中的上表面)上。半导体层22含有浓度低于半导体基板20的n-型半导体。在图7的半导体层22中，将上表面称为表面22A，将下表面称为背面22B。
图7中表示了二极管区域C与晶体管区域D的边界附近的半导体层22，二极管区域C的半导体层22比晶体管区域D的半导体层22薄。因此，二极管区域C的半导体层22的表面22A位于比晶体管区域D的半导体层22的表面22A更靠半导体基板20侧的深位置上。所以，半导体层22的表面22A在二极管区域C内是向半导体基板20侧凹下。晶体管区域D的半导体层22的表面22A与背面22B之间的间隔P大于二极管区域C的半导体层22的表面22A与背面22B之间的间隔Q。二极管区域C的半导体层22的厚度为2.5μm以上。
晶体管区域D的半导体层22的整个表层部上，形成着p-型半导体层31。在p-型半导体层31的表层部选择性形成n+型半导体层32。n+型半导体层32的表面、和未形成n+型半导体层32的区域的p-型半导体层31的表面处于同一面内，形成晶体管区域D的半导体层22的表面22A。
在晶体管区域D的半导体层22上，形成深度1μm以上的第1沟槽12。第1沟槽12是从晶体管区域D的半导体层22的表面22A向背面22B侧掘入而成。第1沟槽12在邻接于n+型半导体层32的位置上贯穿p-型半导体层31，到达比半导体层22的p-型半导体层31更靠背面22B侧的区域(称为n-型半导体层42)的中间。第1沟槽12的底面12A和半导体层22的背面22B之间的间隔R小于所述间隔P，其大小与间隔Q相同。也就是说，第1沟槽12的底面12A、和二极管区域C的半导体层22的表面22A在半导体层22的厚度方向上位于相同位置，且处于同一面内。
栅极绝缘膜23含有SiO2，且形成在第1沟槽12的整个内表面。
栅极电极24含有多晶硅，且嵌入于第1沟槽12的栅极绝缘膜23内侧。
绝缘层40含有SiO2，且选择性覆盖晶体管区域D的半导体层22的表面22A。绝缘层40覆盖在半导体层22的表面22A侧突出的栅极电极24的整个表面(图7中的上表面)，并与栅极电极24周围的栅极绝缘膜23相连，同时与第1沟槽12周围的n+型半导体层32及p-型半导体层31各自的表面部分接触。
金属膜41含有通过与n-型硅接合而形成肖特基接合的金属(所述钛、钼、钯或氮化钛)。金属膜41覆盖二极管区域C及晶体管区域D各自的半导体层22的整个表面22A、和半导体层22上形成二极管区域C与晶体管区域D的边界的阶差面22C的整个区域。金属膜41与二极管区域C的半导体层22(n-型半导体层42)的表面22A及阶差面22C肖特基接合。金属膜41与所述多个外部电极2中对应的外部电极电性连接(参照图1及图2)。而且，栅极电极24透过未图示的转接配线，与对应的外部电极2电性连接。
在所述半导体装置1中，金属膜41、p-型半导体层31、及n+型半导体层32电性连接。并且，背面电极21、半导体基板20、及半导体层22上比p-型半导体层31更靠半导体基板20侧的n-型半导体层42电性连接。
因此，晶体管区域D中构成晶体管单元11A，半导体基板20及n-型半导体层42百年城汲极区域，n+型半导体层32变成源极区域，p-型半导体层31变成主体区域。而且，在晶体管单元11A内，通过p-型半导体层31及n-型半导体层42而构成寄生二极管。
例如，在金属膜41接地且背面电极21施加了正电压的状态下，对栅极电极24施加阈值以上的电压。这样一来，在p-型半导体层31与栅极电极24外侧的栅极绝缘膜23的界面附近的通道区域X内形成通道，透过所述通道，从背面电极21向金属膜41流通电流。
而且，在二极管区域C内，背面电极21与半导体基板20欧姆接触，并且金属膜41与半导体层22的表面22A肖特基接合，从而构成肖特基势垒二极管10。
图8所示的半导体装置1的晶体管11(晶体管单元11A)是与所述实施方式结构不同的平面型MOSFET，其不具有所述第1沟槽12(参照图5及图7)。
图8所示的半导体装置1具备所述半导体基板20、背面电极21及半导体层22、栅极绝缘膜50、栅极电极51、绝缘膜52、以及金属膜53。
半导体基板20含有n+型半导体。背面电极21覆盖半导体基板20的整个背面(图8中的下表面)，且与半导体基板20的背面欧姆接触。
半导体层22通过磊晶成长而层叠在半导体基板20的表面(图8中的上表面)上。半导体层22含有浓度低于半导体基板20的n-型半导体。图8的半导体层22中，将上表面称为表面22A，将下表面称为背面22B。
图8中表示了二极管区域C与晶体管区域D的边界附近的半导体层22，且二极管区域C的半导体层22比晶体管区域D的半导体层22薄。因此，二极管区域C的半导体层22的表面22A位于比晶体管区域D的半导体层22的表面22A更靠半导体基板20侧的深位置上。因此，半导体层22的表面22A在二极管区域C是向半导体基板20侧凹下。晶体管区域D的半导体层22的表面22A与背面22B之间的间隔P大于二极管区域C的半导体层22的表面22A与背面22B之间的间隔Q。二极管区域C的半导体层22的厚度为2.5μm以上。
晶体管区域D的半导体层22的表层部上选择性形成着p-型半导体层54。p-型半导体层54形成着多个，且在半导体层22的表层部离散配置。各p-型半导体层54的表层部上形成着n+型半导体层55。n+型半导体层55的表面、和未形成n+型半导体层55的区域的p-型半导体层54的表面处于同一面内，且形成晶体管区域D的半导体层22的表面22A。
栅极绝缘膜50含有SiO2，且部分覆盖晶体管区域D的半导体层22的表面22A上。栅极绝缘膜50形成为在晶体管区域D的半导体层22的表面22A上，隔开间隔而跨越相邻n+型半导体层55两者。
栅极电极51含有例如多晶硅，且层叠于栅极绝缘膜50上。
绝缘膜52含有SiO2。绝缘膜52覆盖栅极电极51表面上未与栅极绝缘膜50接触的整个部分。绝缘膜52与栅极绝缘膜50相连。
金属膜53含有通过与n-型硅接合而形成肖特基接合的金属(所述钛、钼、钯或硅化钛)。金属膜53覆盖绝缘膜52、二极管区域C及晶体管区域D各自的半导体层22的整个表面22A、及形成半导体层22的二极管区域C与晶体管区域D的边界的阶差面22C。金属膜53与二极管区域C的半导体层22(严格来说是下述n-型半导体层56)的表面22A及阶差面22C肖特基接合。金属膜53与所述多个外部电极2中对应的外部电极电性连接(参照图1及图2)。而且，栅极电极51透过未图示的转接配线，与对应的外部电极2电性连接。
所述半导体装置1中，金属膜53、p-型半导体层54、及n+型半导体层55电性连接。并且，背面电极21、半导体基板20、及半导体层22上未形成p-型半导体层54及n+型半导体层55的部分(称为n-型半导体层56)电性连接。
借此，晶体管区域D内构成各个晶体管单元11A，且半导体基板20及n-型半导体层56变成汲极区域，n+型半导体层55变成源极区域，p-型半导体层54变成主体区域。而且，在晶体管单元11A内，通过p-型半导体层54及n-型半导体层56而构成寄生二极管。
例如，在金属膜53接地且背面电极21施加了正电压的状态下，对栅极电极51施加阈值以上的电压。这样一来，在p-型半导体层54与栅极绝缘膜50的界面附近的通道区域X内形成通道，透过所述通道而从背面电极21向金属膜53流通电流。
而且，在二极管区域C内，背面电极21与半导体基板20欧姆接触，并且金属膜53与半导体层22(n-型半导体层56)的表面22A及阶差面22C肖特基接合，从而构成肖特基势垒二极管10。
图9是本发明一实施方式的半导体包装的示意性透视图。
参照图9，半导体包装60包含所述任一半导体装置1、金属制引线框架61、及树脂包装65。
半导体装置1接合于引线框架61上。引线框架61包含矩形板状的芯片焊垫62、隔开间隔而配置在芯片焊垫62一边的引线63A、及从芯片焊垫62另一边延伸出的引线63B。引线63A及引线63B分别有多个(此处为4个)。
在半导体装置1中，背面电极21(参照图5、图7及图8)是接合于芯片焊垫62的上表面，且各引线63A、和半导体装置1表面上的对应的外部电极2是通过接线64而连接。借此，引线63A及63B、和半导体装置1内的肖特基势垒二极管10及晶体管11(参照图1及图2)电性连接。此处，在图9中，右端的外部电极2是连接于栅极电极24，其他外部电极2是连接于源极电极28(也参照图5)。这种情况下，在图9中，右端的引线63A是栅极侧引线，其他3根引线63A是源极侧引线。并且，所有引线63B都是汲极侧引线。
并且，处于相互接合状态的半导体装置1及引线框架61是以各引线63A及引线63B向外部露出的方式，被树脂包装65覆盖。半导体包装60使各引线63A及引线63B与安装配线基板(未图示)对向，而可连接(安装)于所述安装配线基板。
图10是应用本发明的半导体装置的DC-DC转换器的电路图。
在如图10所示的DC-DC转换器100中，控制部(IC)91上连接着高压侧(Highside)用晶体管92及低压侧(Lowside)用晶体管93，本发明的半导体装置1可以用作低压侧用晶体管93。这种情况下，半导体装置1的晶体管11变成低压侧用晶体管93，肖特基势垒二极管10将高压侧用晶体管92和低压侧用晶体管93连接。
如上所述，在所述半导体装置1中，二极管区域C的半导体层22比晶体管区域D的半导体层22薄(参照图5、图7及图8)。借此，在晶体管区域D中，可以将半导体层22的厚度设为用于确保晶体管11(各晶体管单元11A)的耐压的必要厚度，另一方面在二极管区域C，可以将半导体层22的厚度设为必要最小限度。借此，可以降低肖特基势垒二极管10的直流电阻，从而可以降低其顺向电压。也就是说，可以使半导体层22的厚度在晶体管区域D及二极管区域C分别最佳化，所以在一个芯片内形成着晶体管11及肖特基势垒二极管10的构成中，可以确保晶体管11的耐压，并降低肖特基势垒二极管10的顺向电压。
二极管区域C的半导体层22的厚度为2.5μm以上，所以能够确保肖特基势垒二极管10的最低限度的耐压。
在沟槽型晶体管11(晶体管单元11A)中，第1沟槽12的底面12A、和二极管区域C的半导体层22的表面22A在半导体层22的厚度方向上位于相同位置(参照图5及图7)。借此，能够在同一步骤中同时执行形成第1沟槽12的步骤、和从二极管区域C的半导体层22的表面22A侧研磨而使其变薄的步骤(形成凹部35的步骤)(参照图6E)。因此，可以通过削减制造步骤数来降低半导体装置1的制造成本。这样，可以提供廉价且高性能的半导体装置1。
但是，如果制造步骤数不存在问题，那么在半导体层22的厚度方向上，第1沟槽12的底面12A也可以如图5的一点链线所示，与二极管区域C的半导体层22的表面22A相比位于距半导体层22的背面22B更远的位置上。这种情况下，第1沟槽12的底面12A和半导体层22的背面22B之间的间隔R'(参照图5)，大于二极管区域C的半导体层22的表面22A和背面22B之间的间隔Q。
当然，在半导体层22的厚度方向上，第1沟槽12的底面12A也可以如图5的虚线所示，与二极管区域C的半导体层22的表面22A相比，位于更靠近半导体层22的背面22B的位置上。这种情况下，第1沟槽12的底面12A与半导体层22的背面22B的间隔R″(参照图5)小于所述间隔Q。
而且，从半导体层22的厚度方向观察而俯视时，晶体管区域D包围二极管区域C(参照图1～图4)。当晶体管区域D的晶体管11接通时，二极管区域C的肖特基势垒二极管10断开，借此可利用二极管区域C实现半导体层22的散热。而且，当晶体管11断开时，可以利用晶体管区域D实现半导体层22的散热。这样可以阻止半导体装置1的温度上升。尤其是，通过将晶体管区域D配置成包围二极管区域C，可以透过一个区域来实现另一区域的散热，因此可以有效地抑制半导体装置1的温度上升。并且，将多个二极管区域C分散配置成隔开特定间隔而均匀分布，从而可以更有效地抑制半导体装置1的温度上升(参照图1及图2)。
除了所述说明以外，本发明也可以通过各种各样的形态来实施，能够在权利要求的记载事项的范围内实施各种设计变更。

Claims (17)

1.一种半导体装置，包含：
半导体层；
晶体管区域，形成在所述半导体层上，构成晶体管；
二极管区域，形成在所述半导体层上，构成肖特基势垒二极管，
所述晶体管是具有从所述晶体管区域的所述半导体层的表面掘入的第1沟槽的沟槽型晶体管，且包含栅极绝缘膜、栅极电极、形成于所述栅极电极上的绝缘层、主体区域、汲极区域及源极区域；
在所述半导体层，形成着用于与所述源极区域实现接触的第2沟槽，该第2沟槽是贯通所述绝缘层且从所述晶体管区域的所述半导体层的表面掘入而形成；
第1金属膜，对所述第2沟槽的内表面的整个区域相接的方式形成，且于所述第2沟槽的底面及侧面分别与所述半导体层欧姆接触，并且与所述二极管区域的所述半导体层的表面向背向侧凹入的比所述第2沟槽的底面更深位置的凹部肖特基接触；
源极电极，埋入于所述第2沟槽中的所述第1金属膜的内侧；以及
第2金属膜，层叠有配线层，覆盖所述第1金属膜之表面整个区域，以及所述源极电极从所述第2沟槽所露出的面。
2.根据权利要求1所述的半导体装置，其中所述二极管区域的所述半导体层比所述晶体管区域的所述半导体层薄1μm以上。
3.根据权利要求1所述的半导体装置，其中所述二极管区域的所述半导体层的厚度为2.5μm以上。
4.根据权利要求1所述的半导体装置，其中
所述第1沟槽的底面、与所述二极管区域的所述半导体层的表面在所述半导体层的厚度方向上位于相同位置上。
5.根据权利要求1所述的半导体装置，其中
在所述半导体层的厚度方向上，与所述二极管区域的所述半导体层表面相比，所述第1沟槽的底面位于距所述半导体层背面更远的位置上。
6.根据权利要求1所述的半导体装置，其中
在所述半导体层的厚度方向上，与所述二极管区域的所述半导体层表面相比，所述第1沟槽的底面位于距所述半导体层背面更近的位置上。
7.根据权利要求4至6中任一权利要求所述的半导体装置，其中所述第1沟槽的深度为1μm以上。
8.根据权利要求4至6中任一权利要求所述的半导体装置，其中所述第1沟槽的内表面上形成着含有SiO2的栅极绝缘膜。
9.根据权利要求8所述的半导体装置，其中所述第1沟槽的所述栅极绝缘膜内侧，嵌入着含有多晶硅的栅极电极。
10.根据权利要求4至6中任一权利要求所述的半导体装置，其中从所述半导体层的厚度方向观察而俯视时，所述第1沟槽及所述第2沟槽是交替地配置。
11.根据权利要求10所述的半导体装置，其中所述第1沟槽及所述第2沟槽是形成为条状。
12.根据权利要求10所述的半导体装置，其中所述第1沟槽是形成为内侧具有配置着所述第2沟槽的网目状区域的网目状。
13.根据权利要求1所述的半导体装置，其中从所述半导体层的厚度方向观察而俯视时，所述晶体管区域包围所述二极管区域。
14.根据权利要求1所述的半导体装置，其中所述第1金属膜包含钛、钼、钯或氮化钛。
15.根据权利要求1所述的半导体装置，其中所述半导体层为通过从半导体基板表面磊晶成长而形成的层。
16.根据权利要求15所述的半导体装置，其中还包含背面电极，该背面电极与所述半导体基板的背面欧姆接触。
17.一种半导体包装，包含：根据权利要求1要求所述的半导体装置；及树脂包装，覆盖所述半导体装置。
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