CN102487051A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN102487051A
CN102487051A CN2011103799633A CN201110379963A CN102487051A CN 102487051 A CN102487051 A CN 102487051A CN 2011103799633 A CN2011103799633 A CN 2011103799633A CN 201110379963 A CN201110379963 A CN 201110379963A CN 102487051 A CN102487051 A CN 102487051A
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packaging body
substrate
coupling part
lead
moulding material
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本城广
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Sony Corp
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Sony Corp
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Abstract

一种半导体装置及其制造方法。该半导体装置包括基板、安装在基板上的半导体芯片、基板的上表面和半导体芯片采用绝缘材料密封的封装体以及暴露到封装体的上表面的模制材料。另外，该装置包括其一端连接到模制材料且另一端电连接到基板的引线，该引线从与模制材料连接的连接部分到与基板连接的连接部分由相同的材料一体形成，并且该引线与模制材料连接的连接部分暴露到封装体的上表面。

Description

半导体装置及其制造方法
技术领域
本发明涉及半导体装置及其制造方法，该半导体装置由包括半导体芯片的封装体形成。
背景技术
在电子设备中，提出了所谓的封装体上封装体(Package on Package，PoP)结构(例如，参考国际专利公开第WO 2006-082620号中的图1)，其中层叠了包括半导体芯片的多个封装体，以便实现采用半导体芯片的部件的小型化。
在PoP结构中，与多个封装体水平对齐的结构相比，优点在于减小了安装面积，并且传输通道短。
在现有技术的PoP结构中，下封装体和上封装体之间的连接采用下封装体的半导体芯片周边处提供的焊料球或配线实现。
在该构造中，上封装体必须形成到与焊料球等连接部分对应的大尺寸。
发明内容
如上所述，在下封装体和上封装体采用下封装体的半导体芯片的周边处提供的焊料球或配线连接的构造中，必须根据下封装体的尺寸设计上封装体。
为此，难于使上封装体标准化或者使用诸如通用封装体的任意封装体作为上封装体。另外，当新产品用在下封装体中时，也必须根据下封装体重新开发上封装体。
具体地讲，在下封装体和上封装体之间的连接采用焊料球实现的构造中，连接部分的尺寸由焊料球的节距或尺寸决定。
为了考虑封装体的弯曲而保证可靠连接，必须使焊料球具有大的节距和尺寸，从而，封装体的外部尺寸增加。
另外，如果上封装体中的半导体芯片的尺寸小于下封装体的尺寸，则上封装体的半导体芯片和与下封装体连接的连接部分之间的距离变长。在此情况下，可考虑采用中继板(relay board)中形成的配线层将与下封装体连接的连接部分连接到上封装体。
例如，可进行连接以使从基板的焊盘到上表面贯通的通孔形成在下封装体中，导电层埋设在通孔中，并且导电层和上封装体采用中继板中形成的配线层连接。
然而，当采用中继板时，必须分别在单独的工艺中在通孔和中继板的配线层中形成导电层，由此增加了工艺数量。从而，制造成本增加且生产率下降。
所希望的是提供这样的半导体装置及其制造方法，其中，能够改善具有PoP结构的上封装体的构造自由度，并且以比较低的成本制造装置。
根据本发明的实施例，所提供的半导体装置包括基板、安装在基板上的半导体芯片、通过采用绝缘材料密封基板的上表面和半导体芯片而构造的封装体以及暴露到封装体的上表面的模制材料(molding material)。
另外，该装置包括一端连接到模制材料且另一端电连接到基板的引线，该引线从与模制材料连接的连接部分到与基板连接的连接部分由相同的材料一体形成，该引线与模制材料连接的连接部分暴露到封装体的上表面。
根据本发明的上述实施例，该装置可由模制材料和引线构造，引线的一端连接到模制材料，而另一端电连接到基板，且该引线从与模制材料连接的连接部分到与基板连接的连接部分由相同的材料一体形成。
从而，能够采用现有技术容易且低成本地从基板电连接到封装体的上表面。
另外，因为引线和模制材料之间的连接部分暴露到封装体的上表面，所以可通过电连接其他封装体到暴露到封装体的上表面的与模制材料连接的连接部分而制造具有PoP结构的封装体。
另外，可采用引线使与其他封装体连接的连接部分从与基板连接的连接部分的正上方分离。从而，例如，即使其他封装体很小，也能连接其他封装体到与基板连接的连接部分。
根据本发明的另一个实施例，所提供的半导体装置包括：基板；第一半导体芯片，安装在基板上；第一封装体，通过采用绝缘材料密封基板的上表面和第一半导体芯片而构造；以及模制材料，暴露到第一封装体的上表面。
另外，该装置包括引线，其一端连接到模制材料，而另一端电连接到基板，该引线从与模制材料连接的连接部分到与基板连接的连接部分由相同的材料一体形成，与模制材料连接的连接部分暴露到第一封装体的上表面。
此外，该装置包括第二半导体芯片和第二封装体，第二封装体通过采用绝缘材料密封第二半导体芯片而构造，该第二封装体电连接到暴露到第一封装体的表面的引线与模制材料的连接部分。
根据本发明的上述实施例，该装置可由模制材料和引线构造，引线的一端连接到模制材料，而另一端电连接到基板，从与模制材料连接的连接部分到与基板连接的连接部分由相同的材料一体形成。
以这种方式，能够采用现有技术容易且低成本地实现基板和第一封装体的上表面之间的电连接。
另外，因为引线与模制材料的连接部分暴露到第一封装体的上表面，并且第二封装体电连接到与模制材料连接的连接部分，所以能够构造具有PoP结构的封装体。
此外，与第二封装体的连接部分可采用引线从与基板连接的连接部分的正上方分离。从而，例如，即使第二封装体很小，也能够连接第二封装体到与基板连接的连接部分。
根据本发明的再一个实施例，所提供的半导体装置的制造方法包括：在基板上安装半导体芯片；以及电连接一端连接到模制材料的引线的另一端的部分到基板，引线从与模制材料连接的连接部分到另一端由相同的材料一体形成。
此外，该方法包括通过采用绝缘材料密封基板的上表面、半导体芯片、引线和模制材料而形成封装体，从而暴露引线与模制材料的连接部分和模制材料到封装体的上表面。
根据本发明的上述实施例，在半导体装置的制造方法中，引线的一端可连接到模制材料，其另一端可电连接到基板，并且从与模制材料连接的连接部分到另一端由相同的材料一体形成。另外，封装体通过采用绝缘材料密封基板的上表面、半导体芯片、引线和模制材料而形成，从而将引线与模制材料的连接部分和模制材料暴露到上表面。
以这种方式，能够容易且低成本地实现基板和封装体的上表面之间的电连接。
另外，因为引线与模制材料的连接部分可暴露到封装体的上表面，所以能够通过电连接其他封装体到暴露到封装体的上表面的与模制材料连接的连接部分而制造具有PoP结构的封装体。
此外，能够采用引线使与第二封装体连接的连接部分从与基板连接的连接部分的正上方分离。
根据本发明的实施例，因为能够容易且低成本地实现基板和封装体的上表面之间电连接，所以能够以低成本构造和制造具有PoP结构的封装体。
另外，根据本发明的实施例，因为能够采用引线使与其他封装体(第二封装体)连接的连接部分从与基板连接的连接部分的正上方分离，所以能够改善其他封装体(第二封装体)的构造自由度。
以这种方式，例如，能够采用很小的封装体、通用的封装体或者标准的封装体作为其他封装体(第二封装体)。
附图说明
图1是根据本发明第一实施例的半导体装置的示意性构造图(示出局部侧表面的截面图)。
图2是示出图1所示半导体装置制造方法的制造工艺图。
图3是示出图1所示半导体装置制造方法的制造工艺图。
图4是示出图1所示半导体装置制造方法的制造工艺图。
图5是示出图1所示半导体装置制造方法的制造工艺图。
图6是示出图1所示半导体装置制造方法的制造工艺图。
图7是示出图1所示半导体装置制造方法的制造工艺图。
图8是图7的封装体的平面图，其中周边封装体具有TSOP构造。
图9A至9C是示出周边封装体A至C的制造方法的制造工艺图。
具体实施方式
在下文，将描述本发明的实施例。
另外，描述将以下面的顺序进行。
1.第一实施例
2.修改示例
<1.第一实施例>
图1是根据本发明第一实施例的半导体装置的示意性构造图(示出局部侧表面的截面图)。
半导体装置具有PoP结构，其中第一封装体(下封装体)10和第二封装体(上封装体)20被层叠。
第一封装体(下封装体)10包括第一半导体芯片11，该第一半导体芯片11采用模制树脂(mold resin)15密封。
第一半导体芯片11采用绝缘或导电焊膏13被管芯焊接(die-bonded)到内插板(interposer board)12。
内插板12通过在水平方向和竖直方向上在型芯材料(core material)中形成配线层17而构造。在配线层17当中，暴露到内插板12表面的配线层是焊盘17A。另外，第一封装体(下封装体)10在内插板12的上表面用模制树脂15完全密封时被构造。
绝缘材料(阻焊剂等)18形成在内插板12的上表面和下表面上，从而覆盖配线层17从内插板12暴露的一部分。
另外，在内插板12的下表面上形成多个焊料球16，该焊球16连接到暴露到下表面侧的配线层17。
此外，第一半导体芯片11的上表面上形成的电极焊盘(图中未示出)和内插板12的上表面上的配线层17采用金线14彼此电连接。
第二封装体(上封装体)20形成为用模制树脂24密封第二半导体芯片21。
第二半导体芯片21设置到基板上表面上的绝缘材料27，其中绝缘材料27形成在型芯材料22的上表面和下表面二者上。在该基板中，在其上表面或下表面中，配线层26形成在绝缘材料27内部或不存在绝缘材料27的部分中。另外，配线层26包括贯穿型芯材料的一部分的插塞层。在配线层26中，暴露到基板上表面的配线层是焊盘26A。另外，基板的上表面用模制树脂24完全密封，从而形成第二封装体(上封装体)20。
另外，焊料球25形成为连接到暴露到基板下表面的配线层26。
此外，第二半导体芯片21的上表面上形成的电极焊盘(图中未示出)和基板的上表面上的焊盘26A采用金线23彼此电连接。
另外，图1所示的第一封装体10中的金线14和焊料球16或第二封装体20的金线23并非全部存在于同一截面中。在图1中，对于这些部件14、16和23，如从侧面所看到的，存在于不同截面上的某些部件示出在一起。
具体地讲，在该实施例中，第一封装体10的内插板12的上表面上的焊盘17A和第二封装体20的焊料球25采用第一封装体10中提供的周边封装体30彼此电连接。
周边封装体30由模制树脂32和从模制树脂32延伸的引线框31形成。
另外，在周边封装体30中，模制树脂32和引线框31在模制树脂32附近的部分(连接部分)暴露到第一封装体10的模制树脂15的表面。第二封装体20的焊料球25电连接到暴露到第一封装体表面的引线框31在模制树脂32附近的连接部分。
此外，周边封装体30的引线框31形成为弯曲以具有鸥形翼(gullwing)形状。另外，引线框31的一端连接到模制树脂32而被固定，并且引线框31的另一端的前端连接到第一封装体10的内插板12的上表面上的焊盘17A。引线框31从作为与模制树脂32连接的连接部分的一端到作为与焊盘17A连接的连接部分的另一端由相同的材料一体形成。
周边封装体可采用现有技术的构造制造，从而，可以低成本制造。
在通常的周边封装体中，半导体芯片模制在模制树脂中，并且引线框和半导体芯片采用在模制树脂中的配线等彼此电连接。
根据该实施例的周边封装体30在模制树脂32中不包括半导体芯片或配线，从而，模制树脂32可也相应地形成为较薄。为此，例如，如果模制树脂32的模具改变到对应于薄模制树脂32的构造，则能够在普通周边封装体生产线上制造该周边封装体。
从周边封装体30的模制树脂32延伸的引线框31的设置没有特别限制。它可为LQFP(Low-profile Quad Flat Package，薄型四方扁平封装体)，其中引线框31在两个方向上水平地延伸，并且可为TSOP(Thin Small OutlinePackage，薄型小尺寸封装体)，其中引线框31在前后左右四个方向上延伸。
另外，在图1中，周边封装体30的模制树脂32和引线框31具有基本上相同的厚度，然而，厚度可彼此略微不同，并且任何一个可厚于另一个。
周边封装体30的引线框31的形状不限于鸥形翼形状，而是可为其他形状。另外，在图1中，引线框31的中间部分形成为在倾斜的方向上延伸，然而，引线框31的中间部分可形成为竖直延伸形状或者在基本上竖直的方向上延伸的形状。
无论引线框是什么形状，它可从作为与模制树脂连接的连接部分的一端到作为与基板连接的连接部分的另一端由相同的材料一体形成。
第一封装体10的第一半导体芯片11和第二封装体20的第二半导体芯片21的构造没有特别限制，并且可采用具有各种功能的半导体芯片。
具体地讲，例如，第一半导体芯片11可用作处理电路，而第二半导体芯片21可用作存储电路。
根据本发明的实施例，例如，能够如下所述制造半导体装置。
首先，如图2所示，制备内插板12。内插板12的构造为配线层17水平且竖直地形成在型芯材料上。在配线层17当中，内插板12的表面上的配线层17是焊盘17A。
随后，如图3所示，作为管芯焊接工艺，第一半导体芯片11采用导电或绝缘膏13被管芯焊接到内插板12。
随后，如图4所示，作为配线连接工艺，第一半导体芯片11上的电极焊盘(图中未示出)和内插板12的内部引线图案(配线层17)采用金线14彼此连接。
随后，如图5所示，由引线框31和模制树脂32形成的周边封装体30在引线框31的前端部中采用导电膏被管芯焊接到暴露到内插板12的表面的焊盘17A。
随后，如图6所示，作为模制工艺，仅在内插板12的一个表面上将第一半导体芯片11、金线14和周边封装体30(31和32)用模制树脂15密封，从而形成封装体。此时，通过使周边封装体30的上表面与模具的壁面接触，周边封装体30的引线框31和模制树脂32暴露到封装体的上表面。
随后，如图7所示，作为球安装工艺，作为外部端子的焊料球16安装在内插板12的后表面上，并且采用回流法牢固地固定。以这种方式，完成了图1所示的第一封装体(下封装体)10。
这里，图8中示出了图7所示封装体(第一封装体10)的平面图，其中周边封装体30(31和32)的构造是TSOP。
如图8所示，引线框31的一端的基本上圆形的部分埋设在周边封装体30的模制树脂32的左右边缘处形成的基本上圆形的孔中。在引线框31中，与模制树脂32连接的连接部分附近的部分暴露到第一封装体10的模制树脂15的表面。
其后，第二封装体(上封装体)20的下表面上的焊料球25连接到周边封装体30的引线框31(特别是连接到图8所示的基本上圆形的前端部)，其暴露到第一封装体(下封装体)10的上表面。
以这种方式，能够制造根据图1所示实施例的半导体装置。
另外，可如下所述制造周边封装体30。
制备如图9A所示线性延伸的引线框31。
随后，如图9B所示，作为模制工艺，引线框31的一个端部用模制树脂32密封。
随后，如图9C所示，作为引线形成工艺，引线框31位于模制树脂32外侧的外部引线部分形成为具有预定的鸥形翼形状。
以这种方式，能够制造由引线框31和模制树脂32形成的周边封装体30。
在根据上述实施例的半导体装置的构造中，引线框31的一端用模制树脂32密封且固定，构成周边封装体30。另外，引线框31的另一端连接到内插板12的上表面侧的焊盘17A，并且引线框31与模制树脂32连接的连接部分和模制树脂32暴露到第一封装体10的上表面。引线框31从作为与模制树脂32连接的连接部分的一端到作为与焊盘17A连接的连接部分的另一端由相同的材料一体形成。
以这种方式，能够容易且成本低地采用现有技术的周边封装体制造技术制造由引线框31和模制树脂32形成的周边封装体30。另外，因为引线框31从与模制树脂32连接的连接部分到与焊盘17A连接的连接部分由相同的材料一体形成，所以能够在内插板12和第一封装体10的上表面之间以低的材料成本进行电连接。
此外，引线框31与模制树脂32连接的连接部分暴露到第一封装体10的上表面，并且第二封装体20的焊料球25电连接到该连接部分，从而构成具有PoP结构的封装体。
因此，通过采用根据本发明实施例的构造，能够以低成本构造且制造具有PoP结构的封装体。
另外，能够采用引线框31使与第二封装体20连接的连接部分从内插板12与焊盘17A连接的连接部分的正上方分离。以这种方式，能够改善第二封装体20的构造自由度。
例如，即使第二封装体20小于第一封装体10，第二封装体20也可被连接。
例如，能够采用通用的封装体或标准的封装体作为第二封装体。通过采用通用的封装体或标准的封装体，能够降低开发成本，并且缩短开发周期。
另外，图1示出了第一封装体10和第二封装体20彼此连接的状态，然而，例如，采用根据该实施例的构造也能够制造和销售第一封装体10的单一体，其对应于通用的第二封装体20或标准的第二封装体20。
<2.修改示例>
在上述的实施例中，第二封装体20和周边封装体30之间的连接采用第二封装体20的基板的下表面形成的焊料球25实现。
在该修改示例中，第二封装体和第一封装体的上表面(周边封装体)之间的电连接不限于焊料球，而是可具有另外的构造。例如，示例了格栅阵列封装(Land GridArray，LGA)、引脚阵列封装(Pin GridArray，PGA)和各向异性导电层等。
在上述的实施例中，第一半导体芯片11和第二半导体芯片21分别用模制树脂15和模制树脂24密封，并且模制树脂32连接到引线框31的一端。
在该修改示例中，连接到密封半导体芯片的绝缘材料或引线一端的模制材料不限于模制树脂，而是可为绝缘材料(陶瓷等)或者由其他材料形成的模制材料。当模制树脂用作绝缘材料或模制材料时，与其他材料相比，能够易于密封并实现低成本。
在上述的实施例中，其中配线层17水平且竖直地形成在型芯材料上的内插板12用作第一封装体的基板。
在该修改示例中，具有另外构造的基板可用作第一封装体(下封装体)的基板。
可为这样的构造，其中半导体芯片安装到基板，引线可电连接到形成在该板的上表面上的配线层或焊盘，并且到封装体外部的电连接可在下表面等处实现。
在上述的实施例中，层叠两个封装体以形成具有PoP结构的封装体。然而，在该修改示例中，能够层叠三个或更多个封装体。
在该修改示例中，由引线和模制材料形成的连接构件用于在层叠的n个封装体(n是2或更大的自然数)当中从下数的第一封装体到第(n-1)个封装体。
本申请包含2010年12月2日提交日本专利局的日本优先权专利申请JP2010-269105中公开的相关主题，其全部内容通过引用结合于此。
本领域的技术人员应当理解的是，在权利要求或其等同方案的范围内，根据设计需要和其他因素，可以进行各种修改、结合、部分结合和替换。

Claims (6)

1.一种半导体装置，包括：
基板；
半导体芯片，安装在该基板上；
封装体，通过采用绝缘材料密封该基板的上表面和该半导体芯片而被构造；
模制材料，暴露到该封装体的上表面；以及
引线，该引线的一端连接到该模制材料，该引线的另一端电连接到该基板，该引线从与该模制材料连接的连接部分到与该基板连接的连接部分由相同的材料一体形成，并且该引线与该模制材料连接的该连接部分暴露到该封装体的上表面。
2.根据权利要求1所述的半导体装置，还包括：
焊盘，形成在该基板的上表面上，并且该引线的该另一端与该焊盘电连接。
3.一种半导体装置，包括：
基板；
第一半导体芯片，安装在该基板上；
第一封装体，通过采用绝缘材料密封该基板的上表面和该第一半导体芯片而被构造；
模制材料，暴露到该第一封装体的上表面；
引线，该引线的一端连接到该模制材料，该引线的另一端电连接到该基板，该引线从与该模制材料连接的连接部分到与该基板连接的连接部分由相同的材料一体形成，并且该引线与该模制材料连接的连接部分暴露到该第一封装体的上表面；
第二半导体芯片；以及
第二封装体，通过采用绝缘材料密封该第二半导体芯片而被构造，并且该第二封装体电连接到暴露到该第一封装体的表面的该引线与该模制材料连接的连接部分。
4.根据权利要求3所述的半导体装置，还包括：
焊盘，形成在该基板的该上表面上，并且该引线的该另一端与该焊盘电连接。
5.根据权利要求3所述的半导体装置，还包括：
焊料球，形成在该第二半导体芯片的下表面上，并且电连接到暴露到该第一封装体的上表面的该引线与该模制材料连接的连接部分。
6.一种半导体装置的制造方法，包括：
将半导体芯片安装到基板上；
将一端连接到模制材料的引线的另一端的部分电连接到该基板，该引线从与该模制材料连接的连接部分到该另一端由相同的材料一体形成；以及
通过采用绝缘材料密封该基板的上表面、半导体芯片、该引线和该模制材料而形成封装体，以将该引线与该模制材料连接的该连接部分和该模制材料暴露到该封装体的上表面。
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