CN102479769A - 凸点和测试焊盘十字形排列的半导体器件 - Google Patents
凸点和测试焊盘十字形排列的半导体器件 Download PDFInfo
- Publication number
- CN102479769A CN102479769A CN2011103754115A CN201110375411A CN102479769A CN 102479769 A CN102479769 A CN 102479769A CN 2011103754115 A CN2011103754115 A CN 2011103754115A CN 201110375411 A CN201110375411 A CN 201110375411A CN 102479769 A CN102479769 A CN 102479769A
- Authority
- CN
- China
- Prior art keywords
- semiconductor device
- weld pad
- testing weld
- semiconductor substrate
- principal axis
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
- H01L2224/0346—Plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/036—Manufacturing methods by patterning a pre-deposited material
- H01L2224/03618—Manufacturing methods by patterning a pre-deposited material with selective exposure, development and removal of a photosensitive material, e.g. of a photosensitive conductive resin
- H01L2224/0362—Photolithography
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
- H01L2224/1146—Plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/116—Manufacturing methods by patterning a pre-deposited material
- H01L2224/1162—Manufacturing methods by patterning a pre-deposited material using masks
- H01L2224/11622—Photolithography
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13005—Structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13144—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13155—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/1412—Layout
- H01L2224/1413—Square or rectangular array
- H01L2224/14131—Square or rectangular array being uniform, i.e. having a uniform pitch across the array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/1412—Layout
- H01L2224/1413—Square or rectangular array
- H01L2224/14134—Square or rectangular array covering only portions of the surface to be connected
- H01L2224/14136—Covering only the central area of the surface to be connected, i.e. central arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
- H01L2224/81815—Reflow soldering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01024—Chromium [Cr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01055—Cesium [Cs]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01058—Cerium [Ce]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01073—Tantalum [Ta]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
一种半导体器件包括:半导体衬底;凸点,沿着半导体衬底的第一轴方向布置为多行;和测试焊盘,沿着与第一轴方向垂直的第二轴方向布置为一列或多列。凸点和测试焊盘在半导体衬底的中间部分中形成十字形。通过将凸点布置在半导体衬底的中间部分中,有助于在半导体堆叠的堆叠半导体器件之间形成物理连接,而无论芯片尺寸如何。
Description
相关申请的交叉引用
本申请要求享有于2010年11月24日在韩国知识产权局提交的韩国专利申请No.10-2010-0117521的权益,通过对其进行全文引用将其内容合并到本文中。
背景技术
根据本发明构思的实施例涉及半导体器件,更具体地涉及凸点和测试焊盘十字形排列的半导体器件,以及包括该半导体器件的电子系统。
电子工业已经发展出用户所需要的轻量化、小型化、高速、多功能以及高性能的电子设备。电子产品组装技术的一种类型是芯片规模封装或芯片尺寸封装技术。芯片规模封装可以减小半导体封装的厚度或尺寸。如果对芯片规模封装的半导体器件进行堆叠以允许半导体器件之间物理接触而无论芯片尺寸如何,则可以将芯片规模封装的凸点(bump)布置在每个半导体器件的半导体衬底的中间部分。
发明内容
根据本发明构思的实施例提供了具有十字形布置的凸点和测试焊盘的半导体器件,以及包括该半导体器件的电子系统。
根据本发明构思的一个方面,提供了一种半导体器件,包括:半导体衬底;凸点,沿着半导体衬底的第一轴方向布置为多行;和测试焊盘,沿着与第一轴方向垂直的第二轴方向布置为至少一列,其中凸点和测试焊盘在半导体衬底的中间部分形成十字形。
测试焊盘的列可以在半导体衬底的第二轴方向上隔开。测试焊盘的列可以在第一方向上隔开预定距离,该预定距离对应于用于将凸点连接到测试焊盘的连接区域的宽度。
凸点在多行之间隔开与两行或更多行测试焊盘的区域的宽度对应的距离。凸点可以在多行之间隔开与六行凸点对应的距离。
多行凸点可以在第一轴方向上隔开测试焊盘列的区域的宽度。多行凸点可以在第二轴方向上隔开一定距离,该距离对应于用于将凸点连接到测试焊盘的连接区域的高度。
半导体器件还可以包括测试逻辑电路单元,该测试逻辑电路单元用于在测试时连接多个凸点和一个测试焊盘。
半导体衬底可以被凸点和测试焊盘所形成的十字形划分为多个象限,且集成电路可以布置在半导体衬底的每个象限上,使得每个象限上的每个集成电路可以作为独立的半导体器件操作。
根据本发明构思的另一方面,提供了一种电子系统,包括:半导体器件;和用于控制该半导体器件的处理器件,其中该半导体器件包括:半导体衬底;凸点,沿着半导体衬底的第一轴方向布置为多行;和测试焊盘,沿着与第一轴方向垂直的第二轴方向布置为至少一列,以及其中凸点和测试焊盘在半导体衬底的中间部分形成十字形。
半导体器件和处理器可以形成存储卡。
半导体器件和处理器可以形成半导体盘设备。
根据本发明构思的另一方面,提供了一种半导体器件,包括:半导体衬底的;凸点,沿着半导体衬底的第一轴方向布置为多行;和测试焊盘,沿着与第一轴方向垂直的第二轴方向布置为至少一列,其中测试焊盘的列在半导体衬底的第二轴方向上隔开所述多行凸点的宽度。
半导体器件还可以包括布置在半导体衬底的中间区域中的连接区域,在该中间区域处所述多行凸点会与所述至少一列测试焊盘交叠,其中,连接区域包括将一部分凸点一一对应地连接到一部分测试焊盘的连接。
凸点和测试焊盘可以在半导体衬底的中间部分中形成十字形,该十字形将半导体衬底划分为多个象限。集成电路可以布置在半导体衬底的每个象限上,其中每个象限上的每个集成电路作为独立的半导体器件操作。
附图说明
图1是根据本发明构思的多个实施例,通过将具有芯片规模封装的第一和第二半导体器件堆叠而形成的半导体封装的横截面图。
图2是根据本发明构思的实施例的具有芯片规模封装的半导体器件的平面图。
图3是布置在图2所示的半导体器件上的集成电路的框图。
图4是根据本发明构思的另一实施例的具有芯片规模封装的半导体器件的平面图。
图5是根据本发明构思的另一实施例的具有芯片规模封装的半导体器件的平面图。
图6是根据本发明构思的另一实施例的具有芯片规模封装的半导体器件的平面图。
图7是布置在图6所示的半导体器件上的存储器电路模块的框图。
图8是包括根据本发明构思的实施例的半导体器件的电子系统示例的框图;
图9是采用根据本发明构思的实施例的半导体器件的存储系统示例的框图。
图10是采用根据本发明构思的实施例的半导体器件的存储系统另一示例的框图。
图11是包括根据本发明构思的实施例的半导体器件的计算机系统的框图。
具体实施方式
下面将参照附图更全面地描述本发明构思的实施例,在附图中示出了根据本发明构思的示例性实施例。但是,本发明构思的实施例可以表现为多种不同的形式,并且不应解释为局限于本文中阐述的这些示例性实施例。在附图中,相同的附图标记表示相同的元件,并且为了清楚的说明可以夸大元件的尺寸或厚度。
芯片规模封装是一种新型封装,与典型的塑料封装相比具有许多区别特征。芯片规模封装的一个区别特征是其封装尺寸。根据国际半导体组织如联合电子器件工程委员会(Joint Electron Device EngineeringCouncil,JEDEC)或日本电子工业协会(Electronic IndustriesAssociation of Japan,EIAJ)规定的定义,芯片规模封装的封装尺寸在芯片尺寸的大约1.2倍以内。
芯片规模封装主要用于小型、便携产品中,例如数字摄像机、移动电话、手提电脑以及存储卡。例如,诸如数字信号处理器(DSP)、专用集成电路(ASIC)和微控制器之类的半导体器件可以装配在芯片规模封装中。此外,在其中装配有存储器件如动态随机存取存储器(DRAM)或闪存的芯片规模封装也变得更加常见。
但是,芯片规模封装具有较低的可靠性和较低的价格竞争力,这是因为例如芯片规模封装需要附加的制造装备和更大数量的原材料和辅助材料。
为了解决这些问题,开发了晶片级芯片规模封装。通常,半导体晶片可以通过如下方式来制造:执行常规的晶片制造工艺,然后对各个芯片进行分割以组装成封装。虽然封装组装工艺需要的设备和原材料及辅助材料与晶片制造工艺所需要的不同,但是,也可以将晶片级芯片规模封装作为完整产品来制造,而不需要从晶片分割出单独的芯片。也就是说,现有的制造设备或工艺也可以用于制造晶片级芯片规模封装。因此,可以使得制造晶片级芯片规模封装所需要的额外原材料和辅助材料最小化。
此外,已经提出了堆叠封装,其中晶片级芯片规模封装三维地堆叠。为了三维地堆叠晶片级芯片规模封装,在上层芯片规模封装与下层芯片规模封装之间需要电接触。为了形成这些电接触,在半导体芯片中形成孔,并在这些孔中形成穿透电极。
在形成穿透电极的一种方法中,孔形成到预定深度以穿透半导体芯片的芯片焊盘(pad)。然后,形成凸点下金属(UBM)层,在该UBM层中孔填充有金属。最后,对晶片的后表面进行研磨以暴露填充在孔中的金属层的端部。穿透电极的端部暴露在晶片的研磨后表面上,在堆叠封装时可以用作外部接触端子。
然后,可以在孔表面上形成金属凸点,以使得堆叠的芯片规模封装能够相互电接触。可以利用电镀方法在表面上形成UBM层,然后利用感光层执行光刻工艺来形成金属凸点。
之后,为了使得堆叠的芯片规模封装彼此电连接,可以在从形成在孔中的金属层向外露出的突起上熔化焊球。
图1是根据本发明构思的多个实施例,通过将具有芯片规模封装的第一半导体器件110和第二半导体器件120堆叠而形成的半导体封装10的横截面图。
参照图1,半导体封装10可以具有这样的结构,其中第一半导体器件110和第二半导体器件120堆叠在封装衬底100上。第一半导体器件110和第二半导体器件120可以通过微凸点114和124相互电接触。
第一半导体器件110和第二半导体器件120中的至少一个可以是存储器件。如随后所述,假定第一半导体器件110是存储器件。但是,实施例不限于此,并且第一半导体器件110也可以是逻辑器件。
第一半导体器件110可以具有半导体衬底112,该半导体衬底112具有面向封装衬底100的非有源表面113和面向上的有源表面111,从而,第一半导体器件110可以是以面朝上状态装配在封装衬底100上的存储器件。可以在第一半导体器件110的有源表面111上形成集成电路图案。微凸点114形成在第一半导体器件110的有源表面111中形成的芯片焊盘117上。芯片焊盘117电连接到集成电路图案。微凸点114可以形成为半球状或凸状,并且可以包括镍(Ni)、金(Au)、铜(Cu)或焊料合金。微凸点114可以具有大约8μm到大约50μm的直径。
第一半导体器件110的微凸点114可以形成在半导体衬底112的中间部分112c中。微凸点114电连接到第二半导体器件120,并实现内部输入/输出(I/O)。在示例性实施例中,内部I/O是指芯片之间的数据I/O,即第一半导体器件110与第二半导体器件120之间的数据I/O。
在第一半导体器件110中,半导体衬底112可以包括一个或多个穿透电极116以实现外部I/O。在示例性实施例中,外部I/O是指芯片与封装衬底之间的数据I/O,即第一半导体器件110与封装衬底100之间的数据I/O。
可以通过在半导体衬底112的中间部分112c中形成一个或多个通孔115,然后以导电材料填充通孔115,来形成穿透电极116。可以采用激光或干法刻蚀方法形成通孔115。
穿透电极116将第一半导体器件110电连接到封装衬底100,并可以具有例如少于或等于100um的精细间距,以形成宽的I/O总线。这样,穿透电极116可以应用在具有高电路密度的区域中。
由于通孔115具有用于形成穿透电极116的最小直径,因此通孔115可以在前端工艺中形成。精细间距的穿透电极116可以增大数据传输速度,从而可以提高半导体封装10的电气性质。
第二半导体器件120可以是装配在第一半导体器件110的有源表面111上的存储器件或逻辑器件。第二半导体器件120可以包括半导体衬底122,在半导体衬底122的中间部分中形成有微凸点124。第二半导体器件120可以通过微凸点124电连接到第一半导体器件110。第二半导体器件120的微凸点124可以电连接到第一半导体器件110的微凸点114。例如,第二半导体器件120也可以采用倒装法装配在第一半导体器件110上。
在示例性实施例中,第一半导体器件110和第二半导体器件120的微凸点114和124形成在半导体衬底112和122的中间部分中,从而即使在第一半导体器件110和第二半导体器件120具有不同的芯片尺寸时,也可以将堆叠的第一半导体器件110和第二半导体器件120进行电连接,如图1所示。也就是说,如果堆叠的半导体器件具有不同的芯片尺寸,可以将芯片规模封装的凸点布置在器件衬底的中间部分中,从而促进半导体器件之间的物理接触。
在其他示例性实施例中,第一半导体器件110和第二半导体器件120可以是具有相同尺寸的异类芯片或同类芯片。例如,如果第一半导体器件110和第二半导体器件120是用于形成宽I/O总线的同类存储器件,形成在半导体衬底112和122的中间部分中的微凸点114、124和穿透电极116可以相互连接到与宽I/O总线连接的集成电路。在这种情况下,彼此接触的微凸点114和124可以用作宽I/O球。
封装衬底100例如可以是印刷电路板(PCB)。封装衬底100可以通过穿透电极116和与穿透电极116接触的一个或多个体凸点(bulk bump)130电连接到第一半导体器件110。体凸点130比微凸点114具有更大的体积和高度。由于体凸点具有更大的尺寸,使用设置在半导体衬底112与封装衬底100之间的体凸点130可以增大第一半导体器件110的抗应力性,并可提高半导体封装10的机械耐久性。
图2是根据本发明构思的实施例的具有芯片规模封装的半导体器件110I的平面图。
参照图2,半导体器件110I可以用作图1中所示的第一半导体器件110。图2示出了半导体器件110I的半导体衬底112的有源表面111。下面将要参照图3描述的集成电路可以形成在半导体衬底112的有源表面111上。半导体器件110I包括多个微凸点114和多个测试焊盘210,所述多个微凸点114沿第一轴方向(例如x轴方向)平行布置在半导体衬底112的中间部分112c中,所述多个测试焊盘210布置为沿与半导体衬底112的第一轴方向垂直的第二轴方向(例如y轴方向)延伸的列。这样,微凸点114和测试焊盘210以十字形布置在半导体衬底112的中间部分中。
微凸点114在半导体衬底112的中间部分112c中布置为沿第一方向的多行和沿第二方向的多列。微凸点114例如可以布置为6行和50列。微凸点114可以电连接到集成电路。微凸点114可以是接收命令控制信号如行地址选通信号RAS、列地址选通信号CAS、写使能信号WE、复位信号RESET以及芯片选择信号CS的控制信号输入端子,接收时钟信号CLK的时钟信号端子,接收地址信号ADDR的地址信号端子,接收数据I/O信号如数据选通信号DQS、数据屏蔽信号DM和数据输入/输出信号DQ的数据I/O相关端子,接收测试相关信号如测试信号TEST、直接访问输入信号DA和直接访问输出信号DA(o)的测试相关端子,或者是接收电源信号如VDD1、VDD2、VDDQ、VSS和DQ地信号VSSQ的电源端子。
如果半导体器件110I是晶片级芯片规模封装的一部分,微凸点114可以用于对半导体器件110I执行探测测试。可以改变并测量参数值,以评估半导体器件110I的集成电路的性能。例如,可以测试输入电压、输出电压、电容和电流规格。如果半导体器件110I是存储器件,可以进行逻辑测试以测试数据可储存性、数据可恢复性和反应时间。
具有多个探针22的探测卡20可以对半导体器件110I进行探测测试。因此,探测卡20应该具有与微凸点114相同数量的探针22。可以通过使得探测卡20的探针22接触对应的微凸点114,来确定半导体器件110I是正常工作还是异常工作。例如,如果布置为6行、50列的微凸点114的数量是300,探针22的最大数量可以是300。
但是,由于微凸点114集中在半导体器件110I的中间部分112c中,要使探针22接触对应的微凸点114而不使探针22彼此接触,可能是具有挑战性的。此外,准备与微凸点114相同数量的探针22可能也是具有挑战性的。
为了解决上述问题,半导体器件110I的测试焊盘210可以沿与微凸点114垂直的方向布置成列。测试焊盘210可以与微凸点114一一对应,因而测试焊盘210的数量与微凸点114的数量可以相等。在这种情况下,由于测试焊盘210布置成列,半导体器件110I可能具有较大的尺寸。
为了减小半导体器件110I的芯片尺寸,测试焊盘210的数量可以少于微凸点114的数量。测试逻辑电路单元220可以布置在微凸点114与测试焊盘210之间,以连接微凸点114和测试焊盘210。例如,测试逻辑电路单元220可以是复用逻辑电路,其允许半导体器件110I基于施加到微凸点114的信号执行的操作与基于施加到某个测试焊盘210上的信号所执行的操作相同。
测试逻辑电路单元220可以具有例如与第一测试焊盘210a的连接230。如果半导体器件110I是存储器件,第一测试焊盘210a可以设置为测试半导体器件110I的读操作。在这种情况下,测试逻辑电路单元220可以操作为半导体器件110I的读控制电路。因此,第一测试焊盘210a可以对应于分配作为用于接收用来控制读操作的RAS、CAS、WE、RESET和CS信号的控制信号输入端子的5个微凸点114。
此外,测试逻辑电路单元220可以具有例如与第二测试焊盘210b的连接232。如果半导体器件110I是存储器件,第二测试焊盘210b可以设置为测试半导体器件110I的写操作。在这种情况下,测试逻辑电路单元220可以操作为半导体器件110I的写控制电路。因此,第二测试焊盘210b也可以对应于分配作为用于接收用来控制写操作的RAS、CAS、WE、RESET和CS信号的控制信号输入端子的5个微凸点114。
这样,测试焊盘210的总数量可以少于微凸点114的数量。
此外,预定的微凸点114a可以对应于测试焊盘210之一。例如,微凸点114a可以具有与相邻测试焊盘210c的连接234。在这种情况下,可以预期由测试焊盘210c所测试的参数(例如定时参数)与通过微凸点114a获取的参数相同。也就是说,在微凸点114a与测试焊盘210c之间可以存在相关性。
由于微凸点114和测试焊盘210在半导体衬底112的中间部分中的十字形配置,半导体衬底112可以划分为第一到第四象限240、242、244和246。半导体器件110I的集成电路可以布置在第一到第四象限240、242、244和246上。如果半导体器件110I是如图3所示的存储器件,则图3中所示的存储单元阵列310的各个部件(例如行译码器、列译码器、读出放大器和数据放大器),控制电路320,地址缓冲器330和数据缓冲器340可以分别布置在第一到第四象限240、242、244和246上。可选地,存储单元阵列310、控制电路320、地址缓冲器330和数据缓冲器340都可以布置在第一到第四象限240、242、244和246的每一个上。这样,可以增大布置在第一到第四象限240、242、244和246上的集成电路的利用率。
测试焊盘210可以由下述材料形成:金(Au)、铝(Al)、铬(Cr)、镍(Ni)、钨(W)、钛(Ti)、钽(Ta)、钨化钛(TiW)、铬化镍(NiCr)、氮化铝(AlNx)、氮化钛(TiNx)、氮化钛铝(TiAlxNy)、氮化钽(TaNx)、硅化钨(WSix)、硅化钛(TiSix)、硅化钴(CoSix),或者他们的组合。测试焊盘210可以由比用于形成半导体衬底112的硅更柔性的材料形成。
当对半导体器件110I执行探测测试时,测试焊盘210可能被接触测试焊盘210的探针22划破。从测试焊盘210划出的颗粒物可能留在半导体衬底112上,进而可能降低半导体器件110I的可靠性。
但是,由于测试焊盘210与微凸点114a隔开,并且由于探针22沿着与微凸点114的布置方向(例如,x轴方向)平行的方向(例如,x轴方向)接触测试焊盘210,因而测试焊盘210的颗粒物可以与微凸点114的区域隔开。这样,颗粒物不会落在微凸点114之间,从而防止了半导体器件110I可靠性的降低。
图4是根据本发明构思的另一实施例的具有芯片规模封装的半导体器件110II的平面图。
参照图4,半导体器件110II可以用作图1中所示的第一半导体器件110。除了半导体器件110II的多个测试焊盘410布置成两列之外,半导体器件110II与图2中所示的半导体器件110I类似。
测试焊盘410在半导体器件110II的中间部分布置成沿着y轴方向平行延伸的相邻两列。虽然测试焊盘410在图4中布置为两列,但是测试焊盘410的配置不限于此,例如,测试焊盘也可以布置为更多列,例如三列或四列。由于测试焊盘410布置为相邻的两列,相比于其中测试焊盘210布置为单列的半导体器件110I的芯片尺寸来说,半导体器件110II的芯片尺寸可以减小。
图4示出了半导体器件110II的半导体衬底412的有源表面411。图3所示的集成电路可以形成在半导体衬底412的有源表面411上。多个微凸点414在半导体衬底412的中间部分412c布置成多行和多列。微凸点414和布置成两列的测试焊盘410在半导体衬底412的中间部分中布置为十字形。由于微凸点414和测试焊盘410在半导体衬底412的中间部分处的十字形配置,半导体衬底412可以划分为第一到第四象限440、442、444和446。半导体器件110II的集成电路可以布置在半导体衬底412的第一到第四象限440、442、444和446上。
测试焊盘410可以与微凸点414一一对应。例如,微凸点414a可以具有与相邻测试焊盘410c的连接434。可以预期,由测试焊盘410c所测试的参数(例如定时参数)与通过微凸点414a获取的参数相同。也就是说,在微凸点414a与测试焊盘410c之间可以存在相关性。
利用测试逻辑电路单元420,每个测试焊盘410可以与多个微凸点414对应。测试逻辑电路单元420可以是复用逻辑电路,其允许半导体器件110II基于施加到微凸点414的信号执行的操作与基于施加到某个测试焊盘410上的信号所执行的操作相同。
测试逻辑电路单元420可以具有例如与第一测试焊盘410a的连接430。如果半导体器件110II是存储器件,第一测试焊盘410a可以设置为测试半导体器件110II的读操作。在这种情况下,测试逻辑电路单元420可以操作为半导体器件110II的读控制电路。因此,第一测试焊盘410a可以对应于分配作为用于接收用来控制读操作的RAS、CAS、WE、RESET和CS信号的控制信号输入端子的5个微凸点414。
此外,测试逻辑电路单元420可以具有例如与第二测试焊盘410b的连接432。如果半导体器件110II是存储器件,第二测试焊盘410b可以设置为测试半导体器件110II的写操作。在这种情况下,测试逻辑电路单元420可以操作为半导体器件110II的写控制电路。因此,第二测试焊盘410b也可以对应于分配作为用于接收用来控制写操作的RAS、CAS、WE、RESET和CS信号的控制信号输入端子的5个微凸点414。因此,测试焊盘410的总数量可以少于微凸点414的数量。
图5是根据本发明构思的另一实施例的具有芯片规模封装的半导体器件110III的平面图。
参照图5,半导体器件110III可以用作图1中所示的第一半导体器件110。半导体器件110III与图4中所示的半导体器件110II类似,除了半导体器件110III的多个测试焊盘510布置为沿着y轴方向平行延伸的两列,该两列隔开预定距离510s,并且多个微凸点514隔开测试焊盘510区域的宽度510w。
在半导体器件110III中,微凸点514和测试焊盘510可以十字形布置在半导体衬底512的中间部分中。微凸点514在半导体衬底512的中间部分512c中布置成形成为两组的多行和多列,该两组沿着一个轴方向(例如x轴方向)隔开测试焊盘510区域的宽度510w。测试焊盘510可以布置为两列的两组,该两组沿着x轴方向可以隔开距离510s,沿着y轴方向可以隔开微凸点514区域的宽度514w。尽管在图5中测试焊盘510布置为两列,但是测试焊盘510的配置不限于此,并且可以包括更多列,例如隔开距离510s的3列或4列。
微凸点514在y轴方向上隔开且测试焊盘510在x轴方向上隔开的区域可以位于半导体衬底512的中间区域500处。半导体衬底512的中间区域500可以是微凸点514和测试510区域彼此交叠的区域。半导体衬底512的中间区域500可以用作具有连接的连接区域,这些连接将一部分微凸点514a至514h一一对应的连接到一部分测试焊盘510a至510h。
例如,微凸点514a可以具有与测试焊盘510a的电连接534a。微凸点514b可以具有与测试焊盘510b的电连接534b。微凸点514c可以具有与测试焊盘510c的电连接534c。微凸点514d可以具有与测试焊盘510d的电连接534d。通过这种方式,微凸点514e到514h可以分别具有与测试焊盘510e到510h的电连接534e到534h。
如图5所示,微凸点514a到514h和测试焊盘510a到510h可以布置为与半导体衬底512的中间区域500相邻。可以预期,由测试焊盘510a到510h所测试的参数(例如定时参数)与通过微凸点514a到514h获取的参数相同。这样,在微凸点514a到514h与测试焊盘510a到510h之间可以存在相关性。
图5示出了半导体器件110III的半导体衬底512的有源表面511。图3所示的集成电路可以形成在半导体衬底512的有源表面511上。隔开的微凸点514和两列隔开的测试焊盘510可以在半导体器件110III中半导体衬底512的中间部分中布置为十字形。由于微凸点514和测试焊盘510在半导体衬底512的中间部分中的十字形配置,半导体衬底512可以划分为第一到第四象限540、542、544和546。半导体器件110III的集成电路可以布置在半导体衬底512的第一到第四象限540、542、544和546上。
利用测试逻辑电路单元520,每个测试焊盘510可以与多个微凸点514对应。测试逻辑电路单元520可以是复用逻辑电路,其允许半导体器件110III基于施加到微凸点514的信号执行的操作与基于施加到某个测试焊盘510上的信号所执行的操作相同。
测试逻辑电路单元520可以具有例如与第一测试焊盘510i的连接530。如果半导体器件110III是存储器件,第一测试焊盘510i可以设置为测试半导体器件110III的读操作。在这种情况下,测试逻辑电路单元520可以操作为半导体器件110III的读控制电路,并且第一测试焊盘510i可以对应于分配作为用于接收用来控制读操作的RAS、CAS、WE、RESET和CS信号的控制信号输入端子的5个微凸点514。
此外,测试逻辑电路单元520可以具有例如与第二测试焊盘510j的连接532。如果半导体器件110III是存储器件,第二测试焊盘510j可以设置为测试半导体器件110III的写操作。在这种情况下,测试逻辑电路单元520可以操作为半导体器件110III的写控制电路。因此,第二测试焊盘510j也可以对应于分配作为用于接收用来控制写操作的RAS、CAS、WE、RESET和CS信号的控制信号输入端子的5个微凸点514。因此,测试焊盘510的总数量可以少于微凸点514的数量。
图6是根据本发明构思的另一实施例的具有芯片规模封装的半导体器件110IV的平面图。
参照图6,半导体器件110IV可以用作图1中所示的第一半导体器件110。半导体器件110OIV与图5所示的半导体器件110III类似,除了半导体器件110IV的多个微凸点614沿一个轴方向(例如x轴方向)隔开测试焊盘610区域的宽度610w,以及还沿着另一轴方向(例如y轴方向)隔开预定距离614s。
在半导体器件110IV中,微凸点614和测试焊盘610可以十字形布置在半导体衬底612的中间部分中。微凸点614可以布置为多行和多列,并且在半导体衬底612的中间部分612c处沿着x轴方向隔开测试焊盘610区域的宽度610w,以及沿着y轴方向隔开距离614s。微凸点614隔开的区域和测试焊盘610隔开的区域可以用作连接区域,在该连接区域微凸点614连接到测试焊盘610。距离614s可以是该连接区域在第二轴方向上的高度。
测试焊盘610可以布置为沿着x轴方向隔开预定距离610s以及沿着y轴方向隔开微凸点614区域的宽度614w的两列。尽管在图6中测试焊盘610布置为两列,但是测试焊盘610的配置不限于此,并且可以包括更多列,例如隔开距离610s的3列或4列。
微凸点614和测试焊盘610隔开的区域可以用作连接区域,该连接区域具有将一部分微凸点614a到614h一一对应的连接到一部分测试焊盘610a到610h的连接。例如,微凸点614a可以具有与测试焊盘610a的电连接634a。微凸点614b可以具有与测试焊盘610b的电连接634b。微凸点614c可以具有与测试焊盘610c的电连接634c。微凸点614d可以具有与测试焊盘610d的电连接634d。通过这种方式,微凸点614e到614h可以分别具有与测试焊盘610e到610h的电连接634e到634h。
图6示出了半导体器件110IV的半导体衬底612的有源表面611。图3所示的集成电路可以形成在半导体衬底612的有源表面611上。隔开的微凸点614和两列隔开的测试焊盘610可以在半导体器件110IV中半导体衬底612的中间部分中布置为十字形。由于微凸点614和测试焊盘610在半导体衬底612的中间部分中的十字形配置,半导体衬底612可以划分为第一到第四象限640、642、644和646。半导体器件110IV的集成电路可以布置在半导体衬底612的第一到第四象限640、642、644和646上。
可以这样的方式布置集成电路,使得半导体衬底612的第一到第四象限640、642、644和646中的每个象限可以作为独立的半导体器件工作。例如,布置在第一象限640中的集成电路,以及连接到该第一象限640的多个微凸点614UL和测试焊盘610UL可以作为一个独立的存储器件工作。布置在第二象限642中的集成电路,以及连接到该第二象限642的多个微凸点614UR和测试焊盘610UR可以作为一个独立的存储器件工作。布置在第三象限644中的集成电路,以及连接到该第三象限644的多个微凸点614LL和测试焊盘610LL可以作为一个独立的存储器件工作。布置在第四象限646中的集成电路,以及连接到该第四象限646的多个微凸点614LR和测试焊盘610LR可以设计为一个独立的存储器件。也就是说,半导体器件110IV可以是利用4个独立的存储器件进行工作的4通道存储器件。
连接到第一象限640的微凸点614UL例如可以布置为6行和50列。连接到第二象限642的微凸点614UR例如可以布置为6行和50列。连接到第三象限644的微凸点614LL例如可以布置为6行和50列。连接到第四象限646的微凸点614LR例如可以布置为6行和50列。
微凸点614UL与微凸点614UR之间,以及微凸点614LL与微凸点614LR之间的距离610w可以是与6行微凸点614对应的距离。微凸点614UL与微凸点614LL之间,以及微凸点614UR与微凸点614LR之间的距离614s可以是与2行微凸点614对应的距离。
利用测试逻辑电路单元620UL,连接到第一象限640的测试焊盘610UL可以与微凸点614UL对应。测试逻辑电路单元620UL可以是复用逻辑电路,其允许第一象限640的存储器件基于施加到微凸点614UL的信号执行的操作与基于施加到某个测试焊盘610UL上的信号所执行的操作相同。
利用测试逻辑电路单元620UR,连接到第二象限642的测试焊盘610UR可以与微凸点614UR对应。测试逻辑电路单元620UR可以是复用逻辑电路,其允许第二象限642的存储器件基于施加到微凸点614UR的信号执行的操作与基于施加到某个测试焊盘610UR上的信号所执行的操作相同。
利用测试逻辑电路单元620LL,连接到第三象限644的测试焊盘610LL可以与微凸点614LL对应。测试逻辑电路单元620LL可以是复用逻辑电路,其允许第三象限644的存储器件基于施加到微凸点614LL的信号执行的操作与基于施加到某个测试焊盘610LL上的信号所执行的操作相同。
利用测试逻辑电路单元620LR,连接到第四象限646的测试焊盘610LR可以与微凸点614LR对应。测试逻辑电路单元620LR可以是复用逻辑电路,其允许第四象限646的存储器件基于施加到微凸点614LR的信号执行的操作与基于施加到某个测试焊盘610LR上的信号所执行的操作相同。
布置在第一到第四象限640、642、644和646上的4个独立通道存储器件各自均可以包括如图7所示的双倍数据率同步动态随机存取存储器(DDR-SDRAM)电路模块。例如,单通道存储器件可以是具有128比特数据I/O规范的高宽带宽I/O存储器件。
参照图7,单通道存储器件700可以包括具有动态随机存取存储器(DRAM)单元的存储单元阵列701,和用于驱动这些DRAM单元的多个电路模块。例如,当芯片选择信号CS从无效电平(例如,逻辑高电平)转变到激活电平(例如逻辑低电平)时,可以激活定时寄存器702。定时寄存器702可以接收外部生成的命令信号,例如时钟信号CLK、时钟使能信号CLE、芯片选择信号CS、行地址选通信号RAS、列地址选通信号CAS、写使能信号WE和数据输入/输出屏蔽信号DQM,并可以通过处理所接收的命令信号来生成多个内部命令信号,例如内部时钟使能信号LCKE、内部RAS命令信号LRAS、内部写使能命令信号LWE、内部CAS命令信号LCAS、内部刷新信号LCBR、LWCBR以及内部数据输入/输出屏蔽信号LDQM,用于控制电路模块。
由定时寄存器702生成的一些内部命令信号存储在编程寄存器704中。例如,有关数据输出的等待时间信息或突发长度信息可以存储在编程寄存器704中。存储在编程寄存器704中的内部命令信号可以提供给等待时间/突发长度控制单元706,该等待时间/突发长度控制单元706可以经由列缓冲器708向列译码器710,或者向输出缓冲器712,提供用于控制数据输出的等待时间或突发长度的控制信号。
地址寄存器720可以从外部源接收时钟信号CLK和地址信号ADD。可以通过行缓冲器722向行译码器724提供行地址信号,且可以通过列缓冲器708向列译码器710提供列地址信号。行缓冲器722还可以接收由刷新计数器响应于刷新命令LRAS和LCBR而生成的刷新地址信号,并且可以向行译码器724提供行地址信号和刷新地址信号之一。此外,地址寄存器720可以向存储体(bank)选择单元726提供用于选择存储体的存储体信号。
行译码器724可以对从行缓冲器722接收的行地址信号或刷新地址信号译码,并可以激活存储单元阵列701的字线。列译码器710可以对列地址信号译码,并可以选择存储单元阵列701的位线。例如,可以把列选择线应用于半导体存储器件700,从而可以通过列选择线执行选择操作。
读出放大器730可以对由行译码器714和列译码器710选择的存储单元的数据进行放大,并且可以将放大的数据提供给输出缓冲器712,该输出缓冲器712可以输出放大的数据DQi。要在数据单元中记录的数据可以通过数据输入寄存器732提供给存储单元阵列701,I/O控制器734可以响应于从定时寄存器702接收的内部命令信号LWE和LDQM,控制数据输入寄存器732的数据传输。
图8是包括根据本发明构思的实施例的半导体器件110的电子系统800的框图。
参照图8,电子系统800包括输入器件810、输出器件820、处理器件830和半导体器件110。处理器件830可以使用相应的接口,控制输入器件810、输出器件820和半导体器件110。处理器件830可以是微处理器、数字信号处理器、微控制器或任何其它执行类似功能的逻辑器件中的一种或多种。输入器件810和输出器件820可以包括小键盘、键盘、显示器件等中的至少一种。
半导体器件110可以包括存储器700。存储器700可以是易失性存储器件,例如图7所示的DDR-SDRAM;或者是非易失性存储器件,例如闪存。在半导体器件110中,微凸点和测试焊盘可以在半导体衬底的中间部分中布置为十字形,并且测试焊盘可以布置为一列或多列。此外,在半导体器件110中,布置为多列的测试焊盘可以隔开预定距离,并可以连接到微凸点,并且微凸点可以隔开与隔开的测试焊盘区域的宽度对应的距离。此外,在半导体器件110中,微凸点可以沿着半导体器件110的第一轴方向隔开与第一预定数量行的微凸点对应的距离,以及沿着与第一轴方向垂直的第二轴方向隔开与第二预定数量行的微凸点对应的距离,其中第二预定数量小于第一预定数量。因此,在设置微凸点的区域中可以存在没有微凸点的十字形区域。
图9是采用根据本发明构思的实施例的半导体器件110的存储系统900的第一示例的框图。
参照图9,存储系统900可以包括接口单元910、控制器920和半导体器件110。接口单元910可以作为存储系统900和主机之间的接口。为了与主机接口连接,接口单元910可以执行与主机对应的数据交换协议。接口单元910可以利用多种接口协议之一与主机通信,例如通用串行总线(USB)、多媒体卡(MMC)、外设部件互连-高速(PCI-E)、小型计算机系统接口(SCSI)、串行连接SCSI(SAS)、串行高级技术附件(SATA)、并行高级技术附件(PATA)、增强小型磁盘接口(ESDI)或集成驱动电子设备(IDE)协议。
控制器920可以通过接口单元910从主机接收数据和地址。控制器920可以通过使用从主机接收的数据和地址来访问半导体器件110。控制器920可以将从半导体存储器件110读取的数据通过接口单元910传输给主机。
控制器920可以包括缓冲存储器921。缓冲存储器921可以对主机提供的写数据或从半导体器件110读取的数据进行临时存储。一旦接收到主机的读取请求,如果半导体器件110中存储的数据被缓存,则缓冲存储器921向主机直接提供缓存的数据以支持缓存功能。通常,主机的总线格式(例如SATA或SAS)的数据传输速度可以大于存储系统900中存储通道的数据传输速度。因此,如果主机具有更大的接口速度,则缓冲存储器921可以使由于速度差异导致的性能降低得到最小化。
在半导体器件110中,微凸点和测试焊盘可以十字形布置在半导体衬底的中间部分中。半导体器件110可以作为存储系统900的存储介质。例如,半导体器件110可以是阻性存储器件。可选地,半导体器件110可以是具有大存储容量的NAND型闪存。半导体器件110可以包括多个存储器件。作为存储介质,半导体器件110可以是参数随机存取存储器(PRAM)、磁阻随机存取存储器(MRAM)、阻性随机存取存储器(ReRAM)、铁电随机存取存储器(FRAM)、NOR闪存,或者是包括异类存储器件的存储系统。
图10是采用根据本发明构思的实施例的半导体器件110的存储系统1000的另一示例的框图。
参照图10,存储系统1000包括接口单元910、控制器1020和半导体器件110。如以上针对图9所述,接口单元910可以执行与主机对应的数据交换协议,以与主机接口连接。半导体器件110可以是包含闪存器件的半导体盘设备(SSD),其中微凸点和测试焊盘可以十字形布置在半导体衬底的中间部分。存储系统1000可以是闪存系统。
控制器1020可以包括具有地址翻译表1022的缓冲存储器1021。控制器1020可以利用地址翻译表1022将从接口单元910提供的逻辑地址转换成物理地址。控制器1020可以利用所转换的物理地址来访问半导体器件110。
图9和10中所示的存储系统900和1000均可以装配在数据处理设备例如个人数字助理(PDA)、便携电脑、web平板、数码相机、便携媒体播放器(PMP)、移动电话、无线电话或手提式电脑中。存储系统900和1000均可以是多媒体卡(MMC)、安全数字(SD)卡、微SD卡、存储棒、识别(ID)卡、个人计算机存储卡国际协会(PCMCIA)卡、芯片卡、通用串行总线(USB)卡、智能卡或紧凑闪存(CF)卡。
图11是包括根据本发明构思的实施例的半导体器件110的计算机系统1100的框图。
参照图11,计算机系统1100可以包括电连接到系统总线1150的中央处理单元(CPU)1110、用户接口1120、存储器1130和调制解调器1140(例如基带芯片组)。用户接口1120可以是向通信网络传输数据或者从通信网络接收数据的接口。用户接口1120可以是有线或无线设备,并且可以包括天线或有线或无线收发机。由用户接口1120或调制解调器1140提供的数据,或者由CPU1110处理的数据,可以存储在存储器1130中。
存储器1130可以包括易失性存储器件(例如DRAM)和/或非易失性存储器件(例如闪存)。存储器1130可以是DRAM、PRAM、MRAM、ReRAM、FRAM、NOR闪存、NAND闪存,或者是融合闪存,例如包括SRAM缓冲器、NAND闪存和NOR接口逻辑电路的存储器,其中微凸点和测试焊盘以十字形布置在半导体衬底的中间部分中。
如果计算机系统1100是移动设备,则可以包括用于提供计算机系统1100的工作电压的电池(未示出)。尽管在图11中并未示出,但是计算机系统1100例如可以进一步包括应用芯片组、摄像图像处理器(CIP)以及I/O设备。
如果计算机系统1100是无线通信设备,该计算机系统1100可以应用在通信系统例如码分多址(CDMA)设备、全球移动通信系统(GSM)设备、北美多址(NADC)设备或CDMA2000设备中。
虽然已经参照示例性实施例详细示出并描述了本发明构思的实施例,但是应该理解,可以在形式和细节上对其进行多种改变,而不会偏离所附权利要求的精神和范围。
Claims (19)
1.一种半导体器件,包括:
半导体衬底;
凸点,沿着半导体衬底的第一轴方向布置为多行;以及
测试焊盘,沿着与第一轴方向垂直的第二轴方向布置为至少一列,
其中凸点和测试焊盘在半导体衬底的中间部分中形成十字形。
2.根据权利要求1所述的半导体器件,其中测试焊盘的列在半导体衬底的第二轴方向上隔开所述多行凸点的宽度。
3.根据权利要求2所述的半导体器件,其中测试焊盘沿着半导体衬底的第二轴方向布置为两列或更多列。
4.根据权利要求3所述的半导体器件,其中测试焊盘的列在第一方向上隔开预定距离,该预定距离对应于用于将凸点连接到测试焊盘的连接区域的宽度。
5.根据权利要求4所述的半导体器件,其中所述多行凸点在第一轴方向上隔开所述两列或更多列测试焊盘的区域的宽度。
6.根据权利要求5所述的半导体器件,其中所述多行凸点在第二轴方向上隔开预定距离,该预定距离对应于用于将凸点连接到测试焊盘的连接区域的高度。
7.根据权利要求6所述的半导体器件,其中连接区域包括将一部分凸点一一对应地连接到一部分测试焊盘的连接。
8.根据权利要求1所述的半导体器件,还包括测试逻辑电路单元,该测试逻辑电路单元用于在测试时连接多个凸点和一个测试焊盘。
9.根据权利要求1所述的半导体器件,其中半导体衬底被微凸点和测试焊盘所形成的十字形划分为多个象限,以及集成电路布置在半导体衬底的每个象限上,其中每个象限上的每个集成电路作为独立的半导体器件操作。
10.一种电子系统,包括:
半导体器件;和
处理器件,用于控制所述半导体器件,
其中所述半导体器件包括:
半导体衬底;
凸点,沿着半导体衬底的第一轴方向布置为多行;和
测试焊盘,沿着与第一轴方向垂直的第二轴方向布置为至少一列,以及
其中凸点和测试焊盘在半导体衬底的中间部分中形成十字形。
11.根据权利要求10所述的电子系统,其中凸点的行在第二轴方向上隔开与预定数量行的凸点对应的距离。
12.根据权利要求11所述的电子系统,其中凸点在第一轴方向上隔开与所述至少一列测试焊盘的宽度对应的距离。
13.根据权利要求12所述的电子系统,其中测试焊盘的列在半导体衬底的第二轴方向上隔开所述多行凸点的宽度。
14.根据权利要求13所述的电子系统,其中测试焊盘布置为两列或更多列,以及测试焊盘的列在第一方向上隔开预定距离,该预定距离对应于用于将凸点连接到测试焊盘的连接区域的宽度。
15.一种半导体器件,包括:
半导体衬底;
凸点,沿着半导体衬底的第一轴方向布置为多行;和
测试焊盘,沿着与第一轴方向垂直的第二轴方向布置为至少一列,
其中测试焊盘的列在半导体衬底的第二轴方向上隔开所述多行凸点的宽度。
16.根据权利要求15所述的半导体器件,还包括:
布置在半导体衬底的中间区域中的连接区域,在该中间区域处所述多行凸点与所述至少一列测试焊盘交叠,
其中,连接区域包括将一部分凸点一一对应地连接到一部分测试焊盘的连接。
17.根据权利要求16所述的半导体器件,其中所述多行凸点在第一轴方向上隔开连接区域的宽度。
18.根据权利要求15所述的半导体器件,还包括两列或更多列测试焊盘,其中测试焊盘的列在第一轴方向上隔开。
19.根据权利要求15所述的半导体器件,其中凸点和测试焊盘在半导体衬底的中间部分中形成十字形,该十字形将半导体衬底划分为多个象限,以及该半导体器件还包括布置在半导体衬底的每个象限上的集成电路,其中每个象限上的每个集成电路作为独立的半导体器件操作。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020100117521A KR20120056018A (ko) | 2010-11-24 | 2010-11-24 | 범프들과 테스트 패드들이 십자 모양으로 배열되는 반도체 장치 |
KR10-2010-0117521 | 2010-11-24 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN102479769A true CN102479769A (zh) | 2012-05-30 |
Family
ID=46021518
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2011103754115A Pending CN102479769A (zh) | 2010-11-24 | 2011-11-23 | 凸点和测试焊盘十字形排列的半导体器件 |
Country Status (4)
Country | Link |
---|---|
US (1) | US20120126840A1 (zh) |
KR (1) | KR20120056018A (zh) |
CN (1) | CN102479769A (zh) |
DE (1) | DE102011086806A1 (zh) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105702298A (zh) * | 2014-08-28 | 2016-06-22 | 爱思开海力士有限公司 | 半导体器件和包括所述半导体器件的半导体系统 |
CN105793928A (zh) * | 2013-12-02 | 2016-07-20 | 硅存储技术公司 | 具有可配置引脚的三维nor闪存存储器系统 |
CN107591174A (zh) * | 2016-07-08 | 2018-01-16 | 三星电子株式会社 | 半导体存储器封装、存储器件和半导体存储器系统 |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8797057B2 (en) * | 2011-02-11 | 2014-08-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Testing of semiconductor chips with microbumps |
US9817029B2 (en) | 2011-12-07 | 2017-11-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Test probing structure |
WO2013101085A1 (en) | 2011-12-29 | 2013-07-04 | Intel Corporation | Secure key storage using physically unclonable functions |
US8928347B2 (en) * | 2012-09-28 | 2015-01-06 | Intel Corporation | Integrated circuits having accessible and inaccessible physically unclonable functions |
US9472284B2 (en) * | 2012-11-19 | 2016-10-18 | Silicon Storage Technology, Inc. | Three-dimensional flash memory system |
US8938792B2 (en) | 2012-12-28 | 2015-01-20 | Intel Corporation | Device authentication using a physically unclonable functions based key generation system |
US9224695B2 (en) * | 2013-02-28 | 2015-12-29 | Infineon Technologies Ag | Chip arrangement and a method for manufacturing a chip arrangement |
WO2014175057A1 (ja) * | 2013-04-23 | 2014-10-30 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置 |
KR20150037055A (ko) * | 2013-09-30 | 2015-04-08 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치 |
US20150364454A1 (en) * | 2014-06-13 | 2015-12-17 | Apple Inc. | Reconfigured wide i/o memory modules and package architectures using same |
KR20160025957A (ko) * | 2014-08-28 | 2016-03-09 | 에스케이하이닉스 주식회사 | 집적회로 |
CN111370054A (zh) * | 2018-12-26 | 2020-07-03 | 华为技术有限公司 | 一种存储卡的测试系统 |
KR20210096871A (ko) * | 2020-01-29 | 2021-08-06 | 에스케이하이닉스 주식회사 | 마이크로 범프를 구비한 반도체 장치 및 그의 테스트 방법 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3434398B2 (ja) * | 1995-11-28 | 2003-08-04 | 三菱電機株式会社 | 半導体装置 |
US6590901B1 (en) * | 1998-04-01 | 2003-07-08 | Mosaid Technologies, Inc. | Method and apparatus for providing a packet buffer random access memory |
JP2001223324A (ja) * | 2000-02-10 | 2001-08-17 | Mitsubishi Electric Corp | 半導体装置 |
US7132841B1 (en) * | 2000-06-06 | 2006-11-07 | International Business Machines Corporation | Carrier for test, burn-in, and first level packaging |
US7061263B1 (en) * | 2001-11-15 | 2006-06-13 | Inapac Technology, Inc. | Layout and use of bond pads and probe pads for testing of integrated circuits devices |
SG121707A1 (en) * | 2002-03-04 | 2006-05-26 | Micron Technology Inc | Method and apparatus for flip-chip packaging providing testing capability |
US20070109831A1 (en) * | 2005-11-15 | 2007-05-17 | Siva Raghuram | Semiconductor product and method for forming a semiconductor product |
JP4910512B2 (ja) * | 2006-06-30 | 2012-04-04 | 富士通セミコンダクター株式会社 | 半導体装置および半導体装置の製造方法 |
JP5006640B2 (ja) * | 2006-12-22 | 2012-08-22 | 新光電気工業株式会社 | 半導体装置の製造方法 |
KR100794313B1 (ko) * | 2006-12-27 | 2008-01-11 | 삼성전자주식회사 | 범프 패드를 포함한 반도체 메모리 장치 및 그것의 테스트방법 |
JP2009200101A (ja) * | 2008-02-19 | 2009-09-03 | Liquid Design Systems:Kk | 半導体チップ及び半導体装置 |
US8115321B2 (en) * | 2009-04-30 | 2012-02-14 | Lsi Corporation | Separate probe and bond regions of an integrated circuit |
US8396682B2 (en) * | 2009-10-16 | 2013-03-12 | Samsung Electronics Co., Ltd. | Semiconductor device |
US8796863B2 (en) * | 2010-02-09 | 2014-08-05 | Samsung Electronics Co., Ltd. | Semiconductor memory devices and semiconductor packages |
KR101201860B1 (ko) * | 2010-10-29 | 2012-11-15 | 에스케이하이닉스 주식회사 | 반도체 장치와 그 테스트 방법 및 제조방법 |
KR20120119960A (ko) * | 2011-04-21 | 2012-11-01 | 삼성전자주식회사 | 마이크로 범프 연결성을 테스트할 수 있는 반도체 장치 |
-
2010
- 2010-11-24 KR KR1020100117521A patent/KR20120056018A/ko not_active Application Discontinuation
-
2011
- 2011-09-22 US US13/240,738 patent/US20120126840A1/en not_active Abandoned
- 2011-11-22 DE DE102011086806A patent/DE102011086806A1/de not_active Withdrawn
- 2011-11-23 CN CN2011103754115A patent/CN102479769A/zh active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105793928A (zh) * | 2013-12-02 | 2016-07-20 | 硅存储技术公司 | 具有可配置引脚的三维nor闪存存储器系统 |
CN105702298A (zh) * | 2014-08-28 | 2016-06-22 | 爱思开海力士有限公司 | 半导体器件和包括所述半导体器件的半导体系统 |
CN105702298B (zh) * | 2014-08-28 | 2020-12-08 | 爱思开海力士有限公司 | 半导体器件和包括所述半导体器件的半导体系统 |
CN107591174A (zh) * | 2016-07-08 | 2018-01-16 | 三星电子株式会社 | 半导体存储器封装、存储器件和半导体存储器系统 |
CN107591174B (zh) * | 2016-07-08 | 2021-08-31 | 三星电子株式会社 | 半导体存储器封装、存储器件和半导体存储器系统 |
Also Published As
Publication number | Publication date |
---|---|
US20120126840A1 (en) | 2012-05-24 |
DE102011086806A1 (de) | 2012-05-24 |
KR20120056018A (ko) | 2012-06-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN102479769A (zh) | 凸点和测试焊盘十字形排列的半导体器件 | |
US8799730B2 (en) | Semiconductor devices and semiconductor packages | |
JP5448698B2 (ja) | 半導体装置及びそのテスト方法 | |
JP5697898B2 (ja) | 半導体装置及びその製造方法 | |
US8648429B2 (en) | Semiconductor having chip stack, semiconductor system, and method of fabricating the semiconductor apparatus | |
US8138610B2 (en) | Multi-chip package with interconnected stacked chips | |
US9251863B2 (en) | Multi channel semiconductor memory device and semiconductor device including the same | |
US8953394B2 (en) | Semiconductor device capable of operating in both a wide input/output mode and a high-bandwidth mode | |
JP5559507B2 (ja) | 半導体装置及びこれを備える情報処理システム | |
US8495437B2 (en) | Semiconductor memory device | |
US8547775B2 (en) | Semiconductor memory device and information processing system including the same | |
JP2012209497A (ja) | 半導体装置 | |
US11798917B2 (en) | Stack package including core die stacked over a controller die | |
KR20120118538A (ko) | 멀티 칩 패키지, 이의 제조 방법, 및 멀티 칩 패키지를 포함하는 메모리 시스템 | |
JP2015502652A5 (zh) | ||
US20130088838A1 (en) | Die package, method of manufacturing the same, and systems including the same | |
US11502051B2 (en) | Semiconductor chip including through electrode, and semiconductor package including the same | |
US11538506B2 (en) | Semiconductor device and semiconductor package including the semiconductor device | |
US8861159B2 (en) | Semiconductor device and systems including the same | |
US11450682B2 (en) | Semiconductor memory device | |
US11594471B2 (en) | Semiconductor chip including through electrode, and semiconductor package including the same | |
US20220181288A1 (en) | Semiconductor package including a dualized signal wiring structure | |
JP2014096197A (ja) | 半導体装置及びそのテスト方法 | |
KR20220011558A (ko) | 반도체 소자, 및 그 반도체 소자를 구비한 반도체 패키지 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20120530 |