CN102437147A - 密节距小焊盘铜线键合双ic芯片堆叠封装件及其制备方法 - Google Patents

密节距小焊盘铜线键合双ic芯片堆叠封装件及其制备方法 Download PDF

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CN102437147A
CN102437147A CN2011104086309A CN201110408630A CN102437147A CN 102437147 A CN102437147 A CN 102437147A CN 2011104086309 A CN2011104086309 A CN 2011104086309A CN 201110408630 A CN201110408630 A CN 201110408630A CN 102437147 A CN102437147 A CN 102437147A
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pad
chip
bonding
gold goal
bronze medal
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CN2011104086309A
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CN102437147B (zh
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慕蔚
李习周
郭小伟
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Tianshui Huatian Technology Co Ltd
Huatian Technology Xian Co Ltd
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Tianshui Huatian Technology Co Ltd
Huatian Technology Xian Co Ltd
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Priority to CN201110408630.9A priority Critical patent/CN102437147B/zh
Publication of CN102437147A publication Critical patent/CN102437147A/zh
Priority to PCT/CN2012/082169 priority patent/WO2013082970A1/zh
Priority to US14/363,996 priority patent/US9312242B2/en
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Publication of CN102437147B publication Critical patent/CN102437147B/zh
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Abstract

密节距小焊盘铜线键合双IC芯片堆叠封装件，包括塑封体，塑封体内设有引线框架载体和框架引线内引脚，引线框架载体的上面固接有第一IC芯片，第一IC芯片上堆叠有第二IC芯片，第一IC芯片和第二IC芯片的上表面分别设置多个焊盘，所述多个焊盘组成平行设置的两列焊盘组，分别为第一焊盘组和第二焊盘组，每个焊盘上植有金球，每个金球上接一第一铜键合球，第二IC芯片与第一IC芯片之间在对应的金球上拱丝拉弧形成第三铜键合线。本发明的制备工艺为减薄、划片、上芯、压焊、塑封、后固化、切筋、电镀、打印、成形分离和包装。本发明封装件与制备方法避免了焊盘上产生弹坑、相邻焊点短路和容易碰伤前一根线而造成的塑封冲线开路的隐患。

Description

密节距小焊盘铜线键合双IC芯片堆叠封装件及其制备方法
技术领域
本发明属于电子信息自动化元器件制造技术领域，涉及一种IC芯片封装件，具体说是一种密节距小焊盘铜线键合双IC芯片堆叠封装件，本发明还涉及该封装件的制备方法。
背景技术
随着电子信息产业的高速发展，芯片制造业迈入了纳米时代，芯片制造的工艺尺寸从90nm缩小到45nm，再到30nm、13nm快速递进。芯片的几何尺寸也越来越小，由1.0mm×1.0mm到0.8mm×0.8mm、0.5mm×0.5mm、0.3mm×0.3mm，最小0.15mm×0.15mm，相应地，芯片制造中使用的焊盘节距也由120μm逐步缩小到100μm、70μm、60μm、50μm和45μm。划道也由100μm逐渐缩小到70μm、60μm、50μm和45μm。使得焊盘尺寸也由最初的100μm×100μm渐次缩小为70μm×70μm、55μm×55μm、最小为38μm×38μm。焊盘尺寸的变化给键合工艺带来了难题和巨大的挑战。
正常的球焊键合工艺中，焊球的直径大于/等于线径的2倍，小于线径的5倍为合格。一般金线焊球的直径可控制在2～2.3(倍) 线径，铜线焊球的直径可控制在2.5～ 3(倍) 线径。对于38μm×38μm的焊盘，相邻焊盘间距41μm～43μm，只能使用Φ15μm～Φ16μm的焊线，并且键合焊球的直径必须控制在37μm以内。那么金线无论Φ15μm（2.3×15=34.5＜37）或取上限16（16×2.3=36.8＜37）,均符合压焊要求。而铜线无论Φ15μm（取下限15×2.5=37.5＞37），还是16μm（取上限16×2.5=40＞37），都不符合压焊要求。并且从压焊质量检验的角度讲，相邻键合线间的空隙应等于2倍的焊线直径。实际上，去除线径，相邻焊线间空隙1.69～1.86倍线径，相邻两键合线间距也不能满足一般质量要求。但是，实践证明，随着焊线质量的提高、线径规格的增多，封装技术的发展和高密度封装形式及产品的增加，在保证塑封冲线率满足工艺要求的前提下，焊线与焊线间不短路，相邻引线间空隙大于1倍的线径也被行业公认可以满足焊线工艺要求。但对密节距小焊盘的键合而言，键合球的直径很难控制，稍不注意，键合球会超出焊盘，造成相邻焊点短路，导致产品报废。另外，由于线间距过小，打第二根线时会碰到前一根线，造成前一根线的损伤。所以说，节距≤43μm的密节距小焊盘（38μm×38μm）产品键合的最大难度是键合点焊球直径的控制和碰伤相邻焊线的问题。
发明内容
本发明为了解决现有节距≤43μm、38μm×38μm的密节距小焊盘IC芯片铜线键合中存在相邻焊点间短路和碰伤相邻焊线的问题，提供一种相邻焊点不易短路的密节距小焊盘铜线键合双IC芯片堆叠封装件，本发明的另一目的是提供一种上述封装件的制备方法，在键合过程中能够控制键合球的直径，并且能避免碰伤相邻焊线，实现多芯片堆叠键合封装。
本发明的技术问题采用下述技术方案解决：
一种密节距小焊盘铜线键合双IC芯片堆叠封装件，包括塑封体，塑封体内设有引线框架载体和框架引线内引脚，引线框架载体的上面固接有第一IC芯片，第一IC芯片上堆叠有第二IC芯片，所述第一IC芯片和第二IC芯片的上表面分别设置多个焊盘，所述多个焊盘组成平行设置的两列焊盘组， 分别为第一焊盘组和第二焊盘组，每个焊盘上植有金球，每个金球上接一第一铜键合球，所述第二IC芯片与第一IC芯片之间在对应的金球上拱丝拉弧形成第三铜键合线。
所述第一焊盘组和第二焊盘组间隔的焊盘上分别焊接有一个金球，所述第一焊盘组中的金球与第二焊盘组中的金球交错设置，每个金球上焊接一个第一铜键合球，每列焊盘组中未焊接金球的焊盘上分别焊接一个第二键合球，并在对应的框架引线内引脚上打一铜键合点，形成第二铜键合线。
所述每列焊盘组中相邻两焊盘之间留有空隙，焊盘的外形尺寸为 38μm×38μm，焊盘的节距为43μm。
所述第一铜键合球采用Φ15μm铜线制成，其直径为35μm～38μm。
所述第二铜键合球采用Φ15μm铜线制成，其直径为34μm～37μm。
所述金球的直径为30μm～36.8μm。
上述封装件按下述工艺步骤进行：
步骤1 ：减薄、划片
常规方法将晶圆减薄至210μm并划片；
步骤2 
a）一次上芯
 采用载体不外露的引线框架，将已减薄并划片的第一IC芯片固定在引线框架载体上，依次粘完所有第一IC芯片后，将第一IC芯片收料到传递盒；
b)二次上芯 
将粘完所有第一IC芯片的传递盒送到上芯机上料台，设备自动升到设定位置并送一条进轨道传递到机台中央，由轨道压板固定．在第一IC芯片上点上绝缘胶后，上芯机吸嘴吸附第一ＩＣ芯片放置在绝缘胶上，依次粘完所有第一IC芯片后收料到传递盒；
c) 烘烤
采用N2气流量25ml/min～30ml/min烘烤3小时，烘烤温度150℃；
步骤3： 压焊
a）在步骤1安装的第一IC芯片上表面平行设置两列焊盘组，该两列焊盘组分别由数量相同的焊盘组成，且两列焊盘组中的各焊盘之间互不接触，一列焊盘组中的焊盘与另一列焊盘组中的焊盘为一一对应，焊盘的各条边的边长为38μm×38μm，焊盘之间的节距为43μm，相邻两焊盘之间的空隙为5μm；
b) 植金球
将直径15μm的金线轴固定于压焊台上，将已粘第一IC芯片的引线框架载体送上轨道，预热至210℃后传送到压焊台，由轨道压板固定，在第二IC芯片和第一IC芯片间焊线的焊盘上分别植金球后，收料到传递盒；
c) 叠铜球及拱丝打点
将已植金球的堆叠封装半成品及传递盒送到铜线球焊键合台上，在压焊台上固定直径为15μm的铜线轴，穿好线后，将已植金球的引线框架载体传送到轨道上，预热至200℃后传送到压焊夹具上，通过轨道压板进行固定，在第二IC芯片上的每个金球上堆叠一个第一铜键合球，向上拱丝拉弧到第一IC芯片已植金球的焊盘上堆叠一个第一铜键合球，形成第三铜键合线； 
d) 不植金球的焊盘直接铜线键合
第二IC芯片和第一IC芯片上焊盘组中未植金球的每个焊盘上直接打第二键合球，并拱丝拉弧到与该焊盘相对应的引线框架内引脚上打一个铜焊点，形成第二铜键合线；
e）重复动作
依次将第二IC芯片和第一IC芯片上不植金球的每个焊盘上直接打一个第二键合球，并拱丝拉弧到与该焊盘相对应的引线框架内引脚上打一个铜焊点，形成第二铜键合线；
步骤4 对压焊后形成的半成品框架进行塑封，采用多段注塑防冲丝、冲丝小于8%防离层工艺，然后常规方法后固化、打印和冲切分离或切割分离（QFN/QFN），制得密节距小焊盘铜线键合IC芯片封装产品。
本发明封装件采用多重球焊方法，即在IC芯片焊盘上先植金球，并在金球上焊接铜键合球以及在其余的焊盘上直接焊接铜键合球的结构，避免了焊盘上产生弹坑和相邻焊点短路，既解决了密节距小焊盘高密度键合时容易碰伤前一根线而造成的塑封冲线开路的问题，又避免键合球直径过大造成相邻焊点短路的难题，结构简单合理，能用于多引脚封装。本发明还可以推广到其它高端封装形式，实现铜线代替金线键合，其键合强度优于金线，从而减少了塑封冲线率，提高了产品质量，节约了焊线成本，具有良好的经济效益和社会效益，本发明对于载体外露或载体不外露形式均可适用。
附图说明
图1为本发明结构示意图；
图2为每个芯片焊盘上植金球平面示意图；
图3为间隔焊盘上植金球平面示意图；
图4为间隔焊盘上植金球剖面示意图；
图5为本发明载体不外露示意图；
图6为本发明的芯片焊盘尺寸间距示意图。
具体实施方式
下面结合附图和具体实施方式对本发明进行详细说明。
一种密节距小焊盘铜线键合双IC芯片堆叠封装件，包括塑封体11，塑封体11内设有引线框架载体1和框架引线内引脚7，引线框架载体1的上面通过粘片胶2固接有第一IC芯片3，第一IC芯片3上通过绝缘胶12堆叠有第二IC芯片13，第一IC芯片3和第二IC芯片13的上表面分别设置多个焊盘4，组成平行设置的两列焊盘组， 分别为第一焊盘组和第二焊盘组，每个焊盘4上植有金球5，每个金球5上焊接一个第一铜键合球6。第二IC芯片13与第一IC芯片3之间在对应的金球5上拱丝拉弧形成第三铜键合线15。
本发明的第二种实施方式为：第一焊盘组和第二焊盘组在间隔的焊盘4上分别焊接有一个金球5，第一焊盘组中的金球5与第二焊盘组中的金球5交错设置，每个金球5上焊接一个第一铜键合球6，每列焊盘组中未焊接金球5的焊盘4上分别焊接一个第二键合球8，并在对应的框架引线内引脚7上打一铜焊点10，形成第二铜键合线14。上述各组件封装于封装体11内，形成电路整体，并对金球5、第一铜键合球6、第二铜键合球8、第二键合线14、第三铜键合线15和月牙形的铜焊点10起到保护作用。
本发明的金球5采用直径为15μm～16μm的金线制成。第一铜键合球6和第二铜键合球8采用直径为15μm的铜线制成。第一铜键合球6的直径为35μm～37μm，第二铜键合球8的直径为36μm～38μm。
下面结核实施例对本发明做进一步详细叙述：
步骤3：在各焊盘4上进行压焊：
a）将金线轴固定于压焊台上，然后穿入直径为15μm～16μm的金线9；
b）将粘结IC芯片3和上层IC芯片的引线框架载体1进行预热，使其温度达到200℃～210℃，由设备自动送到步骤a）中的压焊台夹具上，并通过轨道压板进行固定。在上层IC芯片和IC芯片3之间焊线的焊盘4上分别键合金球5，整条框架键合金球5后传送入传递盒。采用同样方法，完成整批产品的IC芯片3和上层IC芯片之间焊线的焊盘4上键合金球5任务；
c）将本批已完成键合金球5的传递盒送到铜丝键合机台上，该机台带有N2、H2混合体管道和专用气体喷嘴，机台衬底预热200℃～210℃。铜丝球焊机将传递盒自动升降到设定位置，自动送一条框架半成品到机台中央，先在上层IC芯片上已植金球5上堆叠第一铜键合球6，然后拱丝拉弧在相对IC芯片3上已植金球5上堆叠铜键合球6，形成第三铜键合线15，依次打完本批本批产品已植金球5的所有铜键合线15；最后在上层IC芯片和IC芯片3上未植金球的焊盘上打第二铜键合球8，并拱丝拉弧在相应内引脚上打一个月牙形的铜键合点10，形成第二铜键合线14。采用同样方法，完成本批所有产品的第二铜键合焊线14；
步骤4采用相关封装形式常规方法对压焊后形成的器件进行塑封，通过环保、普通各3组组合DOE对比试验，优选出环保、普通料和粘接胶组合材料，采用多段注塑防冲丝（冲丝小于8%）防离层工艺，然后按相关封装形式常规方法后固化、打印和冲切分离或切割分离，制成密节距小焊盘铜线键合IC芯片封装产品。
实施例1
1.       上芯
⑴ 减薄、划片
采用相关封装形式减薄通用设备和工艺，将晶圆减薄到210μm并划片；
⑵　一次上芯
 采用载体外露的eSOP、eMSOP、eTSSOP、eL/TQFP、QFN、DFN引线框架，将已减薄210μm并划片的第一IC芯片3用粘片胶2固定在引线框架载体1上，依次粘完所有第一IC芯片3后收料到传递盒；
⑶ 二次上芯
将粘完所有第一IC芯片3的传递盒送到上芯机进料处，自动升降到设定位置，并送一条进轨道传递到机台中央，由轨道压板固定．在第一IC芯片３上点上绝缘胶12后，上芯机自动吸嘴吸附第二IC芯片（芯片厚210μm）放置在绝缘胶12上。依次粘完所有第二IC芯片后收料到传递盒，上芯设备和工艺同相关封装形式常规产品生产；
⑷ 烘烤
使用ESPEC烘箱，采用N2气流量30ml/min烘烤3小时，烘烤温度150℃。
2. 压焊
⑴ 步骤1安装的第一IC芯片3的上表面平行设置两列焊盘组，该两列焊盘组分别由数量相同的焊盘4组成，且两列焊盘组中的各焊盘4之间互不接触，一列焊盘组中的焊盘4与另一列焊盘组中的焊盘4为一一对应，如图3所示，控制焊盘4的各条边a的边长为38μm×38μm，焊盘4之间的节距b为43μm，相邻两焊盘4之间的空隙c为5μm。
⑵ 植金球
将直径15μm的金线轴固定于压焊台上，穿好线后，将已粘IC芯片3的引线框架载体1自动传送到轨道上，预热至200℃后传送到压焊台，由轨道压板固定，在上层IC芯片和IC芯片3间焊线的焊盘4上分别植金球5后，收料到传递盒；
⑶ 叠铜球及拱丝打点
将已植金球5的堆叠封装半成品及传递盒送到铜线球焊键合台上，在压焊台上固定直径为15μm的铜线轴，穿好线后，将已植金球5的引线框架载体1自动传送到轨道上，预热至200℃后传送到压焊夹具上，通过轨道压板进行固定，在IC13上的金球5上堆叠一个第一铜键合球6，向上拱丝拉弧到IC3已植金球5的焊盘4上堆叠一个第一铜键合球6，形成第三铜键合线15； 
⑷ 不植金球的焊盘直接铜线键合
接着在上层IC芯片和IC芯片3上焊盘组中未植金球的每个焊盘4上直接打第二铜键合球8，并拱丝拉弧到与该焊盘4相对应的引线框架内引脚7上打一个月牙形的铜焊点10，形成第二铜键合线14。
（5）重复动作
依次将第二IC芯片13和第一IC芯片3上不植被金球5的每个焊盘4上直接打一个第二铜键合球8，并拱丝拉弧到与该焊盘4相对应的引线框架内引脚7上打一个月牙形的铜焊点10，形成第二铜键合线14。
3、对压焊后形成的半成品框架进行塑封，通过环保、普通各3组组合DOE对比试验，优选出环保、普通料和粘接胶组合方案，采用多段注塑防冲丝（冲丝小于8%）防离层工艺，然后按相关封装形式常规方法后固化、打印和冲切分离或切割分离（QFN/QFN），制得密节距小焊盘铜线键合IC芯片封装产品。
实施例2
1、上芯
⑴ 减薄、划片
采用相关封装形式减薄通用设备和工艺，将下层晶圆减薄到210μm，上层晶圆减薄到150μm并划片；
⑵　一次上芯
 采用载体外露的eSOP、eMSOP、eTSSOP、eL/TQFP、QFN、DFN引线框架，将已减薄210μm并划片的第一IC芯片3用导电胶2固定在上述引线框架载体1上，依次粘完所有第一IC芯片3后收料到传递盒；
⑶ 二次上芯
将粘完所有第一IC芯片3的传递盒送到上芯机进料处，自动升降到设定位置，并送一条进轨道传递到机台中央，由轨道压板固定．在第一IC芯片３上点上绝缘胶12后，设备自动吸嘴吸附第二IC芯片13（芯片厚150μm）放置在绝缘胶12上。依次粘完所有第二IC芯片13后收料到传递盒，上芯设备和工艺同相关封装形式常规产品生产；
⑷ 烘烤
使用ESPEC烘箱，采用N2气流量≥25ml/min烘烤3小时，烘烤温度150℃。
2. 压焊
⑴ 步骤1安装的第一IC芯片3的上表面已平行设置两列焊盘组（芯片制造），该两列焊盘组分别由数量相同的焊盘4组成，且两列焊盘组中的各焊盘4之间互不接触，一列焊盘组中的焊盘4与另一列焊盘组中的焊盘4为一一对应，如图3所示，控制焊盘4的各条边a的边长为38μm×38μm，焊盘4之间的节距b为43μm，相邻两焊盘4之间的空隙c为5μm。
⑵ 植金球
将直径15μm的金线轴固定于压焊台上，穿好线后，将已粘第一IC芯片3的引线框架载体1自动传送到轨道上，预热至200℃后传送到压焊台，由轨道压板固定，在第二IC芯片13和第一IC芯片3间焊线的焊盘4上分别植金球5后，收料到传递盒；
⑶ 叠铜球及拱丝打点
将已植金球5的堆叠封装半成品及传递盒送到铜线球焊键合台上，在压焊台上固定直径为15μm的铜线轴，穿好线后，将已植金球5的引线框架载体1自动传送到轨道上，预热至200℃后传送到压焊夹具上，通过轨道压板进行固定，在IC13上的金球5上堆叠一个第一铜键合球6，向上拱丝拉弧到IC3已植金球5的焊盘4上堆叠一个第一铜键合球6，形成第三铜键合线15； 
⑷ 不植金球的焊盘直接铜线键合
接着在第二IC芯片13和第一IC芯片3上的焊盘组中未植金球的每个焊盘4上直接打第二铜键合球8，并拱丝拉弧到与该焊盘4相对应的引线框架内引脚7上打一个月牙形的铜焊点10，形成第二铜键合线14。
（5）重复动作
第二铜键合球8，并拱丝拉弧到与该焊盘4相对应的引线框架内引脚7上打一个月牙形的铜焊点10，形成第二铜键合线14。
3、对压焊后形成的半成品框架进行塑封，通过环保、普通各3组组合DOE对比试验，优选出环保、普通料和粘接胶组合方案，采用多段注塑防冲丝（冲丝小于8%）防离层工艺，然后按相关封装形式常规方法后固化、打印和冲切分离或切割分离（QFN/QFN），制得密节距小焊盘铜线键合IC芯片封装产品。
实施例3
1.上芯
⑴ 减薄、划片
采用相关封装形式减薄通用设备和工艺，将晶圆减薄至210μm并划片；
⑵　一次上芯
采用载体不外露的SOP、MSOP、SSOP、TSSOP、QFP、L/TQFP、QFN、DFN引线框架，将已减薄210μm并划片的第一IC芯片3用绝缘胶固定在上述引线框架载体1上，依次粘完所有第一IC芯片3后收料到传递盒；
⑶ 二次上芯
将粘完所有第一IC芯片3的传递盒送到上芯机进料处，自动升降到位置，并送一条进轨道传递到机台中央，由轨道压板固定．在IC芯片３上点上绝缘胶12后，设备自动吸嘴吸附第二IC芯片放置在绝缘胶12上。依次粘完所有第二IC芯片后收料到传递盒，上芯设备和工艺同相关封装形式常规产品生产；
⑷ 烘烤
烘烤使用ESPEC烘箱，采用常规烘烤技术烘烤3小时，烘烤温度150℃。
2. 压焊
⑴ 在步骤1安装的第一IC芯片3的上表面平行设置两列焊盘组，该两列焊盘组分别由数量相同的焊盘4组成，且两列焊盘组中的各焊盘4之间互不接触，一列焊盘组中的焊盘4与另一列焊盘组中的焊盘4为一一对应，控制焊盘4的各条边a的边长为38μm×38μm，焊盘4之间的节距b为43μm，相邻两焊盘4之间的空隙c为5μm 。
⑵ 植金球
将直径15μm的金线轴固定于压焊台上，穿好线后，将已粘IC芯片3的引线框架载体1自动传送到轨道上，预热至210℃后传送到压焊台，由轨道压板固定，在第二IC芯片13和第一IC芯片3间焊线的焊盘4上分别植金球5后，收料到传递盒；
⑶ 叠铜球及拱丝打点
将已植金球5的堆叠封装半成品及传递盒送到时铜线球焊键合台上，在压焊台上固定直径为15μm的铜线轴，穿好线后，将已植金球5的引线框架载体1自动传送到轨道上，预热至200℃后传送到压焊夹具上，通过轨道压板进行固定，在每个金球5上堆叠一个第一铜键合球6，向上拱丝拉弧到IC3已植金球5的焊盘4上堆叠一个第一铜键合球6，形成第三铜键合线15； 
⑷ 不植金球的焊盘直接铜线键合
接着第二IC芯片和第一IC芯片3上焊盘组中未植金球5的每个焊盘4上直接打第二铜键合球8，并拱丝拉弧到与该焊盘4相对应的引线框架内引脚7上打一个月牙形的铜焊点10，形成第二铜键合线14。
（5）重复动作
依次将第二IC芯片13和第一IC芯片3上不植被金球的每个焊盘4上直接打一个第二铜键合球8，并拱丝拉弧到与该焊盘4相对应的引线框架内引脚7上打一个月牙形的铜焊点10，形成第二铜键合线14。
3、对压焊后形成的半成品框架进行塑封，通过环保、普通各3组组合DOE对比试验，优选出环保、普通料和粘接胶组合材料，采用多段注塑防冲丝（冲丝小于8%）防离层工艺，然后按相关封装形式常规方法后固化、打印和冲切分离或切割分离（QFN/QFN），制得密节距小焊盘铜线键合IC芯片封装产品。
实施例4
1、上芯
⑴ 减薄、划片
采用相关封装形式减薄通用设备和工艺，将下层晶圆减薄到210μm，上层晶圆减薄到150μm并划片；
⑵　一次上芯
 采用载体外露的eSOP、eMSOP、eTSSOP、eL/TQFP、QFN、DFN引线框架，将已减薄210μm并划片的IC芯片3用绝缘胶4固定在上述引线框架载体1上，依次粘完所有第一IC芯片3后收料到传递盒；
⑶ 二次上芯
将粘完所有第一IC芯片3的传递盒送到上芯机进料处，自动升降到设定位置，并送一条进轨道传递到机台中央，由轨道压板固定．在第一IC芯片３上点上绝缘胶12后，设备自动吸嘴吸附上层IC芯片（芯片厚150μm）放置在绝缘胶12上。依次粘完所有上层IC芯片后收料到传递盒，上芯设备和工艺同相关封装形式常规产品生产；
⑷ 烘烤
使用ESPEC烘箱，采用N2气流量≥25ml/min的防离层烘烤技术及温度曲线烘烤3小时，烘烤温度150℃。
2. 压焊
⑴ 步骤1安装的第一IC芯片3的上表面已平行设置两列焊盘组（芯片制造），该两列焊盘组分别由数量相同或不同的焊盘4组成，且两列焊盘组中的各焊盘4之间互不接触，一列焊盘组中的焊盘4与另一列焊盘组中的焊盘4为一一对应，如图3所示，控制焊盘4的各条边a的边长为38μm×38μm，焊盘4之间的节距b为43μm，相邻两焊盘4之间的空隙c为5μm，见图1。
⑵ 植金球
将直径15μm的金线轴固定于压焊台上，穿好线后，将已粘IC芯片3的引线框架载体1自动传送到轨道上，预热至200℃后传送到压焊台，由轨道压板固定，在上层IC芯片和IC芯片3间焊线的焊盘4上分别植金球5后，收料到传递盒；
⑶ 叠铜球及拱丝打点
将已植金球5的堆叠封装半成品及传递盒送到铜线球焊键合台上，在压焊台上固定直径为15μm的铜线轴，穿好线后，将已植金球5的引线框架载体1自动传送到轨道上，预热至200℃后传送到压焊夹具上，通过轨道压板进行固定，在IC13上的金球5上堆叠一个第一铜键合球6，向上拱丝拉弧到IC3已植金球5的焊盘4上堆叠一个第一铜键合球6，形成第三铜键合线15； 
⑷ 不植金球的焊盘直接铜线键合
接着在上层IC芯片和IC芯片3上焊盘组中未植金球的每个焊盘4上直接打第二铜键合球8，并拱丝拉弧到与该焊盘4相对应的引线框架内引脚7上打一个月牙形的铜焊点10，形成第二铜键合线14。
（5）重复动作
依次将上层IC芯片和IC芯片3上不植被金球5的每个焊盘4上直接打一个第二铜键合球8，并拱丝拉弧到与该焊盘4相对应的引线框架内引脚7上打一个月牙形的铜焊点10，形成第二铜键合线14。
3、对压焊后形成的半成品框架进行塑封，通过环保、普通各3组组合DOE对比试验，优选出环保、普通料和粘接胶组合方案，采用多段注塑防冲丝（冲丝小于8%）防离层工艺，然后按相关封装形式常规方法后固化、打印和冲切分离或切割分离（QFN/QFN），制得密节距小焊盘铜线键合IC芯片封装产品。
虽然结合优选实施例已经示出并描述了本发明，本领域技术人员可以人理解，在不违背所附权利要求限定的本发明的精神和范围的前提下可以进行修改和变换。

Claims (7)

1.一种密节距小焊盘铜线键合双IC芯片堆叠封装件，包括塑封体（11），塑封体（11）内设有引线框架载体（1）和框架引线内引脚（7），引线框架载体（1）的上面固接有第一IC芯片（3），第一IC芯片（3）上堆叠有第二IC芯片（13），其特征在于：所述第一IC芯片（3）和第二IC芯片（13）的上表面分别设置多个焊盘（4），所述多个焊盘（4）组成平行设置的两列焊盘组， 分别为第一焊盘组和第二焊盘组，每个焊盘（4）上植有金球（5），每个金球（5）上接一第一铜键合球（6），所述第二IC芯片（13）与第一IC芯片（3）之间在对应的金球（5）上拱丝拉弧形成第三铜键合线（15）。
2. 如权利要求1所述的一种密节距小焊盘铜线键合双IC芯片堆叠封装件，其特征在于所述第一焊盘组和第二焊盘组在间隔的焊盘（4）上分别焊接有一个金球（5），所述第一焊盘组中的金球（5）与第二焊盘组中的金球（5）交错设置，每个金球（5）上焊接一个第一铜键合球（6），每列焊盘组中未焊接金球（5）的焊盘（4）上分别焊接一个第二键合球（8），并在对应的框架引线内引脚（7）上打一铜键合点（10），形成第二铜键合线（14）。
3.如权利要求1或2所述的密节距小焊盘铜线键合双IC芯片堆叠封装件，其特征在于所述每列焊盘组中相邻两焊盘（4）之间留有空隙，所述焊盘（4）的外形尺寸为 38μm×38μm，焊盘（4）的节距为43μm。
4.如权利要求1或2所述的一种密节距小焊盘铜线键合双IC芯片堆叠封装件，其特征在于所述第一铜键合球（6）采用Φ15μm铜线制成，第一铜键合球（6）直径为35μm～38μm。
5.如权利要求1或2所述一种密节距小焊盘铜线键合双IC芯片堆叠封装件，其特征在于所述金球（5）的直径为30μm～36.8μm。
6.如权利要求1或2所述密节距小焊盘铜线键合双IC芯片堆叠封装件，其特征在于所述第二铜键合球（8）采用Φ15μm铜线制成，第二铜键合球（8）直径为34μm～37μm。
7.如权利要求1所述一种密节距小焊盘铜线键合双IC芯片堆叠封装件的制备方法，其特征在于按下述工艺步骤进行：
步骤1 ：减薄、划片
常规方法将晶圆减薄至210μm并划片；
步骤2 
a）一次上芯
 采用载体不外露的引线框架，将已减薄并划片的第一IC芯片（3）固定在引线框架载体上，依次粘完所有第一IC芯片（3）后，将第一IC芯片（3）收料到传递盒；
b)二次上芯 
将粘完所有第一IC芯片（3）的传递盒送到上芯机，传递到机台中央，由轨道压板固定．在第一IC芯片（3）上点上绝缘胶（2）后，吸附第一ＩＣ芯片（3）放置在绝缘胶（2）上，依次粘完所有第一IC芯片（3）后收料到传递盒；
c) 烘烤
采用N2气流量25~30ml/min烘烤3小时，烘烤温度150℃；
步骤3： 压焊
a）在步骤1安装的第一IC芯片上表面平行设置两列焊盘组，该两列焊盘组分别由数量相同的焊盘（4）组成，且两列焊盘组中的各焊盘（4）之间互不接触，一列焊盘组中的焊盘（4）与另一列焊盘组中的焊盘（4）为一一对应，焊盘（4）的各条边的边长为38μm×38μm，焊盘4之间的节距为43μm，相邻两焊盘（4）之间的空隙为5μm；
b) 植金球
将直径15μm的金线轴固定于压焊台上，将已粘第一IC芯片（3）的引线框架载体送上轨道，预热至210℃后传送到压焊台，由轨道压板固定，在第二IC芯片（13）和第一IC芯片（3）间焊线的焊盘上分别植金球（5）后，收料到传递盒；
c) 叠铜球及拱丝打点
将已植金球（5）的堆叠封装半成品及传递盒送到铜线球焊键合台上，在压焊台上固定直径为15μm的铜线轴，穿好线后，将已植金球的引线框架载体传送到轨道上，预热至200℃后传送到压焊夹具上，通过轨道压板进行固定，在第二IC芯片（13）上的每个金球（5）上堆叠一个第一铜键合球（6），向上拱丝拉弧到第一IC芯片（3）已植金球(5)的焊盘(4)上堆叠一个第一铜键合球(6)，形成第三铜键合线(15)； 
d) 不植金球的焊盘直接铜线键合
第二IC芯片（13）和第一IC芯片（3）上焊盘组中未植金球的每个焊盘(4)上直接打第二键合球(8)，并拱丝拉弧到与该焊盘(4)相对应的引线框架内引脚(7)上打一个铜焊点(10)，形成第二铜键合线(14)；
e）重复动作
依次将第二IC芯片和第一IC芯片上不植金球的每个焊盘上直接打一个第二键合球，并拱丝拉弧到与该焊盘相对应的引线框架内引脚上打一个铜焊点，形成第二铜键合线；
步骤4 对压焊后形成的半成品框架进行塑封，采用多段注塑防冲丝、冲丝小于8%防离层工艺，然后常规方法后固化、打印和冲切分离或切割分离（QFN/QFN），制得密节距小焊盘铜线键合IC芯片封装产品。
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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013082970A1 (zh) * 2011-12-09 2013-06-13 天水华天科技股份有限公司 密节距小焊盘铜线键合双ic芯片堆叠封装件及其制备方法
CN107492534A (zh) * 2017-08-03 2017-12-19 中南大学 细节距单ic芯片封装件及其制备方法
CN108493178A (zh) * 2018-02-06 2018-09-04 昆山市品能精密电子有限公司 封装到位的集成电路支架结构及其制造方法
CN108941826A (zh) * 2018-09-21 2018-12-07 锐驰机器人（深圳）有限公司 环形振子自动焊锡机器人及其控制方法
CN110176440A (zh) * 2019-06-26 2019-08-27 袁家和 一种用超声波铜线制造集成电路芯片封装结构
WO2021103642A1 (zh) * 2019-11-26 2021-06-03 长鑫存储技术有限公司 芯片组合及芯片
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* Cited by examiner, † Cited by third party
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JP2018110169A (ja) * 2016-12-28 2018-07-12 富士電機株式会社 半導体装置および半導体装置製造方法
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US10354980B1 (en) 2018-03-22 2019-07-16 Sandisk Technologies Llc Three-dimensional memory device containing bonded chip assembly with through-substrate via structures and method of making the same
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CN112486892B (zh) * 2020-12-15 2024-07-26 泰和电路科技（惠州）有限公司 邦定ic管控计算器的计算方法
CN112670209B (zh) * 2020-12-23 2023-08-29 杰华特微电子股份有限公司 一种加热治具及引线上芯片封装方法
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1381892A (zh) * 2001-04-16 2002-11-27 矽品精密工业股份有限公司 交叉堆叠式双芯片封装装置及制造方法
CN1571157A (zh) * 2003-07-11 2005-01-26 旺宏电子股份有限公司 堆叠式双芯片封装结构

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090302483A1 (en) * 2008-06-04 2009-12-10 Himax Technologies Limited Stacked die package
CN101626008A (zh) * 2009-05-11 2010-01-13 天水华天科技股份有限公司 一种铜线键合ic芯片封装件的生产方法
CN102437147B (zh) * 2011-12-09 2014-04-30 天水华天科技股份有限公司 密节距小焊盘铜线键合双ic芯片堆叠封装件及其制备方法
CN202339914U (zh) * 2011-12-09 2012-07-18 天水华天科技股份有限公司 密节距小焊盘铜线键合双ic芯片堆叠封装件

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1381892A (zh) * 2001-04-16 2002-11-27 矽品精密工业股份有限公司 交叉堆叠式双芯片封装装置及制造方法
CN1571157A (zh) * 2003-07-11 2005-01-26 旺宏电子股份有限公司 堆叠式双芯片封装结构

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013082970A1 (zh) * 2011-12-09 2013-06-13 天水华天科技股份有限公司 密节距小焊盘铜线键合双ic芯片堆叠封装件及其制备方法
US9312242B2 (en) 2011-12-09 2016-04-12 Tianshui Huatian Technology Co., Ltd Dense-pitch small-pad copper wire bonded double IC chip stack packaging piece and preparation method therefor
CN107492534A (zh) * 2017-08-03 2017-12-19 中南大学 细节距单ic芯片封装件及其制备方法
CN108493178A (zh) * 2018-02-06 2018-09-04 昆山市品能精密电子有限公司 封装到位的集成电路支架结构及其制造方法
CN108493178B (zh) * 2018-02-06 2020-10-20 昆山市品能精密电子有限公司 封装到位的集成电路支架结构及其制造方法
CN108941826A (zh) * 2018-09-21 2018-12-07 锐驰机器人（深圳）有限公司 环形振子自动焊锡机器人及其控制方法
CN110176440A (zh) * 2019-06-26 2019-08-27 袁家和 一种用超声波铜线制造集成电路芯片封装结构
WO2021103642A1 (zh) * 2019-11-26 2021-06-03 长鑫存储技术有限公司 芯片组合及芯片
US11164849B2 (en) 2019-11-26 2021-11-02 Changxin Memory Technologies, Inc. Chip assembly and chip
WO2021189488A1 (zh) * 2020-03-27 2021-09-30 京东方科技集团股份有限公司 显示面板和显示装置
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US11805686B2 (en) 2020-03-27 2023-10-31 Boe Technology Group Co., Ltd. Display panel and display device

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