WO2021103642A1 - 芯片组合及芯片 - Google Patents

芯片组合及芯片 Download PDF

Info

Publication number
WO2021103642A1
WO2021103642A1 PCT/CN2020/107430 CN2020107430W WO2021103642A1 WO 2021103642 A1 WO2021103642 A1 WO 2021103642A1 CN 2020107430 W CN2020107430 W CN 2020107430W WO 2021103642 A1 WO2021103642 A1 WO 2021103642A1
Authority
WO
WIPO (PCT)
Prior art keywords
chip
pad
reference potential
pair
edge
Prior art date
Application number
PCT/CN2020/107430
Other languages
English (en)
French (fr)
Inventor
田凯
李红文
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to EP20892133.8A priority Critical patent/EP3923325A4/en
Priority to US17/196,926 priority patent/US11164849B2/en
Publication of WO2021103642A1 publication Critical patent/WO2021103642A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/071—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5286—Arrangements of power or ground buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0616—Random array, i.e. array with no symmetry
    • H01L2224/06164—Random array, i.e. array with no symmetry covering only portions of the surface to be connected
    • H01L2224/06165—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06506—Wire or wire-like electrical connections between devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H01L2924/1436—Dynamic random-access memory [DRAM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates to the field of semiconductor technology, in particular to a chip combination and a chip.
  • low-power DRAM Dynamic Random-Access Memory
  • PADs Pads
  • data input and output ports including data input and output ports, command address ports, clock ports, and multiple sets of power supplies.
  • PADs Pads
  • multiple groups of power/ground ports can increase the power/ground power supply balance and consistency.
  • the land layout of the chip generally has the following types:
  • the PAD and the peripheral control logic circuit 103 are placed in the middle of the chip, that is, between the memory cell array 104, so that the distance from the power/ground PAD to the two edges of the chip is only half of the chip height , The parasitic resistance will be reduced by half. Under the same width of the power/ground cable and the same current conditions, the voltage drop on the power/ground line will be reduced by half, thereby reducing noise and increasing the driving capability, which is particularly conducive to the height of the chip. Frequency working mode. However, this method is not conducive to large-capacity stacked packaging.
  • RDL Re-Distribution Layer
  • the peripheral control logic circuit and part of the PAD are placed on one side of the chip, and part of the PAD is placed on the other side of the chip.
  • the PAD includes distributed power/ground pads 102 and other signal pads 101. It can also reduce the equivalent resistance and wiring area of the power/ground cable, but because the area of a row of PAD is increased, the cost of the chip is directly increased, and the layout of the PAD on both sides will cause the large-capacity and miniaturized package of the chip. Adverse effects.
  • the current packaging trend of low-power DRAM is large-capacity and miniaturization, that is, it is hoped that multiple low-power DRAM particles can be packaged in one packaging cavity to increase capacity and reduce power consumption. This requires that DRAM chips can be stacked and packaged. Without considering the expensive TSV (Through Silicon Via) technology, in the stacked package as shown in Figures 4 and 5, the chip 401 is placed on the substrate 402, and only the PAD is placed on the edge of the chip. Location to facilitate stacking and packaging.
  • the more layers of the chip stack the longer the bonding wire from the chip to the substrate and the larger the space occupied.
  • the size of the chip and the bonding pads on the substrate The number and the number of stacked layers are mutually restrictive.
  • the chip shown in Figure 5 is smaller than the chip shown in Figure 6, so more layers can be stacked; the pads shown in Figure 7 are more than the pads shown in Figure 8, so the chip to the substrate is connected The line is longer and the angle is larger, which takes up more space.
  • the purpose of the embodiments of the present invention is to provide a chip combination and a chip, thereby solving the problem of more pads and fewer stacked layers in the chip combination at least to a certain extent.
  • a chip assembly including: the chip assembly includes a substrate and a first chip and a second chip stacked on the upper surface of the substrate, and the first chip is located on the Above the second chip; on the edges of the first side of the first chip and the second chip are provided with a first pad pair including a first reference potential pad and a second reference potential pad, the first A second pad pair including a first reference potential pad and a second reference potential pad is provided on the edge of the second side of the chip and the second chip, and the second pad pair is located on the first chip Or between the outermost two adjacent functional units of the second side edge of the second chip, and the lower edge of the second pad pair is not lower than the lower edge of the two adjacent functional units; The difference between the orientation of the first side of the first chip and the orientation of the first side of the second chip is 180 degrees, and the pair of first pads of the first chip and the pair of first pads of the second chip are 180 degrees.
  • the two pads correspond to the positions.
  • the first reference potential is the positive electrode of the power supply
  • the second reference potential is the ground potential
  • the chip combination further includes a third chip and a fourth chip that are stacked, and the third chip and the fourth chip are stacked and the first chip and the second chip are stacked side by side. On the substrate.
  • gold fingers are provided on the upper surface of the edge of the substrate corresponding to the first side and the second side of the first chip.
  • the pad pair is provided on the upper surface of the first chip and the second chip.
  • the pad pairs on the first chip and the second chip are coupled with the golden fingers through bonding wires.
  • the pad pair on the first side of the first chip is connected to the pad pair on the second side of the first chip through a power cable.
  • each of the chip combinations includes a first chip and a second chip in a stack, and a third chip and a fourth chip in a stack.
  • the first chip includes a peripheral logic control circuit and a memory cell array, and the peripheral logic control circuit is located on the first side of the first chip.
  • other signal pads of the first chip except for the first reference potential pad and the second reference potential pad are arranged on the edge of the first side of the first chip .
  • the first reference potential pad of the first pad pair of the first chip corresponds to the first reference potential pad position of the second pad pair of the second chip;
  • the second reference potential pad position of the first pad pair of a chip corresponds to the second reference potential pad position of the second pad pair of the second chip.
  • a chip a first pad pair including a first reference potential pad and a second reference potential pad is provided on the edge of the first side of the chip, the A second pad pair including a first reference potential pad and a second reference potential pad is provided on the edge of the second side of the chip, and the second pad pair is located at the outermost side of the second side edge of the chip And the lower edge of the second pad pair is not lower than the lower edge of the two adjacent functional units; after the chip is rotated 180 degrees in its own plane, The position of the pad pair on the first side of the chip after the rotation corresponds to the position of the pad pair on the second side of the chip before the rotation.
  • the first reference potential pad of the first pad pair of the chip after the rotation corresponds to the first reference potential pad position of the second pad pair of the chip before the rotation;
  • the second reference potential pad of the first pad pair of the chip corresponds to the position of the second reference potential pad of the second pad pair of the chip before the rotation.
  • the chip includes a dynamic random access memory chip, and the functional unit of the chip includes a memory cell array.
  • a pair of pads is provided on the first side and the second side of the first chip and the second chip, and the first pad pair and the second side of the first chip
  • the second pad pair of the chip corresponds to the position, which can reduce the number of pads of the chip and the number of solder joints corresponding to the pad pairs on the substrate, thereby increasing the number of stackable layers in a fixed packaging space; in addition, due to the first
  • the two pad pairs are located between the outermost two adjacent functional units of the second side edge of the first chip or the second chip, which can further save the space of the chip, so as to realize that the pads are provided on the second side of the chip but not The effect of occupying the marginal space on the second side.
  • Fig. 1 schematically shows a schematic diagram of a chip layout in the related art
  • FIG. 2 schematically shows a schematic diagram of another chip layout in the related art
  • FIG. 3 schematically shows a schematic diagram of yet another chip layout in the related art
  • Fig. 4 schematically shows a top view of another chip layout in the related art
  • Figure 5 schematically shows a cross-sectional view of yet another chip layout in the related art
  • Fig. 6 schematically shows a cross-sectional view of another chip layout in the related art
  • FIG. 7 schematically shows a schematic diagram of the connection between a chip and a substrate in the related art
  • FIG. 8 schematically shows another schematic diagram of the connection between a chip and a substrate in the related art
  • FIG. 9 schematically shows a schematic structural diagram of a chip according to an embodiment of the present invention.
  • FIG. 10 schematically shows a schematic diagram of pad pin changes according to an embodiment of the present invention.
  • FIG. 11 schematically shows a structural diagram of a chip assembly according to an embodiment of the present invention.
  • 101 other signal pads; 102, power/ground pads; 103, peripheral control logic circuit; 104, memory cell array; 401, chip; 402, substrate; 901, the first pad pair; 902, the first Two pad pairs; 903, power cable; 1101, first chip; 1102, second chip; 1103, gold finger; 1104, gold finger; 1105, power positive pad; 1106, ground potential pad; 1107, bonding wire.
  • the embodiments of the present invention provide a chip combination to reduce the number of pads of the chip and increase the number of stackable layers in a fixed packaging space.
  • Fig. 9 schematically shows a structural diagram of a chip according to an embodiment of the present invention.
  • the edge of the first side of the chip in the embodiment of the present invention is provided with a first pad pair 901 including a first reference potential pad and a second reference potential pad, and the edge of the second side of the chip
  • a second pad pair 902 including a first reference potential pad and a second reference potential pad is provided thereon, and the second pad pair 902 is located between two adjacent functional units on the outermost side of the second side edge of the chip , And the lower edge of the second pad pair 902 is not lower than the lower edges of the two adjacent functional units; after the chip is rotated 180 degrees in the plane where it is located, the pad pair on the first side of the chip after the rotation is the same as the one before the rotation.
  • the pads on the second side of the chip correspond to the positions.
  • the first reference potential pad of the first pad pair of the chip after rotation corresponds to the first reference potential pad position of the second pad pair of the chip before rotation; the first pad pair of the first pad pair of the chip after rotation
  • the two reference potential pads correspond to the second reference potential pad positions of the second pad pair of the chip before rotation.
  • the chip may be a dynamic random access memory chip, and the functional unit may be the memory cell array 104.
  • the first reference potential may be the positive electrode of the power supply, and the second reference potential may be the ground potential.
  • the pad order recommended by JEDEC Joint Electron Device Engineering Council Soild State Technology Association, Joint Committee on Electronic Device Engineering
  • the arrangement position of the memory cell array 104 select the appropriate VSSQ (number I/O port ground) and VQQ (digital ground), such as pad 19, pad 39 and pad 60, and add power positive (VDD2) pads beside these VSSQ and VQQ, such as pad 18A, pad 38A and pad 60B.
  • VDD2 The added power supply positive (VDD2) pad and the adjacent ground potential PAD form a pad pair, that is, a power/ground pair, so as to facilitate the remote PAD distribution design.
  • VSSQ and VSS are actually short-circuited, that is, the same node.
  • the chip combination provided by an exemplary embodiment of the present disclosure includes a substrate and a first chip and a second chip stacked on the upper surface of the substrate, and the first chip is located above the second chip.
  • the first chip is the chip shown in FIG. 9.
  • a first pad pair 901 including a first reference potential pad and a second reference potential pad is provided on the edge of the first side of the first chip.
  • a second pad pair 902 including a first reference potential pad and a second reference potential pad is provided on the edge of the second side of the first chip.
  • the second pad pair 902 is located at the edge of the second side of the first chip. Between the outermost two adjacent functional units, and the lower edge of the second pad pair 902 is not lower than the lower edge of the two adjacent functional units.
  • a first pad pair including a first reference potential pad and a second reference potential pad is provided on the edge of the first side of the second chip, and a first pad pair including the first reference potential is provided on the edge of the second side of the second chip.
  • the second pad pair of the pad and the second reference potential pad, the second pad pair is located between the two adjacent functional units on the outermost side of the second side edge of the second chip, and the second pad pair The lower edge is not lower than the lower edge of two adjacent functional units.
  • the difference between the orientation of the first side of the first chip and the orientation of the first side of the second chip is 180 degrees, and the first pad pair of the first chip corresponds to the second pad pair of the second chip.
  • pad pairs are provided on the edges of the first side and the second side of the first chip and the second chip, and the first pad pair of the first chip and the second pad pair of the second chip The positions correspond to each other, so that when soldering the pad pair to the gold finger on the substrate, a pad on the first side of the first chip and a pad on the second side of the second chip can correspond to the same gold finger Connect, thereby reducing the number of gold fingers.
  • the second pad pair is located between two adjacent functional units on the outermost side of the second side edge of the first chip or the second chip, which saves the space on the second side edge of the chip, and comprehensively considers the feasibility of packaging.
  • Various factors such as power/ground PAD layout, wiring resources and utilization, the distribution of the modules inside the chip, chip area and manufacturing cost, etc., are a new power/ground PAD layout method, which can be used without increasing In the case of area, the purpose of reducing the equivalent resistance of the power/ground cable and improving the high-frequency performance of the chip is achieved.
  • the first reference potential pad of the first pad pair of the first chip corresponds to the first reference potential pad position of the second pad pair of the second chip;
  • the second reference potential pad of the pad pair corresponds to the position of the second reference potential pad of the second pad pair of the second chip.
  • the first side of the first chip is provided with 3 sets of pad pairs.
  • the left pad of the first pad pair from left to right is the positive electrode pad of the power supply, and the right pad is the ground potential pad; the second and third pad pair from left to right The left pad is the ground potential pad, and the right pad is the power positive pad.
  • the second side of the first chip is provided with 3 sets of pad pairs, of which, from left to right, the left pad of the first pad pair and the second pad pair is the positive electrode pad of the power supply, and the right pad is Ground potential pad; the left pad of the third pad pair from left to right is the ground potential pad, and the right pad is the power supply positive pad.
  • the second chip may have the same structure as the first chip.
  • some of the logic between memory cell arrays 104 are connected up and down. Because there is no connection line at the bottom of the memory cell array, some logic can be simplified and deleted, and power supplies can be placed in vacant positions. Ground PAD, in this way, the second pad pair can be arranged between two adjacent functional units on the outermost side of the second side edge of the first chip or the second chip, so as to reduce the area of the chip.
  • the pad pair on the first side of the first chip is connected to the pad pair on the second side through the power cable 903.
  • the first chip includes a peripheral logic control circuit 103 and a memory cell array 104, and the peripheral logic control circuit 103 is located on the first side of the first chip.
  • the signal pads of the first chip other than the first reference potential pad and the second reference potential pad are arranged on the edge of the first side of the first chip.
  • other signal pads include data input and output port pads, command address port pads, and clock port pads.
  • the chip combination further includes a third chip and a fourth chip that are stacked, and the stack combination formed by the first chip and the second chip is arranged side by side with the stack combination formed by the third chip and the fourth chip. On the substrate.
  • each chip combination includes a first chip and a second chip in a stack, and a third chip and a fourth chip in a stack.
  • the first chip 1101 and the second chip 1102 are stacked on the substrate 402.
  • the power positive electrode pad 1105 and the ground potential pad 1106 are coupled with the gold finger 1103 and the gold finger 1104 through bonding wires 1107.
  • gold fingers are provided on the upper surface of the edge of the substrate corresponding to the first side and the second side of the first chip.
  • the gold finger is arranged on the upper surface of the substrate, and the pad pair may also be arranged on the upper surface of the first side and the second side edge of the first chip and the second chip.
  • the pair of pads can also be provided on the upper surfaces of the third chip and the fourth chip.
  • the pad pairs on the third chip and the fourth chip can also be coupled with gold fingers through bonding wires.
  • the pad pair may include a power positive electrode pad 1105 and a ground potential pad 1106.
  • a pair of pads are respectively provided on the first side and the second side of the first chip and the second chip, and the first pad pair of the first chip and the second chip of the second chip.
  • the two pad pairs correspond to the positions, which can reduce the number of chip pads and the number of solder joints corresponding to the pad pairs on the substrate, thereby increasing the number of stackable layers in a fixed packaging space; in addition, due to the second pad For the two adjacent functional units located on the outermost side of the second side edge of the first chip or the second chip, the space of the chip can be further saved, so that the pads are arranged on the second side of the chip without occupying the second side. The effect of side marginal space.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

本公开提供了一种芯片组合及芯片，包括：基板和设置于基板上表面的堆叠设置的第一芯片和第二芯片，第一芯片位于第二芯片上方；第一芯片和第二芯片的第一侧的边缘上设置有第一焊盘对，第一芯片和第二芯片的第二侧的边缘上设置有第二焊盘对，第二焊盘对位于第一芯片或第二芯片的第二侧边缘的最外侧的两个相邻功能单元之间，且第二焊盘对的下边缘不低于两个相邻功能单元的下边缘；第一芯片的第一侧的朝向与第二芯片的第一侧的朝向的差值为180度，且第一芯片的第一焊盘对与第二芯片的第二焊盘对位置相对应。本发明的技术方案可以在芯片封装内部腔体空间有限的条件下减少芯片尺寸和焊盘数，增加芯片堆叠的层数。

Description

芯片组合及芯片
本公开要求于2019年11月26日递交的第201911176109.X号中国专利、名称为“芯片组合及芯片”的申请的优先权，在此全文引用上述中国专利申请公开的内容以作为本公开的一部分。
技术领域
本发明涉及半导体技术领域，具体而言，涉及一种芯片组合及芯片。
背景技术
目前低功耗DRAM(Dynamic Random-Access Memory，动态随机存储器)一般会有近百个甚至更多的PAD(焊盘)，其中包括数据输入输出端口，命令地址端口，时钟端口及多组电源/地的端口。多组电源/地的端口作为分布式供电的组成部分，可以增加电源/地的供电均衡性和一致性。芯片的焊盘布局一般有以下几种：
如图1所示，把PAD和外围控制逻辑电路103放在芯片的中间部分，即存储单元阵列104之间，这样可以使得电源/地的PAD到芯片两个边缘的距离都只有芯片高度的一半，寄生电阻会减小一半，在同样宽度的电源/地排线和同样的电流条件下，电源/地线上的压降降低一半，从而减少噪声，增大驱动能力，特别有利于芯片的高频工作模式。但这种方式不利于大容量的堆叠封装形式，如果要堆叠封装，需要引入RDL(Re-Distribution Layer，再分布层)把中间的PAD引到芯片的一边，既增加了工艺的复杂性，增加了生产制造的成本，而且引入RDL产生的寄生电阻也会削弱把PAD放在中间所获得的低电阻的好处。
如图2所示，把PAD和外围控制逻辑电路放在芯片的某一边，尤其是在短边，这时电源/地排线最长，寄生电阻最大，在远离PAD的芯片远端压降最大，会造成芯片远端的性能比近端的性能差很多，尤其在高频工作模式。为了能让远端正常工作，所需要的电源/地排线不得不加宽，而这样又侵占了其他信号线的空间，给版图设计增加了难度。
如图3所示，把外围控制逻辑电路和部分PAD设置在芯片的一边，部分PAD放在芯片的另一边，其中PAD包括分布式的电源/地焊盘102及其他信号 焊盘101，这样做同样可以减小电源/地排线的等效电阻及排线面积，但因为增加一排PAD的面积，直接导致芯片成本升高，而且两边的PAD布局会对芯片的大容量、小型化封装造成不良的影响。
目前低功耗DRAM的封装趋势是大容量、小型化，即希望在一个封装腔体内可以封装多低功耗DRAM的颗粒，以提高容量，降低功耗。这就要求DRAM芯片可以堆叠封装。在不考虑昂贵的TSV(Through Silicon Via，硅穿孔)技术的前提条件下，如图4和图5所示的堆叠封装中，芯片401设置在基板402上，只有把PAD放在芯片的边缘的位置，才能方便堆叠封装。
芯片堆叠层数越多，从芯片到基板的连线(bonding wire)也会越长，占用空间也越大，在封装内部腔体空间有限的条件下，芯片的大小，基板上连接的焊盘数，堆叠的层数，是相互制约的关系，较小的芯片尺寸，较少的焊盘数，可以堆叠较多的层数。如图5所示的芯片小于如图6所示的芯片，因此可以堆叠较多的层数；如图7所示的焊盘多于如图8所示的焊盘，因此芯片到基板的连线较长，角度较大，从而占用空间较大。
芯片组合中焊盘较多、堆叠层数较少是当前亟需解决的技术问题。。
需要说明的是，在上述背景技术部分发明的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本发明实施例的目的在于提供一种芯片组合及芯片，进而至少在一定程度上解决芯片组合中焊盘较多、堆叠层数较少的问题。
本发明的其它特性和优点将通过下面的详细描述变得显然，或部分地通过本发明的实践而习得。
根据本发明实施例的第一方面提供了一种芯片组合，包括：所述芯片组合包括基板和设置于基板上表面的堆叠设置的第一芯片和第二芯片，所述第一芯片位于所述第二芯片上方；所述第一芯片和所述第二芯片的第一侧的边缘上设置有包括第一参考电位焊盘和第二参考电位焊盘的第一焊盘对，所述第一芯片和所述第二芯片的第二侧的边缘上设置有包括第一参考电位焊盘和第二参考电位焊盘的第二焊盘对，所述第二焊盘对位于所述第一芯片或所述第二芯片的 第二侧边缘的最外侧的两个相邻功能单元之间，且所述第二焊盘对的下边缘不低于所述两个相邻功能单元的下边缘；所述第一芯片的第一侧的朝向与所述第二芯片的第一侧的朝向的差值为180度，且所述第一芯片的第一焊盘对与所述第二芯片的第二焊盘对位置相对应。
在一些实施例中，所述第一参考电位为电源正极，所述第二参考电位为地电位。
在一些实施例中，所述芯片组合还包括堆叠设置的第三芯片和第四芯片，所述堆叠设置的第三芯片和第四芯片与所述堆叠设置的第一芯片和第二芯片并排设置在所述基板上。
在一些实施例中，所述基板的与所述第一芯片的第一侧和第二侧对应的边缘的上表面设置有金手指。
在一些实施例中，所述焊盘对设置于所述第一芯片和所述第二芯片的上表面。
在一些实施例中，所述第一芯片和所述第二芯片上的所述焊盘对通过接合导线与所述金手指耦合。
在一些实施例中，位于所述第一芯片的第一侧的焊盘对通过电源排线与位于所述第一芯片的第二侧的焊盘对连接。
在一些实施例中，每个所述芯片组合包括堆叠设置的第一芯片和第二芯片，以及堆叠设置的第三芯片和第四芯片。
在一些实施例中，所述第一芯片包括外围逻辑控制电路和存储单元阵列，所述外围逻辑控制电路位于所述第一芯片的第一侧。
在一些实施例中，所述第一芯片的除所述第一参考电位焊盘与第二参考电位焊盘之外的其它信号焊盘设置于所述第一芯片的所述第一侧的边缘。
在一些实施例中，所述第一芯片的第一焊盘对的第一参考电位焊盘与所述第二芯片的第二焊盘对的第一参考电位焊盘位置相对应；所述第一芯片的第一焊盘对的第二参考电位焊盘与所述第二芯片的第二焊盘对的第二参考电位焊盘位置相对应。
根据本发明实施例的第二方面提供了一种芯片，所述芯片的第一侧的边缘上设置有包括第一参考电位焊盘和第二参考电位焊盘的第一焊盘对，所述芯片的第二侧的边缘上设置有包括第一参考电位焊盘和第二参考电位焊盘的第二 焊盘对，所述第二焊盘对位于所述芯片的第二侧边缘的最外侧的两个相邻功能单元之间，且所述第二焊盘对的下边缘不低于所述两个相邻功能单元的下边缘；所述芯片在自身所在的平面内旋转180度后，旋转后所述芯片的第一侧的焊盘对与旋转前所述芯片的第二侧的焊盘对位置相对应。
在一些实施例中，旋转后所述芯片的第一焊盘对的第一参考电位焊盘与旋转前所述芯片的第二焊盘对的第一参考电位焊盘位置相对应；旋转后所述芯片的第一焊盘对的第二参考电位焊盘与旋转前所述芯片的第二焊盘对的第二参考电位焊盘位置相对应。
在一些实施例中，所述芯片包括动态随机存储器芯片，所述芯片的功能单元包括存储单元阵列。
本发明实施例提供的技术方案可以包括以下有益效果：
在本发明的一些实施例所提供的技术方案中，通过在第一芯片和第二芯片的第一侧和第二侧分别设置焊盘对，且第一芯片的第一焊盘对与第二芯片的第二焊盘对位置相对应，可以减少芯片的焊盘数，减少基板上与焊盘对对应的焊点的数量，从而在固定的封装空间中增加可堆叠层数；此外，由于第二焊盘对位于第一芯片或第二芯片的第二侧边缘的最外侧的两个相邻功能单元之间，可以进一步节省芯片的空间，从而实现在芯片的第二侧设置焊盘但不占用第二侧边缘空间的效果。应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1示意性示出了相关技术中的一种芯片布局的示意图；
图2示意性示出了相关技术中的另一种芯片布局的示意图；
图3示意性示出了相关技术中的又一种芯片布局的示意图；
图4示意性示出了相关技术中的又一种芯片布局的俯视图；
图5示意性示出了相关技术中的又一种芯片布局的截面图；
图6示意性示出了相关技术中的又一种芯片布局的截面图；
图7示意性示出了相关技术中的一种芯片与基板连接的示意图；
图8示意性示出了相关技术中的另一种芯片与基板连接的示意图；
图9示意性示出了本发明实施例的一种芯片的结构示意图；
图10示意性示出了本发明实施例的焊盘引脚变动示意图；
图11示意性示出了本发明实施例的芯片组合的结构示意图。
图中：101、其他信号焊盘；102、电源/地焊盘；103、外围控制逻辑电路；104、存储单元阵列；401、芯片；402、基板；901、第一焊盘对；902、第二焊盘对；903、电源排线；1101、第一芯片；1102、第二芯片；1103、金手指；1104、金手指；1105、电源正极焊盘；1106、地电位焊盘；1107、接合导线。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
相关技术中，在同样的封装内部腔体空间中，芯片组合的芯片的焊盘数越多，芯片可以堆叠的层数越少，进而影响芯片组合的功能。
为解决上述问题，本发明实施例提供一种芯片组合，以减少芯片的焊盘数，以增加在固定的封装空间中的可堆叠层数。
图9示意性示出了根据本发明的实施例的芯片的结构示意图。
如图9所述，本发明实施例的芯片的第一侧的边缘上设置有包括第一参考电位焊盘和第二参考电位焊盘的第一焊盘对901，芯片的第二侧的边缘上设置有包括第一参考电位焊盘和第二参考电位焊盘的第二焊盘对902，第二焊盘对902位于芯片的第二侧边缘的最外侧的两个相邻功能单元之间，且第二焊盘对902的下边缘不低于两个相邻功能单元的下边缘；芯片在自身所在的平面内旋转180度后，旋转后芯片的第一侧的焊盘对与旋转前芯片的第二侧的焊盘对位置相对应。
这样，旋转后芯片的第一焊盘对的第一参考电位焊盘与旋转前芯片的第 二焊盘对的第一参考电位焊盘位置相对应；旋转后芯片的第一焊盘对的第二参考电位焊盘与旋转前芯片的第二焊盘对的第二参考电位焊盘位置相对应。
这里，芯片可以为动态随机存储器芯片，功能单元可以为存储单元阵列104。第一参考电位可以为电源正极，第二参考电位可以为地电位。如图10所示，根据JEDEC(Joint Electron Device Engineering Council Soild State Technology Association，电子器件工程联合委员会)推荐的焊盘顺序(pad order)，根据存储单元阵列104的排布位置，选取合适VSSQ(数字I/O口地)和VQQ(数字地)，如焊盘19、焊盘39和焊盘60，并在这些VSSQ和VQQ的旁边增加电源正极(VDD2)焊盘，如焊盘18A，焊盘38A和焊盘60B。增加的电源正极(VDD2)焊盘与相邻的地电位PAD构成焊盘对即电源/地对，以便于远端的PAD分布设计。这里，VSSQ和VSS实际上是短路的情况，即为同一个节点。
本公开示例性实施例提供的芯片组合包括：基板和设置于基板上表面的堆叠设置的第一芯片和第二芯片，第一芯片位于第二芯片上方。这里，第一芯片即为如图9所示芯片。
如图11所示，第一芯片的第一侧的边缘上设置有包括第一参考电位焊盘和第二参考电位焊盘的第一焊盘对901。第一芯片的第二侧的边缘上设置有包括第一参考电位焊盘和第二参考电位焊盘的第二焊盘对902，第二焊盘对902位于第一芯片的第二侧边缘的最外侧的两个相邻功能单元之间，且第二焊盘对902的下边缘不低于两个相邻功能单元的下边缘。第二芯片的第一侧的边缘上设置有包括第一参考电位焊盘和第二参考电位焊盘的第一焊盘对，第二芯片的第二侧的边缘上设置有包括第一参考电位焊盘和第二参考电位焊盘的第二焊盘对，第二焊盘对位于第二芯片的第二侧边缘的最外侧的两个相邻功能单元之间，且第二焊盘对的下边缘不低于两个相邻功能单元的下边缘。第一芯片的第一侧的朝向与第二芯片的第一侧的朝向的差值为180度，且第一芯片的第一焊盘对与第二芯片的第二焊盘对位置相对应。
本发明实施例的技术方案在第一芯片和第二芯片的第一侧和第二侧的边缘设置焊盘对，且第一芯片的第一焊盘对与第二芯片的第二焊盘对位置相对应，这样，在将焊盘对与基板上的金手指焊接时，可以将第一芯片的第一侧的一个焊盘和第二芯片的第二侧的一个焊盘对应同一个金手指连接，从而减 少金手指的数量。
此外，第二焊盘对位于第一芯片或所述第二芯片的第二侧边缘的最外侧的两个相邻功能单元之间，节省了芯片的第二侧边缘的空间，综合考虑封装可行性、电源/地PAD的布局、排线资源及利用率、芯片内部各模块的分布、芯片面积及制造成本等各项因素，是一种新的电源/地PAD排布方式，可以在不增加面积的情况下，达到减小电源/地排线的等效电阻，提高芯片的高频性能的目的。
在本发明实施例中，第一芯片的第一焊盘对的第一参考电位焊盘与第二芯片的第二焊盘对的第一参考电位焊盘位置相对应；第一芯片的第一焊盘对的第二参考电位焊盘与第二芯片的第二焊盘对的第二参考电位焊盘位置相对应。
如图9所示，第一芯片的第一侧设置有3组焊盘对。其中，自左至右第一个焊盘对的左侧焊盘为电源正极焊盘，右侧焊盘为地电位焊盘；自左至右第二个焊盘对和第三个焊盘对的左侧焊盘为地电位焊盘，右侧焊盘为电源正极焊盘。第一芯片的第二侧设置有3组焊盘对，其中，自左至右第一个焊盘对和第二个焊盘对的左侧焊盘为电源正极焊盘，右侧焊盘为地电位焊盘；自左至右第三个焊盘对的左侧焊盘为地电位焊盘，右侧焊盘为电源正极焊盘。第二芯片可以与第一芯片具有同样的结构。
这样，第一芯片的第一焊盘对与第二芯片的第二焊盘对位置相对应设置时，这样，上方的第一芯片的第一侧的3组电源/地PAD与下方的第二芯片的第二侧的电源/地PAD位置重合，不需要额外的面积放置PAD，在封装时也不需要在基板上增加额外的金手指做连接。
此外，存储单元阵列104之间的逻辑比如译码逻辑有一些是作为上下连接的，在最底部的存储单元阵列因为下部没有连接线，可以对一些逻辑进行简化，删除，在空置位置放置电源/地的PAD，这样，第二焊盘对可以设置于第一芯片或第二芯片的第二侧边缘的最外侧的两个相邻功能单元之间，以减少芯片的面积。
如图9所示，位于第一芯片的第一侧的焊盘对通过电源排线903与位于第二侧的焊盘对连接。第一芯片包括外围逻辑控制电路103和存储单元阵列104，外围逻辑控制电路103位于第一芯片的第一侧。第一芯片的除第一参考 电位焊盘与第二参考电位焊盘之外的其它信号焊盘设置于第一芯片的第一侧的边缘。这里，其它信号焊盘包括数据输入输出端口焊盘、命令地址端口焊盘和时钟端口焊盘。
在本发明实施例中，芯片组合还包括堆叠设置的第三芯片和第四芯片，第一芯片和第二芯片形成的堆叠组合，与第三芯片与第四芯片形成的堆叠组合，并排设置在基板上。
如图11所示的基板上的第一芯片和第二芯片形成的堆叠组合中芯片的数量为两个，但在实际应用中第一芯片和第二芯片形成的堆叠组合的芯片的数量并不局限于此。同样，第三芯片与第四芯片形成的堆叠组合的芯片的数量也可以为两个或多个。例如，在一种实施例中，每个芯片组合包括堆叠设置的第一芯片和第二芯片，和堆叠设置的第三芯片与第四芯片。
如图11所示，第一芯片1101和第二芯片1102层叠设置在基板402上。电源正极焊盘1105和地电位焊盘1106通过接合导线1107与金手指1103和金手指1104耦合。在本发明实施例中，基板的与第一芯片的第一侧和第二侧对应的边缘的上表面设置有金手指。金手指设置在基板的上表面，焊盘对也可以设置在第一芯片和第二芯片的第一侧和第二侧边缘的上表面。
同样，焊盘对也可以设置在第三芯片和第四芯片的上表面。第三芯片和第四芯片上的焊盘对也可以通过接合导线与金手指耦合。这里，焊盘对可以包括电源正极焊盘1105和地电位焊盘1106。
在本发明实施例所的芯片组合中，通过在第一芯片和第二芯片的第一侧和第二侧分别设置焊盘对，且第一芯片的第一焊盘对与第二芯片的第二焊盘对位置相对应，可以减少芯片的焊盘数，减少基板上与焊盘对对应的焊点的数量，从而在固定的封装空间中增加可堆叠层数；此外，由于第二焊盘对位于第一芯片或第二芯片的第二侧边缘的最外侧的两个相邻功能单元之间，可以进一步节省芯片的空间，从而实现在芯片的第二侧设置焊盘但不占用第二侧边缘空间的效果。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上” 时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本公开旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (14)

  1. 一种芯片组合，其特征在于，包括：基板和设置于基板上表面的堆叠设置的第一芯片和第二芯片，所述第一芯片位于所述第二芯片上方；
    所述第一芯片和所述第二芯片的第一侧的边缘上设置有包括第一参考电位焊盘和第二参考电位焊盘的第一焊盘对，所述第一芯片和所述第二芯片的第二侧的边缘上设置有包括第一参考电位焊盘和第二参考电位焊盘的第二焊盘对，所述第二焊盘对位于所述第一芯片或所述第二芯片的第二侧边缘的最外侧的两个相邻功能单元之间，且所述第二焊盘对的下边缘不低于所述两个相邻功能单元的下边缘；
    所述第一芯片的第一侧的朝向与所述第二芯片的第一侧的朝向的差值为180度，且所述第一芯片的第一焊盘对与所述第二芯片的第二焊盘对位置相对应。
  2. 根据权利要求1所述的芯片组合，其特征在于，所述第一参考电位为电源正极，所述第二参考电位为地电位。
  3. 根据权利要求1所述的芯片组合，其特征在于，所述芯片组合还包括堆叠设置的第三芯片和第四芯片，所述堆叠设置的第三芯片和第四芯片与所述堆叠设置的第一芯片和第二芯片并排设置在所述基板上。
  4. 根据权利要求3所述的芯片组合，其特征在于，所述基板的与所述第一芯片的第一侧和第二侧对应的边缘的上表面设置有金手指。
  5. 根据权利要求4所述的芯片组合，其特征在于，所述焊盘对设置于所述第一芯片和所述第二芯片的上表面。
  6. 根据权利要求4所述的芯片组合，其特征在于，所述第一芯片和所述第二芯片上的所述焊盘对通过接合导线与所述金手指耦合。
  7. 根据权利要求1所述的芯片组合，其特征在于，位于所述第一芯片的第一侧的焊盘对通过电源排线与位于所述第一芯片的第二侧的焊盘对连接。
  8. 根据权利要求1所述的芯片组合，其特征在于，每个所述芯片组合包括堆叠设置的第一芯片和第二芯片，以及堆叠设置的第三芯片和第四芯片。
  9. 根据权利要求1所述的芯片组合，其特征在于，所述第一芯片包括外围逻辑控制电路和存储单元阵列，所述外围逻辑控制电路位于所述第一芯片的 第一侧。
  10. 根据权利要求1所述的芯片组合，其特征在于，所述第一芯片的除所述第一参考电位焊盘与第二参考电位焊盘之外的其它信号焊盘设置于所述第一芯片的所述第一侧的边缘。
  11. 根据权利要求1所述的芯片组合，其特征在于，所述第一芯片的第一焊盘对的第一参考电位焊盘与所述第二芯片的第二焊盘对的第一参考电位焊盘位置相对应；所述第一芯片的第一焊盘对的第二参考电位焊盘与所述第二芯片的第二焊盘对的第二参考电位焊盘位置相对应。
  12. 一种芯片，其特征在于，所述芯片的第一侧的边缘上设置有包括第一参考电位焊盘和第二参考电位焊盘的第一焊盘对，所述芯片的第二侧的边缘上设置有包括第一参考电位焊盘和第二参考电位焊盘的第二焊盘对，所述第二焊盘对位于所述芯片的第二侧边缘的最外侧的两个相邻功能单元之间，且所述第二焊盘对的下边缘不低于所述两个相邻功能单元的下边缘；
    所述芯片在自身所在的平面内旋转180度后，旋转后所述芯片的第一侧的焊盘对与旋转前所述芯片的第二侧的焊盘对位置相对应。
  13. 根据权利要求12所述的芯片，其特征在于，旋转后所述芯片的第一焊盘对的第一参考电位焊盘与旋转前所述芯片的第二焊盘对的第一参考电位焊盘位置相对应；旋转后所述芯片的第一焊盘对的第二参考电位焊盘与旋转前所述芯片的第二焊盘对的第二参考电位焊盘位置相对应。
  14. 根据权利要求12所述的芯片，其特征在于，所述芯片包括动态随机存储器芯片，所述芯片的功能单元包括存储单元阵列。
PCT/CN2020/107430 2019-11-26 2020-08-06 芯片组合及芯片 WO2021103642A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP20892133.8A EP3923325A4 (en) 2019-11-26 2020-08-06 CHIP AND CHIP COMBINATION
US17/196,926 US11164849B2 (en) 2019-11-26 2021-03-09 Chip assembly and chip

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201911176109.X 2019-11-26
CN201911176109.XA CN112951811A (zh) 2019-11-26 2019-11-26 芯片组合及芯片

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/196,926 Continuation US11164849B2 (en) 2019-11-26 2021-03-09 Chip assembly and chip

Publications (1)

Publication Number Publication Date
WO2021103642A1 true WO2021103642A1 (zh) 2021-06-03

Family

ID=76129949

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/107430 WO2021103642A1 (zh) 2019-11-26 2020-08-06 芯片组合及芯片

Country Status (4)

Country Link
US (1) US11164849B2 (zh)
EP (1) EP3923325A4 (zh)
CN (1) CN112951811A (zh)
WO (1) WO2021103642A1 (zh)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040026794A1 (en) * 2002-04-29 2004-02-12 Yuming Tao High speed I/O pad and pad/cell interconnection for flip chips
CN102437147A (zh) * 2011-12-09 2012-05-02 天水华天科技股份有限公司 密节距小焊盘铜线键合双ic芯片堆叠封装件及其制备方法
US20170011976A1 (en) * 2015-07-09 2017-01-12 Samsung Electronics Co., Ltd. Semiconductor chip including chip pad, redistribution wiring test pad, and redistribution wiring connection pad
CN206532776U (zh) * 2017-02-17 2017-09-29 成都芯锐科技有限公司 多芯片堆叠封装结构
CN108962881A (zh) * 2018-07-03 2018-12-07 华进半导体封装先导技术研发中心有限公司 堆叠封装结构
CN210640244U (zh) * 2019-11-26 2020-05-29 长鑫存储技术有限公司 芯片组合及芯片

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2792795B2 (ja) * 1992-10-29 1998-09-03 三菱電機株式会社 半導体集積装置
KR100384056B1 (ko) * 1999-06-03 2003-05-14 삼성전자주식회사 반도체 메모리 장치 및 그 장치의 데이터 출력버퍼
JP2006140466A (ja) * 2005-10-21 2006-06-01 Renesas Technology Corp 半導体記憶装置
JP4921937B2 (ja) * 2006-11-24 2012-04-25 株式会社東芝 半導体集積回路
KR102211934B1 (ko) * 2014-03-06 2021-02-04 삼성전자주식회사 반도체 패키지

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040026794A1 (en) * 2002-04-29 2004-02-12 Yuming Tao High speed I/O pad and pad/cell interconnection for flip chips
CN102437147A (zh) * 2011-12-09 2012-05-02 天水华天科技股份有限公司 密节距小焊盘铜线键合双ic芯片堆叠封装件及其制备方法
US20170011976A1 (en) * 2015-07-09 2017-01-12 Samsung Electronics Co., Ltd. Semiconductor chip including chip pad, redistribution wiring test pad, and redistribution wiring connection pad
CN206532776U (zh) * 2017-02-17 2017-09-29 成都芯锐科技有限公司 多芯片堆叠封装结构
CN108962881A (zh) * 2018-07-03 2018-12-07 华进半导体封装先导技术研发中心有限公司 堆叠封装结构
CN210640244U (zh) * 2019-11-26 2020-05-29 长鑫存储技术有限公司 芯片组合及芯片

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3923325A4

Also Published As

Publication number Publication date
CN112951811A (zh) 2021-06-11
EP3923325A1 (en) 2021-12-15
EP3923325A4 (en) 2022-06-15
US11164849B2 (en) 2021-11-02
US20210265316A1 (en) 2021-08-26

Similar Documents

Publication Publication Date Title
US20230137580A1 (en) 3d chip with shared clock distribution network
JP4753725B2 (ja) 積層型半導体装置
US8174860B2 (en) Semiconductor memory device having improved voltage transmission path and driving method thereof
US8916875B2 (en) Semiconductor packages
US20060249829A1 (en) Stacked type semiconductor device
US7405472B2 (en) Semiconductor device
US20100052111A1 (en) Stacked-chip device
EP3852110A1 (en) Memory dies, stacked memories, memory devices and methods
US8218346B2 (en) Multi-chip packages including extra memory chips to define additional logical packages and related devices
KR20180064734A (ko) 반도체 메모리 장치 및 이를 구비하는 메모리 모듈
US20130175681A1 (en) Chip package structure
US20200402959A1 (en) Stacked semiconductor package having an interposer
KR20170073004A (ko) 고속 신호 특성을 갖는 반도체 모듈
JP5511823B2 (ja) 半導体装置および電子装置
WO2021103642A1 (zh) 芯片组合及芯片
CN210640244U (zh) 芯片组合及芯片
US20210104486A1 (en) Multi-access memory system and a method to manufacture the system
TWI466247B (zh) 三維封裝結構
US20220375900A1 (en) Stacked semiconductor device
JP4175155B2 (ja) 半導体装置
TWI732647B (zh) 半導體封裝件
US20240021553A1 (en) Semiconductor device including two or more stacked semiconductor structures
TW202316606A (zh) 封裝裝置、記憶體裝置以及半導體裝置
KR20060074091A (ko) 칩 스택 패키지
WO2012021310A1 (en) Disaggregated semiconductor chip assembly and packaging technique

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20892133

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2020892133

Country of ref document: EP

Effective date: 20210907

NENP Non-entry into the national phase

Ref country code: DE