CN102422403B - 半导体元器件、半导体晶片元器件、半导体元器件的制造方法、及接合结构体的制造方法 - Google Patents

半导体元器件、半导体晶片元器件、半导体元器件的制造方法、及接合结构体的制造方法 Download PDF

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Publication number
CN102422403B
CN102422403B CN201080021256.0A CN201080021256A CN102422403B CN 102422403 B CN102422403 B CN 102422403B CN 201080021256 A CN201080021256 A CN 201080021256A CN 102422403 B CN102422403 B CN 102422403B
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knitting layer
protuberance
devices
semiconductor
face
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CN102422403A (zh
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北浦秀敏
古泽彰男
酒谷茂昭
中村太一
松尾隆广
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Panasonic Intellectual Property Management Co Ltd
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Abstract

本发明的半导体元器件(100)包括：半导体元件(101)；以及接合层(102)，该接合层(102)形成于半导体元件(101)的一个面上，由Bi为主要成分的接合材料构成，在接合层(102)的与半导体元件(101)相接的面的相反一侧的面上形成有凸部(103)。使用该半导体元器件(100)，使其与被配置成与接合层(102)彼此相对的电极(201)接合，从而能够抑制空隙的产生。

Description

半导体元器件、半导体晶片元器件、半导体元器件的制造方法、及接合结构体的制造方法
技术领域
本发明涉及在半导体元件的面上具有以Bi为主要成分的接合材料构成的接合层的半导体元器件、半导体晶片元器件、半导体元器件的制造方法、及接合结构体的制造方法。
背景技术
使用焊锡材料将半导体元器件安装于基板。例如，作为将IGBT(InsulatedGateBipolarTransistor，绝缘栅双极型晶体管)之类的半导体元器件和基板接合的焊锡材料，一般采用熔点为220℃的Sn-3重量％Ag-0.5重量％Cu。
图4是将半导体元器件安装于基板的示意图。将半导体元器件401安装于基板402时，采用焊锡浸渍式的浸入装置，例如用熔点为220℃的焊锡材料403(Sn-3重量％Ag-0.5重量％Cu)将半导体元器件401的外部电极404与基板电极405锡焊连接。此时，因为焊锡材料403被浸入装置加热至250～260℃，因此半导体元器件401的温度可达250～260℃。而半导体元器件401采用以下结构：即，半导体元件406和内部电极407通过接合材料408接合，如果接合材料408在半导体元器件401的内部熔融，则可能会发生短路、断路或电学特性的变化，最终产品发生缺陷。因此，对于在半导体元器件401的内部使用的接合材料408，要求具有比用浸入装置进行锡焊时达到的半导体元器件401内部的最高温度要更高的熔融温度。
因此，作为熔融温度超过260℃且不含铅的接合材料，考虑使用包含90重量％以上的Bi的接合材料(以下称作“以Bi为主要成分的接合材料”)(例如Bi-2.5Ag熔点262℃，Bi-0.5Cu熔点270℃)。作为其它接合材料，也对Zn进行了研究，但考虑到浸润性和接合的难易程度等，现在使用的是上述以Bi为主要成分的接合材料。于是，提出了使用以Bi为主要成分的接合材料的功率半导体模块(参照专利文献1)
图5(a)～图5(c)是用于说明专利文献1所记载的现有的接合结构体的制造过程中所产生的空隙的示意图。在图5(a)～图5(c)中，接合结构体501是将熔融后的以Bi为主要成分的接合材料502提供到电极503上(图5(a))，并在该接合材料502上安装半导体元件504(图5(b))以进行接合而成的结构体(图5(c))。
现有技术文献
专利文献
专利文献1：日本专利特开2007-281412号公报(第24页、图2)
发明内容
然而，专利文献1中的接合材料的主要成分即Bi的氧化物的标准生成能为-494kJ/mol，容易氧化。如上所述，为了形成接合结构体501，将以熔融后的Bi为主要成分的接合材料502提供给电极503，在该接合材料502上安装半导体元件504并进行接合。此时，在提供给电极503的以熔融状态的Bi为主要成分的接合材料502的表面，形成有因接触大气而自然地生成的氧化物505。
因此，在将半导体元件504安装到熔融状态的接合材料502的表面的情况下，氧化物505层在半导体元件504的表面浸润并扩散，最终移动到接合材料502的外周缘部。因而，如图5(b)的箭头所示那样，在存在有空气集聚的情况下，氧化物505层的一部分可能不会移动到接合材料502的外周部，而会残留。而且，该残留下的氧化物505层具有容易卷入空气的特性，因此，如图5(c)所示的那样，卷入到氧化物505层中的空气会作为空隙506而进入接合材料502中。此外，集中在接合材料502的外周缘部的氧化物505以大致均匀地覆盖该外周缘部的表面的方式进行分布。
在接合材料502中混入有空隙506的状态下，若因热循环而施加反复的应力，则会在凝固的接合材料502中发生裂纹，具有接合结构体501的半导体元器件会发生故障，从而产生问题。
本发明考虑了上述现有的半导体元器件的上述问题，其目的在于提供一种能够减少在由Bi为主要成分的接合材料构成的接合层中所产生的空隙的半导体元器件、使该半导体元器件与电极相接合的接合结构体、半导体晶片元器件、半导体元器件的制造方法、及接合结构体的制造方法。
本发明的第1发明为一种半导体元器件，包括：
半导体元件；以及
接合层，该接合层形成于上述半导体元件的一侧的面上，由Bi为主要成分的接合材料构成，
在上述接合层的与上述半导体元件相接的面相反一侧的面上形成有单个或多个凸部。
另外，本发明的第2发明在于，在本发明的第1发明的半导体元器件中，上述凸部的高度为5μm以上30μm以下。
另外，本发明的第3发明是一种半导体元器件的制造方法，包括：
接合层形成工序，该接合层形成工序在形成有多个半导体元件的半导体晶片的一侧的面上，使用以Bi为主要成分的接合材料来形成接合层；
掩膜配置工序，该掩膜配置工序将掩膜配置在上述接合层之上，上述掩膜在与上述半导体元件的各位置相对应的每个区域形成有单个或多个孔部；
凸部形成工序，该凸部形成工序使用与上述接合材料相同的材料或比上述接合材料的熔融开始温度要低的材料，来对配置有上述掩膜的上述接合层形成与上述孔部相对应的单个或多个凸部；以及
切断工序，该切断工序对在上述接合层上形成有上述凸部的上述半导体晶片进行切断。
另外，本发明的第4发明在于，在本发明的第3发明的半导体元器件的制造方法中，
上述孔部的上述掩膜的厚度对应于上述凸部的高度，
上述掩膜的与上述接合层相接的面上的上述孔部的开口部的尺寸比与上述开口部相对的相反一侧的开口部的尺寸要大。
另外，本发明的第5发明是一种接合结构体的制造方法，
是对上述第1或第2发明的半导体元器件和电极进行接合的接合结构体的制造方法，包括：
配置工序，该配置工序配置上述半导体元器件，使得上述接合层的形成有上述凸部的面与上述电极隔开规定的距离而彼此相对；
加热工序，该加热工序将上述电极加热到上述接合材料的熔融温度以上；以及
接合工序，该接合工序通过使上述半导体元器件向上述被加热的电极侧移动，并使上述凸部与上述电极的表面相接触，从而以上述凸部为起点使上述接合层开始熔融。
另外，本发明的第6发明是一种半导体晶片元器件，包括：
半导体晶片，该半导体晶片中形成有多个半导体元件；
接合层，该接合层形成于上述半导体晶片的形成有上述半导体元器件的面上，由Bi为主要成分的接合材料构成；以及
保护片材，该保护片材粘接在上述接合层上，
在上述接合层的上述保护片材侧的面的、与上述半导体元件的各位置相对应的每个区域中，形成有单个或多个凸部。
此外，上述本发明的相关发明是一种接合结构体，包括
半导体元件；
接合层，该接合层形成于上述半导体元件的一侧的面上，由Bi为主要成分的接合材料构成；以及
电极，该电极与上述接合层相对地接合，并在上述接合层侧的面上具有单个或多个凸部。
另外，本发明相关的其他发明是一种接合结构体的制造方法，
是与本发明相关的上述发明的接合结构体的制造方法，包括：
配置工序，该配置工序配置上述半导体元器件，使得上述接合层与上述电极的形成有上述凸部的面隔开规定的距离而彼此相对；
加热工序，该加热工序将上述电极加热到上述接合材料的熔融温度以上；以及
接合工序，该接合工序通过使上述半导体元器件向上述被加热的电极侧移动，并使上述凸部与上述接合层的表面相接触，从而以上述凸部为起点使上述接合层开始熔融。
根据上述本发明的结构，在半导体元件的一侧面上具有由Bi为主要成分的接合材料构成的接合层，例如，在接合层的与半导体元件相接的面的相反一侧的面上形成有凸部，从而在凸部的周围在与电极接合时形成空气的通道，从而能够抑制空气被Bi的氧化物围住即空隙的生成。
根据本发明，能够发挥在由Bi为主要成分的接合材料构成的接合层中降低空隙的发生的效果。
附图说明
图1(a)～(e)是表示本发明的实施方式1的半导体元器件的示意图。
图2(a)～(d)是表示对本发明的实施方式1的半导体元器件和引线框进行焊接的工序的图。
图3是表示空隙的发生率相对于凸部的高度的关系的图。
图4是将半导体元器件安装于基板的示意图。
图5(a)～(c)是用于说明在现有的接合结构体的制造过程中发生的空隙的示意图。
图6是用于说明本发明的实施方式1中的半导体元器件的制造方法中所使用的掩膜的简要剖视图。
图7是表示本发明的另一实施方式的接合结构体的电极结构的简要的剖视图。
附图标记
100半导体元器件
101半导体元件
102接合层
103凸部
104氧化物
201电极
202引线框
具体实施方式
下面，参照附图，说明本发明的实施方式。
(实施方式1)
图1(a)～图1(e)是表示本发明的实施方式1的半导体元器件的示意图。图1(a)、(e)是半导体元器件的剖视图，图1(b)、(c)及(d)是沿图1(a)的箭头方向来看半导体元器件时的接合层的俯视图。
在由Si构成的直径为6英寸且厚度为0.3mm的晶片(半导体晶片)上，以4.5mm×3.55mm的尺寸切下半导体元件101。半导体元件101不限于Si，也可以由Ge构成，还可以由作为化合物半导体的GaN、GaAs、InP、ZnS、ZnSe、SiC、SiGe等构成。此外，根据半导体元件101的功能的不同，半导体元件101的尺寸可以使用6mm×5mm的较大的尺寸，或者也可以使用3mm×2.5mm、2mm×1.6mm等较小的尺寸。半导体元件101的厚度不限于0.3mm，也可使用1.0mm、0.5mm、0.1mm、0.01mm等厚度。
接合层102由Bi-2.5重量％Ag(熔点262℃)形成，半球状的凸部103形成于接合层102的与半导体元件101相接侧相反一侧的面的中央部的一个部位，在接合层102和凸部103的与半导体元件101相反一侧的面上形成有因与大气接触而自然生成的氧化物104。
对于接合层102的厚度h，由于接合层102的主要成分即Bi的热传导率为9W/m·K，因此若接合层102过厚，则基于热电阻的观点无法满足半导体元器件的产品性能，但若过薄则会导致接合不良。如上所述，厚度h优选为大约10μm以上30μm以下。
对于凸部103的尺寸，以接合层102的、与半导体元件101相接侧相反一侧的面(在图1(a)中以标号P示出的位置相对应的平面P)，即，接合层102的、后述电极201(参照图2(a))侧的平面P为基准，形成为在法线方向上的最大高度m为10μm，在平面方向上的最大直径n为10μm的大致半球形形状。
此处，在形成凸部103之后，形成了因接触大气而自然生成的氧化物104的层，但是该氧化物104的层厚是大致均一的。因而，对于形成氧化物104的层之后的凸部103的高度，下文将以下述情况为前提进行说明，即，在以氧化物104的层在电极201侧的面(图1(a)中的标号Q表示的位置所对应的平面Q)为基准的情况下的高度、与在形成氧化物104之前的凸部103的高度(以上述平面P为基准的高度)相同。因此，下文中若无特别记载，凸部的高度是指以平面P为基准的、在法线方向上的最大高度。
此外，作为凸部103的形状，由于最好能确保在接合层102和后述的电极201(参照图2(b))之间存在空气的通道或能确保被卷入氧化物104中的空气的通道，因此，凸部103的形状也可以是在接合层102的与半导体元件101相接侧相反一侧的面上沿垂直方向形成为多角锥等形状。
接着，一边说明形成凸部103的方法，一边说明本发明的半导体元器件的制造方法的一个例子。
在接合层形成工序中，对形成有多个半导体元件的半导体晶片的主平面，利用电解镀敷法将以Bi为主要成分的接合材料构成的接合层102成膜为目标厚度。
之后，如图6所示，在掩膜配置工序中，在成膜后的接合层102上配置具有多个与凸部103的形状相对应的孔部的掩膜601。
此处，掩膜601的、与半导体晶片602的主面602a上形成有多个半导体元件的各位置相对应的每个区域中，形成有单个或多个孔部603。另外，如图6所示那样，孔部603的掩膜601的厚度601t对应于凸部103的高度。而且，掩膜601的与接合层102相接一侧的面上的孔部603的开口部603a的形状和尺寸对应于凸部103的根部的形状和尺寸，同一孔部603的与其开口部603a相对的相反侧的面的开口部603b的形状和尺寸对应于凸部103的前端形状和尺寸。
接着，在掩膜配置工序中，在配置了掩膜601之后，通过进行电解镀敷来将以Bi为主要成分的接合材料电解镀敷为凸部103的形状。若在进行电解镀敷之后，去除掩膜601，则在接合层102的与半导体元件101相接侧的相反一侧的面上形成有凸部103。
此外，通过对配置了掩膜601的半导体晶片602实施电解镀敷的时间进行控制，从而能够调整凸部103的高度。
接着，在形成有凸部103的半导体晶片602的主面602a侧粘接有作为保护片材的切割片。之后，在切割工序中，利用切割装置将半导体晶片602切割为规定的尺寸。此外，粘接有切割片的半导体晶片602是本发明的半导体晶片元器件的一个例子。
图1(b)是表示接合层的与半导体元件相接面的相反一侧的面的俯视图，通过将凸部103形成在一个部位，从而在与电极接合时，凸部103的周围成为空气的通道，能够防止在Bi的氧化物中有空气被围住即防止产生空隙。
图1(c)是表示接合层102的与半导体元件101相接面的相反一侧的面的俯视图，示出了在氧化物104的平面上在5个部位形成凸部103的状态。图1(c)所示的凸部103与相邻的其他凸部103的距离L如图1(e)所示那样，是以接合层102的与半导体元件101相接的面的相反一侧的面(氧化物104的表面)为基准来连接顶点间的距离。在图1(c)的情况下，对于凸部103的配置，在考虑相邻的凸部103彼此之间的距离L的情况下，对于离氧化物104的外周较近的凸部间距L，该距离L要设定得相对更长。
图1(d)是表示图1(c)所示的从凸部103开始熔融时接合层浸润并扩散的图。如上所述，通过将离开氧化物104的外周较近的凸部与相邻凸部之间的距离L设定得相对更长，从而在与电极201接合时，以凸部103为起点的熔融部向着外周部浸润扩散，在以凸部103为起点的熔融部的周围形成空气的通道，从而使得被Bi氧化物围住的空气的通道不会被封闭，从而能够防止空隙的产生。
图2是表示对本发明的实施方式1的半导体元器件和引线框进行焊接的工序的图。各图均表示剖面。
以下，参照图2来说明本发明的接合结构体的制造方法的一个例子。
图2(a)示出了将半导体元器件100靠近引线框202的电极201进行配置的配置工序的图。即，在该工序中，保持装置(省略图示)对半导体元器件100进行保持，使得形成有凸部103的接合层102的面与电极201隔开规定的距离而彼此相对。
另外，如图2(a)所示那样，大致半球状的凸部103形成于接合层102的电极201侧的一个面的中央部的一个部位，在接合层102的电极201侧的面上形成有因接触大气而自然生成的氧化物104。该图是示出将半导体元器件100与引线框202的电极201相接合之前的状态的图。
图2(b)是表示在将引线框202加热到接合层102的熔融开始温度即262℃以上的状态下、保持装置将半导体元器件100安装到电极201上的状态的示意图。
如图2(b)所示的那样，在使接合层102和电极201接合时，凸部103的氧化物104最先与电极201相接触，热从电极201通过氧化物104和凸部103而传至接合层102。由此，首先凸部103发生熔融，接着，与凸部103相接的接合层102熔融，熔融部位一边向外周部扩散一边完成接合。此外，保持装置保持半导体元器件100且根据该熔融部位的扩散状态而逐渐稍许向下方移动半导体元器件100。
由此，通过对接合层102的熔融的定时设置时差，从而如图2(c)那样，将氧化物104向接合层102的外周缘部挤出。
图2(d)是表示使半导体元器件和引线框接合的接合结构体的示意图。如图所示，氧化物104被挤出接合层102的外周缘部，向电极201侧的外周面102a移动，因而在接合层102中不存在氧化物104。因此，不会产生因卷入氧化物104而引起的空隙。
因而，根据本实施方式，存在于接合层102的外周缘部的氧化物具有以下特征：即，相比半导体元件101侧的外周缘部，氧化物更多地分布在电极201侧的外周缘部(相当于外周面102a的部分)。
根据该结构，在使用半导体元器件与电极相接合的情况下，在凸部的周围形成空气的通道，能够抑制或防止空气被Bi的氧化物围住即抑制或防止空隙的生成，上述半导体元器件包括：半导体元件；以及在上述半导体元件的一侧面上以Bi为主要成分的接合材料构成的接合层，上述接合层的与上述半导体元件相接的面的相反一侧的面上形成有凸部。
(实施方式2)
在上述实施方式1中的半导体元器件中，在接合层的与半导体元件相接的面的相反一侧的面上形成有凸部103，将该凸部103的尺寸形成为以平面P(参照图1(a))为基准，在法线方向上的最大高度m为10μm、在平面方向上的最大直径n为10μm的大致半球形形状。
然而，由于考虑到若凸部的高度太低则会导致空气的通道容易闭合，因此，对凸部的高度和是否有空隙发生进行验证。
图3是表示空隙的发生率相对于凸部的高度的关系图。本次实验中，将凸部设置于接合层的中央部的一个部位。
空隙的发生率(％)可表示为：
空隙的发生率(％)＝(空隙的面积)÷(接合材料表面积)×(100)(％)
此外，空隙的面积是利用透射X射线装置对使用半导体元器件进行接合组装而成的IGBT进行测量的。
基于图3的结果可知，在凸部高度为5μm的情况下，空隙的发生率为0％，可知通过设置凸部能够获得良好的防止空隙产生的效果。另一方面，在凸部高度为3μm时，空隙发生率为24％，不能防止空隙的发生。其原因在于，因为凸部会发生熔融，之后，接合层也会发生熔融，从而与电极相接合，但是若凸部的高度不够，则在去除空隙之前接合层就已熔融并与电极相接合，因而封闭了去除空隙的通路，因此，会成为在焊料中仍残留有空隙的状态。另外，在凸部高度为4μm时，成为在焊料中稍许残留有部分空隙的状态。
另一方面，在凸部高度为25μm的情况下，空隙发生率为0％，但对凸部的高度比25μm更高的情况进行说明。
例如，在凸部的高度为30μm时，空隙发生率为0％，但是若凸部高度超过30μm，则如上所述，在切断工序中，为了利用切割装置对半导体晶片进行加工，需要将半导体晶片粘接至切割片，此时，在切割片和粘接至切割片的接合层102的粘接面之间会因凸部103的存在而产生气泡。若在该状态下进行切割则切割所带来的切割废料会进入气泡中，污染接合层表面，并会发生接合不良，因此，优选凸部高度不超过30μm的高度。根据该结果，优选凸部高度为5μm以上30μm以下。
接着，在上述验证中使用的是Bi-2.5重量％Ag并且使用半导体元器件，但是也针对其他接合材料成分对凸部的有效性进行了验证。
表1是改变接合层的种类、凸部的高度、凸部的数量来对空隙发生率进行测量的结果。此外，作为参考，还验证了不具有凸部的情况(比较例1)。
[表1]
从该表1中可知，在使用Bi-1.0重量％Ag-0.5重量％Cu、100重量％Bi的情况下，空隙发生率为0％。由此，可知作为接合材料，只要是以Bi为主要成分的接合材料即可。若凸部高度为5μm以上30μm以下，则空隙发生率为0％，而且不会受到凸部的数量的影响，只要满足上述的配置条件，则空隙率为0％。另外，在没有凸部的比较例1中，空隙发生率为39％，不能作出质量稳定的结论。
根据该结构，在使用半导体元器件与电极相接合的情况下，在凸部的周围形成空气的通道，能够防止空气被Bi的氧化物围住即防止空隙的生成，上述半导体元器件包括：半导体元件；以及在上述半导体元件的一侧面上以Bi为主要成分的接合材料构成的接合层，上述接合层的与上述半导体元件相接的面的相反一侧的面上形成有高度为5μm以上30μm以下的凸部。
此外，由于在凸部的周围形成空气通道，以防止空气被Bi的氧化物围住即防止空隙的产生，因此，认为用于防止空隙产生的凸部的尺寸、凸部的体积也是相关的。其原因在于，只有在凸部的周围保持一定的体积空间才能形成空气的通道。
另外，在上述实施方式中，围绕着凸部103的数量为一个的情况进行了说明，但并不限于此，例如也可以设置多个凸部103。特别若采用形成3个以上的凸部103、对半导体元件101进行支撑的结构时，则在将半导体元器件100安装到电极上时，能够防止半导体元器件100发生倾斜。
另外，在上述实施方式中，对凸部103的材料使用了与接合层102的成分相同的材料的情况进行了说明，但是并不限于此，对于凸部103的材料，即使是使用成分不同于接合层102的材料，只要是熔点为接合层102的材料的熔融开始温度以下的材料即可。例如，作为凸部103的材料，还能使用Bi-Sn合金(熔融开始温度：139℃)、Sn-In合金(熔融开始温度：120℃)、或Bi-In合金(熔融开始温度：73℃)等。由此，能够确保从凸部103开始发生熔融。
另外，在上述实施方式中，对在接合层102的面的一部分形成凸部103的情况进行了说明，但是并不限于此，也可在接合层102的电极201侧的整个面上形成具有以该面的中央为顶点的四角锥形形状或圆锥形形状等锥形。在这种情况下，接合层102的电极201侧的面向着外周侧倾斜，因此，在发生熔融的定时中会产生时差，并能确保去除空气的通道，因此，也能发挥与上述相同的效果。
另外，在上述实施方式中，对保持装置保持半导体元器件100且根据熔融部位的扩散状态而逐渐稍许向下移动半导体元器件100的结构进行了说明，但是并不限于此，例如，也可采用在保持装置将半导体元器件100安装到电极201上之后，解除保持的结构。在这种情况下，半导体元器件100因其自重而逐渐稍许向下方移动。
另外，在上述实施方式中，对将凸部设置于接合层的表面的情况进行了说明，但并不限于此，例如也可采用在电极的表面设置单个或多个凸部的结构。在这种情况下，能够利用冲压金属膜对电极进行按压而简单地在电极上形成凸部。图7是简要表示接合结构体703的剖面示意图，该接合结构体703包括：半导体元件101；接合层102，该接合层102形成于半导体元件101的一侧的面上，由Bi为主要成分的接合材料构成；电极702，该电极702与接合层102彼此相对地接合，且在接合层102一侧的面的中央具有一个凸部701；以及引线框202。此外，对于与图2(d)相同的部分附加了相同标号。即，在采用图7的结构的情况下，未在接合层102形成图2(a)所说明的凸部103，相反，而是在电极702侧形成凸部701。
另外，图7所示的接合结构体703的制造方法包括：配置工序，该配置工序配置半导体元器件100，使得接合层102与形成有凸部701的电极702的面隔开规定的距离而彼此相对；加热工序，该加热工序将电极702加热到接合层102的以Bi为主要成分的接合材料的熔融温度以上；以及接合工序，该接合工序通过使半导体元器件100向被加热的电极侧移动，并使凸部701与自然形成有氧化物的接合层102的表面相接触，从而以凸部701为起点使接合层开始熔融。与图2所说明的接合结构体的制造方法基本相同。因而，在这种情况下，也与上述相同，接合层102的氧化物发生熔融的定时中会产生时差，并能确保去除空气的通道，因此，也能发挥与上述相同的效果。
工业中的应用
本发明的半导体元器件、接合结构体、半导体晶片元器件、半导体元器件的制造方法、及接合结构体的制造方法能够减少在由Bi为主要成分的接合材料构成的接合层中所产生的空隙，因此，能够应用到功率半导体、小功率晶体管等半导体封装体中。

Claims (5)

1.一种半导体元器件，其特征在于，包括：
半导体元件，该半导体元件的宽度为1.6mm～5mm；以及
接合层，该接合层形成于所述半导体元件的一侧的面上，由Bi为主要成分的接合材料构成，且该接合层的宽度与所述半导体元件的所述宽度相等，
在所述接合层的与所述半导体元件相接的面相反一侧的面上形成有凸部，
所述凸部是最大直径为10μm、高度为5μm以上30μm以下的半球状，且由与所述接合层相同的材料构成。
2.一种半导体元器件的制造方法，其特征在于，包括：
接合层形成工序，该接合层形成工序在形成有多个宽度为1.6mm～5mm的半导体元件的半导体晶片的一侧的面上，使用以Bi为主要成分的接合材料来形成接合层；
掩膜配置工序，该掩膜配置工序将掩膜配置在所述接合层之上，所述掩膜在与所述半导体元件的各位置相对应的每个区域形成有孔部；
凸部形成工序，该凸部形成工序使用与所述接合材料相同的材料或比所述接合材料的熔融开始温度要低的材料，来对配置有所述掩膜的所述接合层形成与所述孔部相对应的凸部，所述凸部是最大直径为10μm、高度为5μm以上30μm以下的半球状；以及
切断工序，该切断工序对在所述接合层上形成有所述凸部的所述半导体晶片进行切断。
3.如权利要求2所述的半导体元器件的制造方法，其特征在于，
所述孔部的所述掩膜的厚度对应于所述凸部的高度，
所述掩膜的与所述接合层相接的面上的所述孔部的开口部的尺寸比与所述开口部相对的相反一侧的开口部的尺寸要大。
4.一种接合结构体的制造方法，
是对权利要求1的半导体元器件和电极进行接合的接合结构体的制造方法，其特征在于，包括：
配置工序，该配置工序配置所述半导体元器件，使得所述接合层的形成有所述凸部的面与所述电极隔开规定的距离而彼此相对；
加热工序，该加热工序将所述电极加热到所述接合材料的熔融开始温度以上；以及
接合工序，该接合工序通过使所述半导体元器件向所述被加热的电极侧移动，并使所述凸部与所述电极的表面相接触，从而以所述凸部为起点使所述接合层开始熔融。
5.一种半导体晶片元器件，包括：
半导体晶片，该半导体晶片中形成有多个宽度为1.6mm～5mm半导体元件；
接合层，该接合层形成于所述半导体晶片的形成有所述半导体元器件的面上，由Bi为主要成分的接合材料构成；以及
保护片材，该保护片材粘接在所述接合层上，
在所述接合层的所述保护片材侧的面的、与所述半导体元件的各位置相对应的每个区域中，形成有凸部，所述凸部是最大直径为10μm、高度为5μm以上30μm以下的半球状，且由与所述接合层相同的材料构成。
CN201080021256.0A 2009-07-24 2010-07-20 半导体元器件、半导体晶片元器件、半导体元器件的制造方法、及接合结构体的制造方法 Expired - Fee Related CN102422403B (zh)

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JPH07263469A (ja) * 1994-03-24 1995-10-13 Sansha Electric Mfg Co Ltd 半導体装置
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