JP5533223B2 - 接合材料およびその製造方法、半導体装置およびその製造方法 - Google Patents
接合材料およびその製造方法、半導体装置およびその製造方法 Download PDFInfo
- Publication number
- JP5533223B2 JP5533223B2 JP2010110187A JP2010110187A JP5533223B2 JP 5533223 B2 JP5533223 B2 JP 5533223B2 JP 2010110187 A JP2010110187 A JP 2010110187A JP 2010110187 A JP2010110187 A JP 2010110187A JP 5533223 B2 JP5533223 B2 JP 5533223B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- based layer
- semiconductor element
- bonding
- bonding material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Description
Claims (10)
- Alを主成分として含有した金属からなるAl系層を中央層とし、第1のX系層および第2のX系層によって前記Al系層を挟持し、さらにZnを主成分として含有した金属からなる第1のZn系層および第2のZn系層によって前記第1のX系層および第2のX系層を挟持した層構造を有するクラッド材であり、前記第1のX系層および前記第2のX系層は、Ge、Mg、In、Sn、Ag、Au、Gaのいずれかを主成分Xとして含有した金属からなる層であり、
前記Zn系層におけるZnの含有率、前記X系層におけるXの含有率、前記Al系層におけるAlの含有率は、それぞれ90wt.%乃至100wt.%であり、
前記第1のX系層および前記第2のX系層の厚さは0.5μm以上、50μm以下であり、前記層構造の総厚は20μm以上、300μm以下であることを特徴とする接合材料。 - 請求項1に記載のX系層は、Geを含むことを特徴とする接合材料。
- 請求項1に記載のX系層は、Mgを含むことを特徴とする接合材料。
- 請求項1に記載のX系層は、Inを含むことを特徴とする接合材料。
- 請求項1に記載のX系層は、Snを含むことを特徴とする接合材料。
- 請求項1に記載のX系層は、Agを含むことを特徴とする接合材料。
- 請求項1に記載のX系層は、Auを含むことを特徴とする接合材料。
- Alを主成分として含有した金属からなるAl系層を中央層とし、第1のX系層および第2のX系層によって前記Al系層を挟持し、さらにZnを主成分として含有した金属からなる第1のZn系層および第2のZn系層によって前記第1のX系層および第2のX系層を挟持した層構造を有するクラッド材であり、前記第1のX系層および前記第2のX系層は、Ge、Mg、In、Sn、Ag、Au、Gaのいずれかを主成分Xとして含有した金属からなる層であり、前記Zn系層におけるZnの含有率、前記X系層におけるXの含有率、前記Al系層におけるAlの含有率は、それぞれ90wt.%乃至100wt.%であり、前記第1のX系層および前記第2のX系層の厚さは0.5μm以上、50μm以下であり、前記層構造の総厚は20μm以上、300μm以下である接合材料の製造方法であって、
前記Al系層を前記第1のX系層および第2のX系層によって挟んでクラッド圧延を行って、積層材を製作する工程と、前記積層材を前記第1のZn系層および第2のZn系層によって挟んでクラッド圧延を行って、前記層構造を製作する工程と含むことを特徴とする接合材料の製造方法。 - 半導体素子と、前記半導体素子を接合するフレームと、一端が外部端子となるリードと、前記リードの他端と前記半導体素子の電極とを接合するワイヤと、前記半導体素子および前記ワイヤを樹脂封止するレジンとを有し、
前記半導体素子と前記フレームとの接合部は、請求項1乃至7のいずれか1項に記載の接合材料を溶融することによって形成され、
前記接合部のボイド率が10wt.%以下であることを特徴とする半導体装置。 - 半導体素子と、前記半導体素子を接合するフレームと、一端が外部端子となるリードと、前記リードの他端と前記半導体素子の電極とを接合するワイヤと、前記半導体素子および前記ワイヤを樹脂封止するレジンとを有する半導体装置の製造方法であって、
前記半導体素子と前記フレームとを、請求項1乃至7のいずれか1項に記載の接合材料を溶融して接合する工程を含むことを特徴とする半導体装置の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010110187A JP5533223B2 (ja) | 2010-05-12 | 2010-05-12 | 接合材料およびその製造方法、半導体装置およびその製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010110187A JP5533223B2 (ja) | 2010-05-12 | 2010-05-12 | 接合材料およびその製造方法、半導体装置およびその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2011238838A JP2011238838A (ja) | 2011-11-24 |
JP5533223B2 true JP5533223B2 (ja) | 2014-06-25 |
Family
ID=45326472
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010110187A Expired - Fee Related JP5533223B2 (ja) | 2010-05-12 | 2010-05-12 | 接合材料およびその製造方法、半導体装置およびその製造方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP5533223B2 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP2992553A4 (en) | 2013-05-03 | 2017-03-08 | Honeywell International Inc. | Lead frame construct for lead-free solder connections |
JP2017509489A (ja) | 2014-02-20 | 2017-04-06 | ハネウェル・インターナショナル・インコーポレーテッド | 鉛フリーはんだ組成物 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010073908A (ja) * | 2008-09-19 | 2010-04-02 | Hitachi Ltd | 半導体装置およびその製造方法 |
JP5152125B2 (ja) * | 2009-08-12 | 2013-02-27 | 株式会社日立製作所 | 接続材料、接続材料の製造方法、および半導体装置 |
JP2011056222A (ja) * | 2009-09-09 | 2011-03-24 | Izumi Shoji:Kk | 洋式トイレ便座 |
-
2010
- 2010-05-12 JP JP2010110187A patent/JP5533223B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2011238838A (ja) | 2011-11-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5601275B2 (ja) | 接合材料、その製造方法、および接合構造の製造方法 | |
JP4390799B2 (ja) | 接続材料、接続材料の製造方法、および半導体装置 | |
KR101722893B1 (ko) | Cu/세라믹스 접합체, Cu/세라믹스 접합체의 제조 방법, 및 파워 모듈용 기판 | |
JP6111764B2 (ja) | パワーモジュール用基板の製造方法 | |
JP5725060B2 (ja) | 接合体、パワーモジュール用基板、及びヒートシンク付パワーモジュール用基板 | |
WO2014148425A1 (ja) | 接合体の製造方法及びパワーモジュール用基板の製造方法 | |
JP2006108604A (ja) | 半導体装置およびその製造方法 | |
JP5725061B2 (ja) | パワーモジュール用基板、及びヒートシンク付パワーモジュール用基板 | |
JP2013176780A (ja) | 接合材料、その製造方法、および接合構造の製造方法 | |
JP5533223B2 (ja) | 接合材料およびその製造方法、半導体装置およびその製造方法 | |
JP2009285732A (ja) | 接続材料、接続材料の製造方法、および半導体装置 | |
KR20180104659A (ko) | 접합체, 파워 모듈용 기판, 접합체의 제조 방법 및 파워 모듈용 기판의 제조 방법 | |
JP5738523B2 (ja) | 接続材料、接続方法及び半導体装置の製造方法 | |
JP2013146764A (ja) | 接続材料及びそれを用いたはんだ付け製品 | |
WO2011030517A1 (ja) | 接続材料、半導体装置及びその製造方法 | |
KR102524698B1 (ko) | 접합체, 파워 모듈용 기판, 파워 모듈, 접합체의 제조 방법 및 파워 모듈용 기판의 제조 방법 | |
JP5723523B2 (ja) | 接続材料、接続材料の製造方法、半導体装置、半導体装置の製造方法、パワーモジュール | |
JP5251849B2 (ja) | 接続材料および半導体装置の製造方法 | |
JP5821991B2 (ja) | 半導体モジュール及び接合材料 | |
JP2014184446A (ja) | 積層接合材料およびそれを用いて接合した接合体 | |
JP6299442B2 (ja) | パワーモジュール | |
JP6078577B2 (ja) | 接続材料、接続方法、半導体装置及び半導体装置の製造方法 | |
JP5604995B2 (ja) | 半導体装置の製造方法 | |
JP2007222939A (ja) | ロウ材シートおよびその製造方法ならびに電子部品用パッケージ | |
JP2011189399A (ja) | 接続材料の製造方法、接続材料及びそれを用いた半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20120622 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20130621 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20130702 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130822 |
|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A712 Effective date: 20131128 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20140401 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5533223 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20140414 |
|
LAPS | Cancellation because of no payment of annual fees |