CN102412262A - 功率用半导体器件 - Google Patents

功率用半导体器件 Download PDF

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CN102412262A
CN102412262A CN2011102734646A CN201110273464A CN102412262A CN 102412262 A CN102412262 A CN 102412262A CN 2011102734646 A CN2011102734646 A CN 2011102734646A CN 201110273464 A CN201110273464 A CN 201110273464A CN 102412262 A CN102412262 A CN 102412262A
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semiconductor layer
layer
conductive layer
groove
semiconductor device
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川口雄介
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Toshiba Corp
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Toshiba Corp
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Abstract

本发明提供功率用半导体器件，包括：包含纵式MOSFET的元件部和与元件部邻接的二极管部，该纵式MOSFET包括：第一导电型的第一半导体层；第一导电型的第二半导体层；第二导电型的第三半导体层；第一导电型的第四半导体层；第二导电型的第五半导体层；覆盖从第四半导体层或第五半导体层的表面起贯穿第三半导体层直到第二半导体层的多个沟槽的内表面的绝缘膜；邻接的沟槽以第一间隔设置；第一埋入导电层；第二埋入导电层；层间绝缘膜；第一主电极以及第二主电极，该二极管部包括第一半导体层至第三半导体层、第五半导体层、绝缘膜、第一埋入导电层及第二埋入导电层、层间绝缘膜以及第一主电极及第二主电极，邻接的沟槽以第二间隔设置。

Description

功率用半导体器件
该申请基于并主张2010年9月17日在日本申请的、申请号为特愿2010-209160的在先专利申请的优先权，在先申请的全部内容包含于本申请中。
技术领域
本发明的实施方式涉及一种功率用半导体装置。
背景技术
涉及含有MOSFET(Metal Oxide Silicon Field Effect Transistor：金属氧化物半导体场效应晶体管)的功率用半导体装置的利用，除大电流、高耐压的开关电源市场之外，近年来，在笔记本式PC等移动通信设备的节能用开关市场中也急剧增加。功率用半导体装置使用于电源管理电路、锂离子电池的安全电路等。因此，功率用半导体装置设计为实现通过电池电压能够直接驱动的低电压驱动化、低导通电阻化、以及栅极漏极间电容降低等。
例如，与沟槽栅(trench gate)结构的n沟道MOSFET的低导通电阻化相对，缩小沟槽间距的技术是已知的。在缩小了沟槽间距的MOSFET中，连接到源电极的n+型源极层及p+型接触层中的p+型接触层难以确保足够的用于连接的接触面积。
因此，难以将连接到p+型接触层的p型基极层的电位固定到源极电位，发生半导体装置的雪崩耐受量低下的问题。
例如，感应性负荷的开关动作关闭时，当由感应电动势的影响引起的浪涌电压(surge voltage)超过了MOSFET的耐压的情况下，会发生雪崩击穿。所谓雪崩耐受量，是指抗雪崩击穿的能力。
当p型基极层的电位没有完全固定到源极电位的情况下，由雪崩击穿生成的空穴作为电流流动到源电极时，会通过n+型源极层的下方。这时，在源电极和p型基极层之间产生电位差，寄生在MOSFET的npn双极型晶体管会导通。其结果，该电流集中，MOSFET变得易于被破坏。
发明内容
根据一实施例，半导体装置具有：包含纵式MOSFET的元件部；以及与所述元件部邻接的二极管部；该纵式MOSFET包括：第一导电型的第一半导体层；第一导电型的第二半导体层，与在所述第一半导体层的第一主面上形成的所述第一半导体层相比杂质浓度低；第二导电型的第三半导体层，在所述第二半导体层的表面上形成；第一导电型的第四半导体层，在所述第三半导体层的表面上选择性地形成；第二导电型的第五半导体层，在所述第三半导体层的表面上选择性地形成；绝缘膜，覆盖从所述第四半导体层或第五半导体层的表面起贯穿所述第三半导体层直到所述第二半导体层的多个沟槽的内表面，邻接的所述沟槽以第一间隔设置；第一埋入导电层，隔着所述绝缘膜被埋入到所述沟槽内的底部；第二埋入导电层，隔着所述绝缘膜被埋入到所述沟槽内的所述第一埋入导电层上部；层间绝缘膜，在所述第二埋入导电层上形成；第一主电极，在与所述第一主面相反一侧的所述第一半导体层的第二主面上形成并且电连接到所述第一半导体层；以及第二主电极，在所述第四及第五半导体层以及所述层间绝缘膜上形成并且电连接到所述第四及第五半导体层；该二极管部包括：所述第一半导体层至所述第三半导体层、所述第五半导体层、覆盖所述多个沟槽的内表面的所述绝缘膜、所述第一埋入导电层及第二埋入导电层、所述层间绝缘膜以及所述第一主电极及所述第二主电极，邻接的所述沟槽以比所述第一间隔大的第二间隔设置。
本实施例提供抑制步骤的增加并且能够提高雪崩耐受量的半导体装置。
附图说明
图1是示意性地表示第一实施方式涉及的半导体装置的结构的图，(a)是俯视图，(b)是剖视图。
图2是说明第一实施方式涉及的半导体装置的结构的模式图。
图3是示意性地表示第二实施方式涉及的半导体装置的结构的剖视图。
图4是示意性地表示第二实施方式的变形例涉及的半导体装置的结构的剖视图。
具体实施方式
以下，参照附图对本发明的实施方式进行说明。在各图中，对于同一构成要素标注同一标号。另外，在半导体装置中，设源电极侧为上侧，设漏电极侧为下侧。
(第一实施方式)
参照图1及图2对本发明的实施方式涉及的半导体装置进行说明。图1(a)表示除去图1(b)所示的上端(纸面上部)两层后的状态的俯视图，图1(b)是沿着图1(a)所示的A-A线的剖视图。
如图1所示，半导体装置1具有：元件部，含有具有n沟道型的纵式MOSFET的区域；以及二极管部，与元件部相邻，含有具有二极管的区域。在图1中，纸面左侧是元件部，与元件部相连纸面右侧是二极管部。
元件部具有n+型半导体基板11，该n+型半导体基板11例如含有单晶硅，并作为第一导电型的第一半导体层。在n+型半导体基板11的第一主面(上表面)上具有n-型漂移层12，该n-型漂移层12与n+型半导体基板11相比杂质浓度低，并作为外延生长出的第一导电型的第二半导体层。在n-型漂移层12的表面，选择性地具有p-型基极层13，该p-型基极层13例如作为注入了p型杂质后的第二导电型的第三半导体层。在p-型基极层13的表面，选择性地具有n+型源极层14，该n+型源极层14作为注入了n型杂质后的第一导电型的第四半导体层，以及在p-型基极层13的表面，选择性地具有p+型接触层15，该p+型接触层15作为注入了p型杂质后的第二导电型的第五半导体层。
如图1(a)所示，n+型源极层14和p+型接触层15以在与A-A线垂直的方向上交替出现的方式排列。为了尽量降低半导体装置1的导通电阻，俯视图上的n+型源极层14的面积比p+型接触层15的面积大。
如图1所示，元件部设置了从n+型源极层14或p+型接触层15的表面起贯穿p-型基极层13直到n-型漂移层12的多个沟槽16。沟槽16沿着A-A线以成为设计规则的最小尺寸的一定的开口宽度以及反复间隔(间距31)排列。沟槽16在沿着沟槽16的并列方向(A-A线)的剖面上为U字形，在俯视时在与A-A线垂直的方向较长地延伸。
在沟槽16的内表面设置了例如含有硅氧化膜的绝缘膜17。隔着绝缘膜17在沟槽16内的底部，即n-型漂移层12侧设置有源极埋入电极18，该源极埋入电极18例如作为含有导电性多晶硅的第一埋入导电部件。
另外，隔着绝缘膜17在沟槽16内的源极埋入电极18的上部，即n+型源极层14或p+型接触层15侧，埋入了栅电极19，该栅电极19例如作为含有导电性的多晶硅的第二埋入导电部件。至少从相当于p-型基极层13的底面的位置达到相当于p-型基极层13的上表面的位置。由此，栅电极19能够在沟槽16侧面的p-型基极层13上形成沟道。源极埋入电极18和栅电极19通过绝缘膜17而分离。由于源极埋入电极18的宽度(沿着A-A线的方向的尺寸)比栅电极19的宽度小，所以源极埋入电极18侧面的绝缘膜17设置得比栅电极19侧面的绝缘膜17厚。另外，也可以使源极埋入电极18的宽度和栅电极19的宽度相同。
在栅电极19上，与绝缘膜17相连地设置着例如硅氧化膜的层间绝缘膜20。栅电极19由绝缘膜17及层间绝缘膜20围绕着。
在n+型半导体基板11的与第一主面相反一侧的第二主面(下表面)上，设置着电连接的、例如作为含有金属的第一主电极的漏电极21。设置着源电极22，该源电极22在n+型源极层14、p+型接触层15以及层间绝缘膜20上形成，电连接到n+型源极层14以及p+型接触层15，例如作为含有金属的第二主电极。
二极管部具有n+型半导体基板11、n-型漂移层12、p-型基极层13以及p+型接触层15这四层。二极管部成为将p+型接触层15设置到p-型基极层13上的结构，没有存在于元件部的n+型源极层14。此四层是元件部中的对应的四层分别连续地延长的层。因此，使用与元件部共通的名称。对于后述的其它的构成要素，在从元件部起连续地延长或以相同步骤形成的情况下，也使用与元件部共通或类似的名称。其结果，在二极管部，构成要素的名称有时未必表示功能。另外，在元件部和二极管部的边界部，沟槽16以及其中的构成要素被共有。
二极管部的沟槽16具有与元件部的沟槽16相同的形状，沟槽16中的绝缘膜17、源极埋入电极部件18a以及栅电极部件19a分别与元件部的沟槽16中的绝缘膜17、源极埋入电极18以及栅电极19相对应，具有相同的结构。
二极管部的沟槽16的间距32比元件部的沟槽16的间距31大。二极管部的沟槽16的间距32如后述那样，以元件部的沟槽16的间距31为基准，由二极管的耐压决定。
二极管部的源电极22成为阳极，漏电极21成为阴极。
源电极22省略了图示，与源极埋入电极18以及源极埋入电极部件18a连接。另外，如上述那样，在元件部，源电极22以相对较大的面积与n+型源极层14具有低阻抗地接触，另一方面，以相对较小的面积与p+型接触层15具有低阻抗地接触。在二极管部，源电极22与p+型接触层15具有低阻抗地接触。栅电极19以及栅电极部件19a省略了图示，和设置在半导体装置1的表面的外部连接用的栅电极连接。
接下来，对元件部的间距31和二极管部的间距32之间的关系进行说明。元件部提高MOSFET的沟道的密度，来实现低导通电阻化。为了提高沟道密度，以设计规则的最小尺寸设置沟道。即，在沟槽结构的纵式MOSFET中，因为沟道在沟槽的侧面形成，所以沟道的高密度化等同于提高沟槽的密度。沟槽的开口宽度以及反复间隔(间距)基于设计规则的最小尺寸而设计。
在图2中，以沟槽16的间距为横轴，以耐压为纵轴，示出了在沟槽16内具有含有源极埋入电极18及栅电极19的两段电极结构的元件部的沟槽16的间距和耐压之间的关系。以设计规则的最小尺寸决定元件部的沟槽16的间距31，接着，依据此间距31，决定耐压变为最大的沟槽16周边的n-型漂移层12等的半导体层的膜厚以及杂质浓度等。
其结果，如图2所示，通过元件部的沟槽16的间距31，耐压变为最大。如果变更沟槽16的间距则耐压减少，但因为元件部的沟槽16的间距31是设计规则的最小尺寸，所以二极管部的沟槽16的间距只能朝较大一方变更。而且，在超过半导体装置1所要求的耐压的标准值的范围内，决定具有在元件部之前开始雪崩击穿的电压的二极管部的耐压。此时的沟槽16的间距变为间距32。例如，如朝向下方的箭头那样，二极管部的耐压设定得比元件部的耐压低1V～数V。
在半导体装置1中，并不限定二极管部相对于元件部的平面分布。例如，在俯视时，二极管部可以位于半导体装置1的中央部、周边部、它们的中间部，也能够分布在多个地方。二极管部可将间距32设定为最小限度的宽度，也可以设定为多个连续的宽度。俯视的二极管部的分布面积可以根据需要决定。
接下来，对半导体装置1的制造步骤进行说明。在n+型半导体基板11上外延生长n-型漂移层12时，在元件部和二极管部之间，制造步骤没有不同的地方。在n-型漂移层12上通过离子注入法来形成p-型基极层13时，在元件部和二极管部之间，制造步骤没有不同的地方。通过离子注入法形成n+型源极层14及p+型接触层15时，俯视的分布不同。即，虽然在二极管部形成p+型接触层15，但是由于与元件部的p+型接触层15同时形成，所以能够通过掩摸图案的变更来对应，在元件部和二极管部之间，制造步骤没有不同的地方。
沟槽16及沟槽16内的结构在元件部和二极管部中是相同的，沟槽16的间距31、32不同。由于能够通过掩摸图案的变更来对应间距31、32的差异，因此，在元件部和二极管部之间，制造步骤没有不同的地方。同样地，层间绝缘膜20的间距的差异能够通过掩摸图案的变更来对应。以后的漏电极21及源电极22等的制造步骤，因为在俯视的分布上没有差异，所以在元件部和二极管部之间，没有不同的地方。
对于元件部和二极管部，虽然由于俯视的图案不同需要变更掩摸图案，但是因为在剖面方向即在深度方向的图案相同，所以即使追加二极管部，也能够不追加元件部的制造步骤之外的额外的制造步骤而制造半导体装置1。
接下来，对半导体装置1的感应性负荷的开关动作关闭时的动作进行说明。
如上所述，二极管部的沟槽16的间距32形成得比元件部的沟槽16的间距31大。因为在两个部分中，沟槽16是相同的尺寸，所以邻接的沟槽16之间的距离在二极管部变得更大。其结果，二极管部的n-型漂移层12由于比元件部的n-型漂移层12难以耗尽化，因此耐压降低，雪崩击穿开始的电压降低。
如果在漏电极21和源电极22之间施加超过耐压的电压，则在元件部发生故障之前，在耐压低的二极管部发生雪崩击穿。雪崩击穿时，电流的大部分流入到二极管部。因为在元件部电流几乎不流动，所以寄生npn双极型晶体管变得难以导通。在不能获得p+型接触层15和源电极22之间的较大的接触面积的情况下，由于抑制了寄生npn双极型晶体管的导通，因此抑制了破坏，能够增大雪崩耐受量。
另外，半导体装置1在元件部的开关动作接通时，能够使导通电阻比较低。在元件部的沟槽16内具有含有源极埋入电极18及栅电极19的两段电极结构。耗尽层从p-型基极层13及两侧的沟槽16侧延伸，而且，间距31窄，所以n-型漂移层12变得易于耗尽化。因此，漏电极21和源电极22之间的耐压变高。其结果，沟槽内的电极与具有通常结构(一段电极结构)的半导体装置相比，n-型漂移层12能够提高杂质浓度，能够使导通电阻更低。
(第二实施方式)
参照图3对本发明的实施方式涉及的半导体装置进行说明。图3是与图1(b)对应的剖视图。相对于第一实施方式的半导体装置1，不同的是在沟槽内以底部设置宽度较窄的阶梯结构的栅电极。另外，对与第一实施方式相同的构成部分标注相同的标号，并省略其说明。
如图3所示，半导体装置2在元件部设置有栅电极25，该栅电极25隔着沟槽16内表面的绝缘膜17从沟槽16上部到底部，并且例如含有导电性的多晶硅。在二极管部，与栅电极25同样地，设置有栅电极部件25a。半导体装置2的其它的结构与第一实施方式的半导体装置1相同。
栅电极25在上端侧在沟槽16的并列方向上的宽度较宽，在下端侧在沟槽16的并列方向上的宽度较窄。上端侧的宽度较宽的栅电极25为了能够在沟槽16的侧面的p-型基极层13上形成沟道，至少从与p-型基极层13的底面相当的位置到达与p-型基极层13的上表面相当的位置。下端侧的栅电极25在沟槽16的并列方向上的宽度几乎均等地狭窄并以与上端侧的栅电极25成为一体的方式连续。沟槽16的内侧侧面的绝缘膜17的厚度，在上端侧较薄，在下端侧较厚。
在上端侧宽度较宽且在底部侧宽度较窄的阶梯结构的栅电极25，和含有第一实施方式的源极埋入电极18及栅电极19的两段电极结构同样地，在沟槽的间距31耐压变为最大(参照图2)。
二极管部的栅电极部件25a和元件部的栅电极25在加工误差以内是相同的尺寸。
沟槽16内的结构，元件部和二极管部基本相同，仅沟槽16的间距不同。因此，和第一实施方式同样地，在制造步骤上，元件部和二极管部没有不同的地方。
半导体装置2和半导体装置1相比，栅电极25延伸到比n-型漂移层12的更深的位置，在沿着沟槽16的n-型漂移层12内，能够形成电荷积蓄层。其结果，能够确保更低的导通电阻。除此之外，半导体装置2同样具有半导体装置1所具有的效果。
接下来，参照图4对第二实施方式的变形例涉及的半导体装置进行说明。第二实施方式的半导体装置2中是具有阶梯结构的一体型的栅电极25，与之相对，如图4所示，变形例的半导体装置3具有在阶梯部分离并成为宽度较宽的上端侧的栅电极36和宽度较窄的底部栅电极35的两段电极结构。栅电极36和底部栅电极35为了成为相同电位，一起连接到设置在表面的栅电极(图示略)。另外，分别与栅电极36和底部栅电极35相对应的二极管部的栅电极36a和底部栅电极35a一起连接到设置在表面的栅电极。
第二实施方式的变形例的半导体装置3也可以考虑第一实施方式的半导体装置1的变形例。即，代替在半导体装置1中将源极埋入电极18连接到源电极22，通过将源极埋入电极18连接到设置在表面的栅电极来形成。
半导体装置3同样具有半导体装置2具有的效果。
在本实施例中，示出了使用硅氧化膜作为沟槽内的绝缘膜的例子，但为了谋求耐压、导通电阻等性能的进一步提高，可以将绝缘膜变更为比硅氧化膜的介电常数高的膜或低的膜。另外，介电常数高的膜或低的膜，并不限于沟槽内的整个膜的替换，也可以部分替换。
另外，在实施例中示出了半导体层含有硅的例子，但也可以是SiC类、GaN类等的化合物半导体。另外，示出了n沟道的MOSFET的例子，但也可以是p沟道。
说明书中的实施方式仅用于对本发明进行说明，其并不对本发明的保护范围起到限定作用。本发明的保护范围仅由权利要求限定，在本发明公开的实施方式的基础上所做的任何省略、替换或修改将落入本发明的保护范围。

Claims (15)

1.一种功率用半导体器件，具有：
包含纵式MOSFET的元件部；以及
与所述元件部邻接的二极管部，
该纵式MOSFET的元件部包括：
第一导电型的第一半导体层；
第一导电型的第二半导体层，与在所述第一半导体层的第一主面上形成的所述第一半导体层相比，杂质浓度低；
第二导电型的第三半导体层，在所述第二半导体层的表面上形成；
第一导电型的第四半导体层，在所述第三半导体层的表面上选择性地形成；
第二导电型的第五半导体层，在所述第三半导体层的表面上选择性地形成；
绝缘膜，覆盖从所述第四半导体层或第五半导体层的表面起贯穿所述第三半导体层直到所述第二半导体层的多个沟槽的内表面，邻接的所述沟槽以第一间隔设置；
第一埋入导电层，隔着所述绝缘膜被埋入到所述沟槽内的底部；
第二埋入导电层，隔着所述绝缘膜被埋入到所述沟槽内的所述第一埋入导电层上部；
层间绝缘膜，在所述第二埋入导电层上形成；
第一主电极，在与所述第一主面相反一侧的所述第一半导体层的第二主面上形成，并且电连接到所述第一半导体层；以及
第二主电极，在所述第四半导体层及第五半导体层以及所述层间绝缘膜上形成并且电连接到所述第四半导体层及第五半导体层，
该二极管部包括；
所述第一半导体层至所述第三半导体层、所述第五半导体层、覆盖所述多个沟槽的内表面的所述绝缘膜、所述第一埋入导电层及第二埋入导电层、所述层间绝缘膜以及所述第一主电极及所述第二主电极，邻接的所述沟槽以比所述第一间隔大的第二间隔设置。
2.如权利要求1记载的功率用半导体器件，其中，
在所述第一埋入导电层及所述第二埋入导电层之间形成有绝缘膜。
3.如权利要求1记载的功率用半导体器件，其中，
所述第一埋入导电层及所述第二埋入导电层是同电位。
4.如权利要求1记载的功率用半导体器件，其中，
所述第一埋入导电层和所述第二主电极连接。
5.如权利要求1记载的功率用半导体器件，其中，
所述第二埋入导电层是栅电极。
6.如权利要求1记载的功率用半导体器件，其中，
与所述第一埋入导电层的侧面相连的所述绝缘膜的第一膜厚比与所述第二埋入导电层的侧面相连的所述绝缘膜的第二膜厚厚。
7.如权利要求1记载的功率用半导体器件，其中，
所述第一埋入导电层的宽度比所述第二埋入导电层的宽度窄。
8.如权利要求1记载的功率用半导体器件，其中，
所述第二埋入导电层和所述第一埋入导电层连接，共同作为栅电极发挥功能。
9.如权利要求1记载的功率用半导体器件，其中，
在所述元件部，所述第四半导体层及所述第五半导体层在所述沟槽的长度方向上交替排列。
10.如权利要求1记载的功率用半导体器件，其中，
所述二极管部的耐压设定得比所述元件部的耐压低。
11.一种功率用半导体器件，具有：
包含纵式MOSFET的元件部；以及二极管部；
该纵式MOSFET包括：
第一导电型的第一半导体层；
第一导电型的第二半导体层，与在所述第一半导体层的第一主面上形成的所述第一半导体层相比，杂质浓度低；
第二导电型的第三半导体层，在所述第二半导体层的表面上形成；
第一导电型的第四半导体层，在所述第三半导体层的表面上选择性地形成；
第二导电型的第五半导体层，在所述第三半导体层的表面上选择性地形成；
绝缘膜，覆盖从所述第四半导体层或所述第五半导体层的表面起贯穿所述第三半导体层直到所述第二半导体层的多个沟槽的内表面，并且在与所述第二半导体层相对置的底部侧的侧面上的膜厚形成得比在上部侧的侧面上的膜厚厚，邻接的所述沟槽以第一间隔设置；
埋入导电层，隔着所述绝缘膜被埋入到所述沟槽内，并作为栅电极；
层间绝缘膜，在所述埋入导电层上形成；
第一主电极，在与所述第一主面相反一侧的所述第一半导体层的第二主面上形成，并且电连接到所述第一半导体层；以及
第二主电极，在所述第四半导体层及所述第五半导体层的表面上以及层间绝缘膜上形成并且电连接到所述第四半导体层及所述第五半导体层，
该二极管部包括：
所述第一半导体层至所述第三半导体层、所述第五半导体层、覆盖所述多个沟槽的内表面的所述绝缘膜、所述埋入导电层、所述层间绝缘膜以及所述第一主电极及所述第二主电极，邻接的所述沟槽以比所述第一间隔大的第二间隔设置。
12.如权利要求11记载的功率用半导体器件，其中，
所述埋入导电层是栅电极。
13.如权利要求11记载的功率用半导体器件，其中，
与所述绝缘膜的所述膜厚较厚的底部侧的侧面相连的埋入导电层的宽度比与所述绝缘膜的所述膜厚较薄的上部侧的侧面相连的埋入导电层的宽度宽。
14.如权利要求11记载的功率用半导体器件，其中，
在所述元件部，所述第四半导体层及所述第五半导体层在所述沟槽的长度方向上交替排列。
15.如权利要求11记载的功率用半导体器件，其中，
所述二极管部的耐压设定得比所述元件部的耐压低。
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