CN102403243A - 减少金属凸块结构下金属层底切现象的方法 - Google Patents

减少金属凸块结构下金属层底切现象的方法 Download PDF

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CN102403243A
CN102403243A CN2011100709137A CN201110070913A CN102403243A CN 102403243 A CN102403243 A CN 102403243A CN 2011100709137 A CN2011100709137 A CN 2011100709137A CN 201110070913 A CN201110070913 A CN 201110070913A CN 102403243 A CN102403243 A CN 102403243A
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wafer
layer
distributor
etching
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CN102403243B (zh
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雷弋昜
郭宏瑞
刘重希
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明公开一种减少金属凸块结构下金属层底切现象的方法，于附有基板的晶片上形成下金属层，该下金属层包括一叠于基板之上的阻挡层与一叠于阻挡层之上的籽晶层。接着将金属凸块直接生长于下金属层的第一部分之上；其中，下金属层的第二部分未被金属凸块覆盖，且该下金属层的第二部分包含籽晶层部分及阻挡层部分；随之进行第一次蚀刻以移除籽晶层部分，再对晶片进行第一次清洗。进行第二次蚀刻以移除阻挡层部分，再对晶片进行第二次清洗。从第一次蚀刻到第一次清洗的第一转换时间与从第二次蚀刻到第二次清洗的第二转换时间，至少一个转换时间约在一秒之内。因底切造成结构剥落的情形得以减少，金属凸块与再配置线工艺的可靠度也大幅提升。

Description

减少金属凸块结构下金属层底切现象的方法
技术领域
本发明涉及一种集成电路，特别是涉及一种形成金属凸块结构的方法。
背景技术
在半导体晶片的制造过程中，集成电路元件如晶体管首先形成于半导体基板的表面，紧接着在集成电路元件上形成内连线结构，最后在半导体晶片表面形成金属凸块，使集成电路元件得以由外部连结之。
传统的金属凸块工艺中，第一步为形成下金属层(under-bump metallurgylayer；UBM layer)。下金属层包括一钛金属层以及位于该钛金属层之上的一铜籽晶层。金属凸块随即以电镀的方式生长于下金属层之上。下金属层不需要的部分以湿蚀刻方式去除。铜籽晶层习惯上以氨蚀(ammonical etching)方式去除，使用碱性蚀刻剂如Cu(NH3)4CL2，NH3，NH4Cl等。蚀刻产生的化学物包含CuO，可以用NH3及水清除。钛金属层暴露在外的部分随即以浓度高达11％的氢氟酸(HF)溶液蚀刻。横向蚀刻钛金属层所产生的底切(undercut)在金属凸块底部延伸，延伸的横向长度大约达10微米。因此可能会造成金属凸块与对应的金属垫片分离，使金属凸块工艺良率降低。
发明内容
依据本发明的一特征，本文公开一种减少金属凸块结构下金属层底切现象的方法，包括：
提供附有基板的晶片；形成一下金属层于该基板上，该下金属层包括一形成于基板之上的阻挡层以及一形成于阻挡层之上的籽晶层。直接形成金属凸块于下金属层的一第一部分之上；此时下金属层的一第二部分并未被金属凸块所覆盖，且该下金属层的第二部分包含籽晶层部分及阻挡层部分。进行第一次蚀刻将籽晶层部分去除，紧接着对晶片进行第一次清洗。接着进行第二次蚀刻将阻挡层部分去除，紧接着对晶片进行第二次清洗。从第一次蚀刻到第一次清洗的第一转换时间与从第二次蚀刻到第二次清洗的第二转换时间，至少一个转换时间约在一秒之内。
其他实施例也予以公开。
因此，因底切造成结构剥落的情形减少，金属凸块与再配置线(redistribution line)工艺的可靠度也大幅提升。
附图说明
为了更完整的说明具体实施例以及其优点，以下的附图解说皆对应文中所附附图，包括：
图1至图6为具体实施例中制造一金属凸块过程的截面图；以及
图7示出蚀刻下金属层所使用的装置。
并且，上述附图中的附图标记说明如下：
2：晶片
10：基板
12：内连线结构
14：集成电路元件
28：金属垫片
30：保护层
40：阻挡层
42：籽晶层
42A：籽晶层的第一部分
42B：籽晶层的第二部分
45：掩模开口处
46：掩模
50：金属凸块
52：附加层
60：平台
62：分配器组
64：化学品分配器
65：化学品分配器
66：去离子水分配器
68：分配器组移动范围
72：分配器组
74：化学品分配器
76：去离子水分配器
78：分配器组移动范围
具体实施方式
下文将讨论本发明所公开的实施例制作及使用过程。此实施例衍生出许多新颖的应用概念，可以广泛实施于各种实际情况。文中所描述的实施例仅作为说明的用途，并非局限本发明的专利保护范围。
本实施例提供一创新的方法，以形成金属凸块并有效减少下金属(UBM)层的底切现象。本实施例的制造过程显示于附图。也针对实施例的变形加以讨论。附图皆有附图标记以定义实施例中的各元件，相同的参照数字代表相同的元件。
如图1所示，首先提供一包含基板10的晶片2。在实施例中基板10为半导体材质，如硅基板，也可使用其他种类的半导体材料，例如硅化锗、碳化硅、以及砷化镓等等。半导体元件14如晶体管等，形成于基板10的表面；内连线结构12形成于基板10之上，包括金属导线以及介层窗(未描绘于附图中)并与半导体元件14电耦合。金属导线与介层窗可以铜金属或铜合金为材料，也可以著名的金属镶嵌法(damascene)制作。内连线结构12包含层间介电层(inter-layer dielectric，ILD)以及金属间介电层(inter-metal dielectric，IMD)。在其他的实施例中，晶片2可为一中介晶片(interposer wafer)或一含有封装基板(package substrate)的晶片，并且实质上无集成电路元件，如晶体管、电容、电阻及电感等生成于其上。以上实施例的基板10的材料可为半导体材料或如氧化硅的介电质材料。
接着，于内连线结构12之上生成金属垫片28。金属垫片28的材料可为铝、铜、银、金、镍、钨等金属、前述金属的合金，及/或前述金属的多阶层(multi-layer)结构。金属垫片28，例如可通过在其下的内连线结构12，与半导体元件14形成电耦合。最后，形成保护层30以覆盖金属垫片28的边缘部分；在一示范实施例中，以聚酰亚胺(polyimide)或其他常用的介电材料如氧化硅、氮化硅或前述材料的多阶层结构作为保护层。
如图2所示，下金属层由薄层状的阻挡层40以及籽晶层42所组成。阻挡层40延伸进入保护层30的开口并与金属垫片28接触。阻挡层40可以钛金属、氮化钛、钽金属或氮化钽为材料。籽晶层42的材料可为铜金属或铜合金，下文所提到的籽晶层将直接视为铜籽晶层。然而，其他金属如银、金、铝以及银、金、铝的组合物也可作为籽晶层的材料。本实施例中以物理气相沉积法或其他可应用的方法形成阻挡层40以及籽晶层42。阻挡层40的厚度约在500埃至2000埃之间。籽晶层42的厚度约在1000埃至10000埃之间。然而也可使用不同的厚度参数。
图3显示出例如以光阻或干膜方式形成具有布局图样的掩模46。籽晶层42的第一部分42A，经由掩模46的开口部分45暴露在外；籽晶层42的第二部分42B则被掩模46所遮蔽。接着，将晶片2放置于电镀液中(未描绘于附图中)进行电镀步骤，形成金属凸块50于籽晶层42的第一部分42A之上以及于开口部分45处。此步骤可采用电镀、无电电镀或是浸镀法等工艺。在一实施例中，金属凸块50为铜凸块。在另一实施例中，金属凸块50可为焊合凸块，如锡银合金、锡银铜合金等等；也可为含铅或无铅材料。
在以铜为金属凸块50材料的一实施例中，可有一附加层52形成于金属凸块50的表面，该附加层52可为焊合盖(solder cap)，或为镍、锡、钯、金层、前述金属的合金或前述金属的多层材质。另外，生成附加层的时机可在移除掩模46之前或之后。掩模46移除的程序显示于图4。待金属凸块50生成后，随即移除掩模46。先前被掩模46所覆盖的下金属层40/42的部分现在裸露出来，其结果也显示于图4。
图5显示以酸蚀刻移除籽晶层42的第二部分42B，该酸蚀刻也为湿蚀刻的一种。在实施例中籽晶层42为铜金种层，因此蚀刻液可采用事先混合稀释过的磷酸(H3PO4)及过氧化氢(H2O2)，下文将称此组合蚀刻液为DPP。实施例中所使用的DPP包含重量百分比0.5至5的磷酸以及重量百分比0.5至5的过氧化氢。也可使用不同浓度的DPP。图7显示用以蚀刻籽晶层42的范例装置。首先将晶片2放置于平台60之上，在蚀刻过程中该平台60会带动置于其上的晶片2一同旋转。化学品分配器64与去离子水分配器66位于晶片2上方，并且固定在一起结合为分配器组62。因此分配器64与66永远是一起移动的。在籽晶层42的蚀刻过程中，分配器组62会来回移动(以箭头68表示)，使DPP得以均匀的喷洒于晶片2之上。蚀刻需时约30秒至3分钟，可由下列反应式表示：
Cu+H2O2->CuHPO4+H2O    [式1]
与
CuO+H3PO4->CuHPO4+H2O  [式2]
DPP喷洒结束后，立刻切换至第一次清洗程序，将去离子水由分配器66喷洒于晶片2之上加以清洗。由DPP停止喷洒到去离子水开始喷洒的转换时间相当短。在实施例中，转换时间可能小于1秒、0.5秒，甚至小于0.3秒。由于分配器64与66被固定于同一分配器组，去离子水会喷洒到DPP喷洒过的相同位置。再加上极短的转换时间可确保DPP反应的残余物快速被清除，让不必要的微粒如焊锡蚀刻反应生成的锡微粒较不易沉积于晶片2上。于实施例中，晶片2在第一次清洗的过程中的转速以高—低—高的程序进行。第一次高转速约大于每分钟1000转，甚至可大于每分钟2000转，使晶片2上的DPP得以被快速甩离。紧接着的低转速阶段为达到良好的清洗效果，其转速小于每分钟500转，甚至可小于每分钟200转。另一高转速阶段则将去离子水甩干，去离子水于此阶段可能持续喷洒或停止喷洒。在实施例中，第一次清洗时间例如约为20秒至一分钟。铜籽晶层的蚀刻完成后，部分的阻挡层40暴露在外。根据图6所示，使用氢氟酸溶液以去除暴露部分的阻挡层40。为了使工艺容易控制且减少底切现象，必须使用低浓度的氢氟酸溶液。于一具体实施例中，氢氟酸溶液的浓度约在0.3百分率至3百分率之间。反应式表示如下：
Ti+HF->[TiF6]-3    [式3]
图7显示了用以喷洒氢氟酸溶液的化学品分配器65也被固定于分配器组62之上。同样的，去离子水由分配器66提供。于另一具体实施例中，化学品分配器74与去离子水分配器76位于晶片2上方，并且固定在一起结合为分配器组72。在阻挡层40的蚀刻过程中，分配器组62或72会来回移动(以箭头78表示)，使氢氟酸溶液得以由分配器65及74均匀的喷洒于晶片2之上。本实施例中蚀刻所需时间例如约20秒到3分钟之间，可能约30秒至1分钟之间。
氢氟酸溶液喷洒结束后，切换至第二次清洗程序。依据所使用的氢氟酸溶液分配器65或74，将去离子水由对应的分配器66或76喷于晶片2之上加以清洗。由氢氟酸溶液停止喷洒，到去离子水开始喷洒的转换时间相当短。在一具体实施例中，转换时间可能小于1秒、0.5秒，甚至小于0.3秒。由于分配器65与66(或74与76)被固定于同一分配器组之上，去离子水会喷洒到氢氟酸溶液喷洒过的相同位置。再加上极短的转换时间可确保氢氟酸溶液快速的被带离晶片2表面。于另一具体实施例中，晶片在第二次清洗的过程中的转速以高—低—高的程序进行。高转速约大于每分钟1000转，甚至可大于每分钟2000转，使晶片2上的氢氟酸溶液得以被快速甩离。低转速阶段其转速小于每分钟500转，甚至可小于每分钟200转。在实施例中，第一次清洗时间例如约为30秒至一或二分钟。
于具体实施例中，由于以酸蚀刻去除籽晶层42与以低浓度氢氟酸蚀刻阻挡层40，并搭配蚀刻后快速切换清洗，使阻挡层40的底切现象获得显著改善。实验结果显示，使用传统的下金属层蚀刻工艺形成的金属凸块结构底切长度约为9微米至10微米；相较之下，采用本实施例的工艺可使底切长度减少为5微米至6微米，改善程度高达百分之三十。因此，因底切造成结构剥落的情形减少，金属凸块与再配置线(redistribution line)工艺的可靠度也大幅提升。
虽然文中将具体实施例及其优点作了详尽的描述，但在不背离本发明的精神与范畴内的各种经改变、调整与置换的实施例仍受随附的权利要求所保护。再者，本文中所呈现的具体应用并无意将保护范围局限于说明书中所提及的特定工艺、仪器、制造方式以及各种物质、步骤、方法与手段的组合。任何本领域普通技术人员可轻易由本文所公开的发明，利用无论是已存在的或尚未开发的工艺、仪器、制造方式以及各种物质、步骤、方法与手段的组合，实现与本发明中的实施例相同的原理或实际结果。因此，本发明的保护范围将以随附的权利要求所界定的范围为准，且每一权利要求皆有相对应的具体实施例，这些权利要求或具体实施例的组合也在本发明所公开的范围内。

Claims (10)

1.一种减少金属凸块结构下金属层底切现象的方法，包括：
提供一晶片，该晶片包括一基板；
形成一下金属层，该下金属层包括覆于该基板上方的一阻挡层，以及覆于该阻挡层上方的一籽晶层；
于该下金属层的第一部分之上形成一金属凸块，该下金属层的第二部分未被该金属凸块所覆盖，且该下金属层的第二部分包括一籽晶层部分及一阻挡层部分；
进行一第一次蚀刻以移除该籽晶层部分；
对该晶片进行一第一次清洗；
进行一第二次蚀刻以移除该阻挡层部分；以及
对该晶片进行一第二次清洗，其中该第一次蚀刻至该第一次清洗的第一转换时间与该第二次蚀刻至该第二次清洗的第二转换时间至少一个转换时间小于1秒。
2.如权利要求1所述的减少金属凸块结构下金属层底切现象的方法，其中该第一次蚀刻以一第一分配器将酸性蚀刻液分配至该晶片之上，该第一次清洗以一第二分配器将去离子水分配至该晶片之上，且该第一分配器与该第二分配器被固定在一起，并设定为可以同时在该晶片上方来回移动。
3.如权利要求1所述的减少金属凸块结构下金属层底切现象的方法，其中该第一次清洗与该第二次清洗至少一次清洗包括：
以大于每分钟1000转的一高转速旋转晶片；
上述高转速旋转完成后，接着以小于每分钟500转的一低转速旋转晶片；以及
上述低转速旋转完成后，接着再以大于每分钟1000转的另一高转速旋转晶片。
4.一种减少金属凸块结构下金属层底切现象的方法，包括：
提供一晶片，该晶片包括一基板；
形成一下金属层，该下金属层包括覆于该基板上方的一阻挡层，以及覆于该阻挡层上方的一籽晶层；
于该下金属层的第一部分之上形成一金属凸块，该下金属层的第二部分未被该金属凸块所覆盖，且该下金属层的第二部分包括一籽晶层部分及一阻挡层部分；
将一第一分配器与一第二分配器置于该晶片上方，上述第一分配器与一第二分配器被固定在一起，并设定为可以同时在该晶片上方来回移动；
将一第三分配器置于该晶片上方，并设定为可以在该晶片上方来回移动；
以该第一分配器将酸性蚀刻液分配至该晶片上以蚀刻该籽晶层部分；
以该第二分配器将去离子水分配至该晶片上；
以该第三分配器将氢氟酸溶液分配至该晶片上以蚀刻该阻挡层部分；以及
将去离子水分配至该晶片上以清除氢氟酸溶液。
5.如权利要求4所述的减少金属凸块结构下金属层底切现象的方法，其中于上述籽晶层部分的蚀刻以及使用该第二分配器分配去离子水的步骤中，上述第一及第二分配器的组合于该晶片上方来回移动，且于上述阻挡层部分的蚀刻以及分配去离子水至该晶片上的步骤中，该第三分配器于该晶片上方来回移动。
6.如权利要求4所述的减少金属凸块结构下金属层底切现象的方法，其中上述使用该第二分配器以及分配去离子水清洗氢氟酸溶液的步骤中皆包括：
以大于每分钟1000转的一高转速旋转该晶片；
上述高转速旋转完成后，接着以小于每分钟500转的一低转速旋转该晶片；以及
上述低转速旋转完成后，接着再以大于每分钟1000转的另一高转速旋转该晶片。
7.如权利要求4所述的减少金属凸块结构下金属层底切现象的方法，其中将去离子水分配至该晶片上以清洗氢氟酸溶液的步骤是通过该第二分配器作分配，此时上述第一、第二以及第三分配器皆被固定在一起并设定为于该晶片上方来回移动。
8.如权利要求4所述的减少金属凸块结构下金属层底切现象的方法，其中将去离子水分配至该晶片上以清洗氢氟酸溶液的步骤是通过异于该第二分配器的一第四分配器作分配，该第三以及该第四分配器被固定在一起并设定为于该晶片上方来回移动。
9.一种减少金属凸块结构下金属层底切现象的方法，包括：
提供一基板；
于该基板上方形成一金属垫片；
于该金属垫片上方形成一保护层；
于该保护层上方形成一钛金属阻挡层，该钛金属阻挡层覆盖该保护层以及延伸进该保护层的开口处使该钛金属阻挡层与上述金属垫片接触；
于该阻挡层上方形成一铜金属籽晶层；
于该铜金属籽晶层上方形成一掩模，该掩模覆盖该铜金属籽晶层的第一部分，且该铜金属籽晶层的第二部分并未被该掩模所覆盖；
于该铜金属籽晶层的第二部分上，以电镀方式形成一金属凸块；
将该掩模移除以使该铜金属籽晶层的第一部分暴露在外；
以一酸蚀刻方式移除该铜籽晶层的第一部分，使一部分的该钛金属阻挡层暴露在外，该酸蚀刻以稀释过的磷酸与过氧化氢作为蚀刻液；以及
进行一额外蚀刻，该额外蚀刻以氢氟酸溶液将一部分的该钛金属阻挡层清除。
10.如权利要求9所述的减少金属凸块结构下金属层底切现象的方法，其中还包括：
完成该酸蚀刻之后，对该基板进行一第一次清洗，且由酸蚀刻转换至该第一次清洗的一第一转换时间约小于0.5秒；以及
完成该额外蚀刻后，对该基板进行一第二次清洗，且由该额外蚀刻转换至该第二次清洗的一第二转换时间约小于0.5秒。
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104241148A (zh) * 2013-06-19 2014-12-24 中芯国际集成电路制造(上海)有限公司 一种在cpi测试中防止衬垫剥离的方法以及产生的器件
CN104821271A (zh) * 2014-02-04 2015-08-05 格罗方德半导体公司 蚀刻底层凸块金属化层及产生的装置
CN104835751A (zh) * 2014-02-10 2015-08-12 格罗方德半导体公司 在集成电路制造期间蚀刻铜的方法
CN104992898A (zh) * 2015-05-28 2015-10-21 北京七星华创电子股份有限公司 一种改善dhf腐蚀均匀性及控制腐蚀速率的方法
CN105826246A (zh) * 2015-01-28 2016-08-03 英飞凌科技股份有限公司 用于铜结构化的中间层及其形成方法
WO2022111146A1 (en) * 2020-11-24 2022-06-02 International Business Machines Corporation Protective surface layer on under bump metallurgy for solder joining

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5096849B2 (ja) * 2007-09-13 2012-12-12 株式会社Ｓｏｋｕｄｏ 基板処理装置および基板処理方法
KR102258660B1 (ko) 2013-09-17 2021-06-02 삼성전자주식회사 구리를 함유하는 금속의 식각에 사용되는 액체 조성물 및 이를 이용한 반도체 장치의 제조 방법
US20150262952A1 (en) * 2014-03-13 2015-09-17 Taiwan Semiconductor Manufacturing Co., Ltd Bump structure and method for forming the same
US9287228B2 (en) * 2014-06-26 2016-03-15 Lam Research Ag Method for etching semiconductor structures and etching composition for use in such a method
US9385197B2 (en) 2014-08-29 2016-07-05 Taiwan Semiconductor Manufacturing Co., Ltd Semiconductor structure with contact over source/drain structure and method for forming the same
US9324820B1 (en) 2014-10-28 2016-04-26 Taiwan Semiconductor Manufacturing Co., Ltd Method for forming semiconductor structure with metallic layer over source/drain structure
US9401336B2 (en) * 2014-11-04 2016-07-26 International Business Machines Corporation Dual layer stack for contact formation
KR102410018B1 (ko) 2015-09-18 2022-06-16 삼성전자주식회사 반도체 패키지
US9624094B1 (en) 2015-11-13 2017-04-18 Cypress Semiconductor Corporation Hydrogen barriers in a copper interconnect process
ITUB20160027A1 (it) * 2016-02-01 2017-08-01 St Microelectronics Srl Procedimento per produrre dispositivi a semiconduttore e corrispondente dispositivo
KR102578794B1 (ko) 2016-06-14 2023-09-18 삼성전자주식회사 반도체 장치 및 그 제조 방법
IT201700087201A1 (it) 2017-07-28 2019-01-28 St Microelectronics Srl Dispositivo a semiconduttore e corrispondente metodo di fabbricazione di dispositivi a semiconduttore
IT201700087318A1 (it) 2017-07-28 2019-01-28 St Microelectronics Srl Dispositivo elettronico integrato con regione di redistribuzione e elevata resistenza agli stress meccanici e suo metodo di preparazione
IT201700087174A1 (it) 2017-07-28 2019-01-28 St Microelectronics Srl Dispositivo a semiconduttore e corrispondente metodo di fabbricazione di dispositivi a semiconduttore
US10790244B2 (en) 2017-09-29 2020-09-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
JP7112873B2 (ja) * 2018-04-05 2022-08-04 新光電気工業株式会社 配線基板、半導体パッケージ及び配線基板の製造方法
US11469194B2 (en) 2018-08-08 2022-10-11 Stmicroelectronics S.R.L. Method of manufacturing a redistribution layer, redistribution layer and integrated circuit including the redistribution layer
DE102019112030B4 (de) * 2019-05-08 2023-11-02 LSR Engineering & Consulting Limited Verfahren zum Strukturieren eines Substrats
US11302537B2 (en) * 2020-04-01 2022-04-12 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure with conductive adhesive layer and method for forming the same
US20230123307A1 (en) * 2021-10-18 2023-04-20 Texas Instruments Incorporated Electronic device having chemically coated bump bonds

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5508229A (en) * 1994-05-24 1996-04-16 National Semiconductor Corporation Method for forming solder bumps in semiconductor devices
US7064436B2 (en) * 2003-12-10 2006-06-20 Fujitsu Limited Semiconductor device and method of fabricating the same
CN101330065A (zh) * 2007-06-22 2008-12-24 中芯国际集成电路制造(上海)有限公司 凸点制作方法、凸点下金属层及制作方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5656858A (en) * 1994-10-19 1997-08-12 Nippondenso Co., Ltd. Semiconductor device with bump structure
KR100219806B1 (ko) * 1997-05-27 1999-09-01 윤종용 반도체장치의 플립 칩 실장형 솔더 범프의 제조방법, 이에 따라 제조되는 솔더범프 및 그 분석방법
TW521359B (en) 2002-02-20 2003-02-21 Advanced Semiconductor Eng Bump fabrication process
TWI239578B (en) 2002-02-21 2005-09-11 Advanced Semiconductor Eng Manufacturing process of bump

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5508229A (en) * 1994-05-24 1996-04-16 National Semiconductor Corporation Method for forming solder bumps in semiconductor devices
US7064436B2 (en) * 2003-12-10 2006-06-20 Fujitsu Limited Semiconductor device and method of fabricating the same
CN101330065A (zh) * 2007-06-22 2008-12-24 中芯国际集成电路制造(上海)有限公司 凸点制作方法、凸点下金属层及制作方法

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104241148A (zh) * 2013-06-19 2014-12-24 中芯国际集成电路制造(上海)有限公司 一种在cpi测试中防止衬垫剥离的方法以及产生的器件
CN104241148B (zh) * 2013-06-19 2017-08-25 中芯国际集成电路制造(上海)有限公司 一种在cpi测试中防止衬垫剥离的方法以及产生的器件
CN104821271A (zh) * 2014-02-04 2015-08-05 格罗方德半导体公司 蚀刻底层凸块金属化层及产生的装置
CN104821271B (zh) * 2014-02-04 2018-04-24 格罗方德半导体公司 蚀刻底层凸块金属化层及产生的装置
CN104835751B (zh) * 2014-02-10 2018-06-01 格罗方德半导体公司 在集成电路制造期间蚀刻铜的方法
CN104835751A (zh) * 2014-02-10 2015-08-12 格罗方德半导体公司 在集成电路制造期间蚀刻铜的方法
CN105826246A (zh) * 2015-01-28 2016-08-03 英飞凌科技股份有限公司 用于铜结构化的中间层及其形成方法
CN105826246B (zh) * 2015-01-28 2019-06-14 英飞凌科技股份有限公司 用于铜结构化的中间层及其形成方法
CN104992898A (zh) * 2015-05-28 2015-10-21 北京七星华创电子股份有限公司 一种改善dhf腐蚀均匀性及控制腐蚀速率的方法
CN104992898B (zh) * 2015-05-28 2017-12-08 北京七星华创电子股份有限公司 一种改善dhf腐蚀均匀性及控制腐蚀速率的方法
WO2022111146A1 (en) * 2020-11-24 2022-06-02 International Business Machines Corporation Protective surface layer on under bump metallurgy for solder joining
US11682640B2 (en) 2020-11-24 2023-06-20 International Business Machines Corporation Protective surface layer on under bump metallurgy for solder joining
GB2616764A (en) * 2020-11-24 2023-09-20 Ibm Protective surface layer on under bump metallurgy for solder joining

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US8389397B2 (en) 2013-03-05
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US20120064712A1 (en) 2012-03-15

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