CN102365748A - 组态和制造其中非单结晶半导体间隔部分控制基极链长的具有双极面结型晶体管的半导体结构 - Google Patents

组态和制造其中非单结晶半导体间隔部分控制基极链长的具有双极面结型晶体管的半导体结构 Download PDF

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CN102365748A
CN102365748A CN2010800138581A CN201080013858A CN102365748A CN 102365748 A CN102365748 A CN 102365748A CN 2010800138581 A CN2010800138581 A CN 2010800138581A CN 201080013858 A CN201080013858 A CN 201080013858A CN 102365748 A CN102365748 A CN 102365748A
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lateral separation
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杰恩-均·杨
康斯坦丁·布卢恰
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National Semiconductor Corp
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National Semiconductor Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0112—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs
    • H10D84/0119—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs the components including complementary BJTs
    • H10D84/0121—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs the components including complementary BJTs the complementary BJTs being vertical BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0107—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs
    • H10D84/0109—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs the at least one component covered by H10D12/00 or H10D30/00 being a MOS device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/40—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
    • H10D84/401—Combinations of FETs or IGBTs with BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/67—Complementary BJTs
    • H10D84/673—Vertical complementary BJTs

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
CN2010800138581A 2009-03-27 2010-03-25 组态和制造其中非单结晶半导体间隔部分控制基极链长的具有双极面结型晶体管的半导体结构 Pending CN102365748A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/382,966 2009-03-27
US12/382,966 US8030151B2 (en) 2009-03-27 2009-03-27 Configuration and fabrication of semiconductor structure having bipolar junction transistor in which non-monocrystalline semiconductor spacing portion controls base-link length
PCT/US2010/000884 WO2010110891A1 (en) 2009-03-27 2010-03-25 Configuration and fabrication of semiconductor structure having bipolar junction transistor in which non-monocrystalline semiconductor spacing portion controls base-link length

Publications (1)

Publication Number Publication Date
CN102365748A true CN102365748A (zh) 2012-02-29

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US (2) US8030151B2 (https=)
EP (1) EP2412026A4 (https=)
JP (1) JP2012522362A (https=)
KR (1) KR20120003911A (https=)
CN (1) CN102365748A (https=)
TW (1) TW201108413A (https=)
WO (1) WO2010110891A1 (https=)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104517969A (zh) * 2013-09-27 2015-04-15 力旺电子股份有限公司 非挥发性存储器单元及非挥发性存储器单元的制作方法
CN106170861A (zh) * 2014-01-16 2016-11-30 理想能量有限公司 对表面电荷敏感性降低的结构和方法
CN105633078B (zh) * 2015-12-23 2018-06-22 成都芯源系统有限公司 双极结型半导体器件及其制造方法
CN108417634A (zh) * 2017-02-02 2018-08-17 恩智浦有限公司 制造半导体开关装置的方法
CN108807515A (zh) * 2017-05-05 2018-11-13 联华电子股份有限公司 双极性晶体管
CN109427767A (zh) * 2017-08-24 2019-03-05 新加坡商格罗方德半导体私人有限公司 用于esd的使用隔离的高电压pnp及其制造方法
CN115000018A (zh) * 2021-05-07 2022-09-02 台湾积体电路制造股份有限公司 形成半导体结构的方法

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8299532B2 (en) * 2009-08-20 2012-10-30 United Microelectronics Corp. ESD protection device structure
JP5915194B2 (ja) * 2012-01-17 2016-05-11 富士通セミコンダクター株式会社 半導体装置及びその製造方法
US8716827B2 (en) 2012-09-11 2014-05-06 Texas Instruments Incorporated Diffusion resistor with reduced voltage coefficient of resistance and increased breakdown voltage using CMOS wells
US9190501B2 (en) * 2013-02-26 2015-11-17 Broadcom Corporation Semiconductor devices including a lateral bipolar structure with high current gains
US8981490B2 (en) * 2013-03-14 2015-03-17 Texas Instruments Incorporated Transistor with deep Nwell implanted through the gate
US9601607B2 (en) * 2013-11-27 2017-03-21 Qualcomm Incorporated Dual mode transistor
US10283584B2 (en) * 2016-09-27 2019-05-07 Globalfoundries Inc. Capacitive structure in a semiconductor device having reduced capacitance variability
TWI655772B (zh) * 2017-05-05 2019-04-01 旺宏電子股份有限公司 半導體元件
US10256307B2 (en) 2017-05-08 2019-04-09 Macronix International Co., Ltd. Semiconductor device
JP7075172B2 (ja) * 2017-06-01 2022-05-25 エイブリック株式会社 基準電圧回路及び半導体装置
US11288430B2 (en) * 2017-11-27 2022-03-29 Globalfoundries U.S. Inc. Producing models for dynamically depleted transistors using systems having simulation circuits
CN108389890B (zh) * 2018-01-12 2022-01-07 矽力杰半导体技术(杭州)有限公司 场效应晶体管及其制造方法
JP2021052150A (ja) * 2019-09-26 2021-04-01 株式会社村田製作所 パワーアンプ単位セル及びパワーアンプモジュール
US11217665B2 (en) * 2020-02-04 2022-01-04 Texas Instruments Incorporated Bipolar junction transistor with constricted collector region having high gain and early voltage product
US12176346B2 (en) * 2021-10-25 2024-12-24 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices, semiconductor structures and methods for fabricating a semiconductor structure
US20250098190A1 (en) * 2023-09-14 2025-03-20 Globalfoundries U.S. Inc. Bipolar transistors

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7145191B1 (en) * 2000-03-31 2006-12-05 National Semiconductor Corporation P-channel field-effect transistor with reduced junction capacitance
CN1938820A (zh) * 2004-03-26 2007-03-28 关西电力株式会社 双极型半导体装置及其制造方法
US7211863B2 (en) * 2002-09-29 2007-05-01 Advanced Analogic Technologies, Inc. Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology
US20070187795A1 (en) * 2004-06-30 2007-08-16 Gernot Langguth Integrated circuit arrangement comprising a pin diode, and production method
US20080311717A1 (en) * 2005-08-29 2008-12-18 Constantin Bulucea Fabrication of semiconductor architecture having field-effect transistors especially suitable for analog applications

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6226850A (ja) * 1985-07-27 1987-02-04 Nippon Gakki Seizo Kk 集積回路装置の製法
US5023193A (en) * 1986-07-16 1991-06-11 National Semiconductor Corp. Method for simultaneously fabricating bipolar and complementary field effect transistors using a minimal number of masks
US5011784A (en) * 1988-01-21 1991-04-30 Exar Corporation Method of making a complementary BiCMOS process with isolated vertical PNP transistors
JP2625602B2 (ja) * 1991-01-18 1997-07-02 インターナショナル・ビジネス・マシーンズ・コーポレイション 集積回路デバイスの製造プロセス
US5650340A (en) 1994-08-18 1997-07-22 Sun Microsystems, Inc. Method of making asymmetric low power MOS devices
US5622880A (en) 1994-08-18 1997-04-22 Sun Microsystems, Inc. Method of making a low power, high performance junction transistor
US6548642B1 (en) 1997-07-21 2003-04-15 Ohio University Synthetic genes for plant gums
US6570242B1 (en) * 1997-11-20 2003-05-27 Texas Instruments Incorporated Bipolar transistor with high breakdown voltage collector
JPH11238817A (ja) * 1998-02-24 1999-08-31 Rohm Co Ltd 半導体装置およびその製造方法
US6548842B1 (en) 2000-03-31 2003-04-15 National Semiconductor Corporation Field-effect transistor for alleviating short-channel effects
JP4003438B2 (ja) * 2001-11-07 2007-11-07 株式会社デンソー 半導体装置の製造方法および半導体装置
US6630377B1 (en) * 2002-09-18 2003-10-07 Chartered Semiconductor Manufacturing Ltd. Method for making high-gain vertical bipolar junction transistor structures compatible with CMOS process
JP2005252158A (ja) * 2004-03-08 2005-09-15 Yamaha Corp バイポーラトランジスタとその製法
US7419863B1 (en) 2005-08-29 2008-09-02 National Semiconductor Corporation Fabrication of semiconductor structure in which complementary field-effect transistors each have hypoabrupt body dopant distribution below at least one source/drain zone
US7642574B2 (en) 2005-08-29 2010-01-05 National Semiconductor Corporation Semiconductor architecture having field-effect transistors especially suitable for analog applications

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7145191B1 (en) * 2000-03-31 2006-12-05 National Semiconductor Corporation P-channel field-effect transistor with reduced junction capacitance
US7211863B2 (en) * 2002-09-29 2007-05-01 Advanced Analogic Technologies, Inc. Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology
CN1938820A (zh) * 2004-03-26 2007-03-28 关西电力株式会社 双极型半导体装置及其制造方法
US20070187795A1 (en) * 2004-06-30 2007-08-16 Gernot Langguth Integrated circuit arrangement comprising a pin diode, and production method
US20080311717A1 (en) * 2005-08-29 2008-12-18 Constantin Bulucea Fabrication of semiconductor architecture having field-effect transistors especially suitable for analog applications

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104517969A (zh) * 2013-09-27 2015-04-15 力旺电子股份有限公司 非挥发性存储器单元及非挥发性存储器单元的制作方法
CN106170861A (zh) * 2014-01-16 2016-11-30 理想能量有限公司 对表面电荷敏感性降低的结构和方法
CN106170861B (zh) * 2014-01-16 2018-12-28 理想能量有限公司 对表面电荷敏感性降低的结构和方法
CN105633078B (zh) * 2015-12-23 2018-06-22 成都芯源系统有限公司 双极结型半导体器件及其制造方法
CN108417634A (zh) * 2017-02-02 2018-08-17 恩智浦有限公司 制造半导体开关装置的方法
CN108417634B (zh) * 2017-02-02 2023-09-15 恩智浦有限公司 制造半导体开关装置的方法
CN108807515A (zh) * 2017-05-05 2018-11-13 联华电子股份有限公司 双极性晶体管
CN108807515B (zh) * 2017-05-05 2022-07-05 联华电子股份有限公司 双极性晶体管
CN109427767A (zh) * 2017-08-24 2019-03-05 新加坡商格罗方德半导体私人有限公司 用于esd的使用隔离的高电压pnp及其制造方法
CN109427767B (zh) * 2017-08-24 2023-07-18 新加坡商格罗方德半导体私人有限公司 用于esd的使用隔离的高电压pnp及其制造方法
CN115000018A (zh) * 2021-05-07 2022-09-02 台湾积体电路制造股份有限公司 形成半导体结构的方法
CN115000018B (zh) * 2021-05-07 2026-03-17 台湾积体电路制造股份有限公司 形成半导体结构的方法

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WO2010110891A1 (en) 2010-09-30
US8030151B2 (en) 2011-10-04
JP2012522362A (ja) 2012-09-20
EP2412026A1 (en) 2012-02-01
WO2010110891A8 (en) 2011-08-11
KR20120003911A (ko) 2012-01-11
US20100244143A1 (en) 2010-09-30
EP2412026A4 (en) 2014-03-19
TW201108413A (en) 2011-03-01
US8304308B2 (en) 2012-11-06
US20120181619A1 (en) 2012-07-19

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Application publication date: 20120229