KR20120003911A - 비-단결정질의 반도체 스페이싱 부분이 베이스-연결 길이를 조절하는 바이폴라 접합 트랜지스터를 갖는 반도체 구조의 구성 및 제조 - Google Patents
비-단결정질의 반도체 스페이싱 부분이 베이스-연결 길이를 조절하는 바이폴라 접합 트랜지스터를 갖는 반도체 구조의 구성 및 제조 Download PDFInfo
- Publication number
- KR20120003911A KR20120003911A KR1020117025421A KR20117025421A KR20120003911A KR 20120003911 A KR20120003911 A KR 20120003911A KR 1020117025421 A KR1020117025421 A KR 1020117025421A KR 20117025421 A KR20117025421 A KR 20117025421A KR 20120003911 A KR20120003911 A KR 20120003911A
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- South Korea
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- semiconductor
- dopant
- base
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0112—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs
- H10D84/0119—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs the components including complementary BJTs
- H10D84/0121—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs the components including complementary BJTs the complementary BJTs being vertical BJTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0107—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs
- H10D84/0109—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs the at least one component covered by H10D12/00 or H10D30/00 being a MOS device
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/40—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
- H10D84/401—Combinations of FETs or IGBTs with BJTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
- H10D84/67—Complementary BJTs
- H10D84/673—Vertical complementary BJTs
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Bipolar Transistors (AREA)
- Bipolar Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/382,966 | 2009-03-27 | ||
| US12/382,966 US8030151B2 (en) | 2009-03-27 | 2009-03-27 | Configuration and fabrication of semiconductor structure having bipolar junction transistor in which non-monocrystalline semiconductor spacing portion controls base-link length |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20120003911A true KR20120003911A (ko) | 2012-01-11 |
Family
ID=42781338
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020117025421A Withdrawn KR20120003911A (ko) | 2009-03-27 | 2010-03-25 | 비-단결정질의 반도체 스페이싱 부분이 베이스-연결 길이를 조절하는 바이폴라 접합 트랜지스터를 갖는 반도체 구조의 구성 및 제조 |
Country Status (7)
| Country | Link |
|---|---|
| US (2) | US8030151B2 (https=) |
| EP (1) | EP2412026A4 (https=) |
| JP (1) | JP2012522362A (https=) |
| KR (1) | KR20120003911A (https=) |
| CN (1) | CN102365748A (https=) |
| TW (1) | TW201108413A (https=) |
| WO (1) | WO2010110891A1 (https=) |
Families Citing this family (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8299532B2 (en) * | 2009-08-20 | 2012-10-30 | United Microelectronics Corp. | ESD protection device structure |
| JP5915194B2 (ja) * | 2012-01-17 | 2016-05-11 | 富士通セミコンダクター株式会社 | 半導体装置及びその製造方法 |
| US8716827B2 (en) | 2012-09-11 | 2014-05-06 | Texas Instruments Incorporated | Diffusion resistor with reduced voltage coefficient of resistance and increased breakdown voltage using CMOS wells |
| US9190501B2 (en) * | 2013-02-26 | 2015-11-17 | Broadcom Corporation | Semiconductor devices including a lateral bipolar structure with high current gains |
| US8981490B2 (en) * | 2013-03-14 | 2015-03-17 | Texas Instruments Incorporated | Transistor with deep Nwell implanted through the gate |
| US9236453B2 (en) * | 2013-09-27 | 2016-01-12 | Ememory Technology Inc. | Nonvolatile memory structure and fabrication method thereof |
| US9601607B2 (en) * | 2013-11-27 | 2017-03-21 | Qualcomm Incorporated | Dual mode transistor |
| CN106170861B (zh) * | 2014-01-16 | 2018-12-28 | 理想能量有限公司 | 对表面电荷敏感性降低的结构和方法 |
| CN105633078B (zh) * | 2015-12-23 | 2018-06-22 | 成都芯源系统有限公司 | 双极结型半导体器件及其制造方法 |
| US10283584B2 (en) * | 2016-09-27 | 2019-05-07 | Globalfoundries Inc. | Capacitive structure in a semiconductor device having reduced capacitance variability |
| EP3358626B1 (en) * | 2017-02-02 | 2022-07-20 | Nxp B.V. | Method of making a semiconductor switch device |
| TWI655772B (zh) * | 2017-05-05 | 2019-04-01 | 旺宏電子股份有限公司 | 半導體元件 |
| CN108807515B (zh) * | 2017-05-05 | 2022-07-05 | 联华电子股份有限公司 | 双极性晶体管 |
| US10256307B2 (en) | 2017-05-08 | 2019-04-09 | Macronix International Co., Ltd. | Semiconductor device |
| JP7075172B2 (ja) * | 2017-06-01 | 2022-05-25 | エイブリック株式会社 | 基準電圧回路及び半導体装置 |
| US10037988B1 (en) * | 2017-08-24 | 2018-07-31 | Globalfoundries Singapore Pte. Ltd. | High voltage PNP using isolation for ESD and method for producing the same |
| US11288430B2 (en) * | 2017-11-27 | 2022-03-29 | Globalfoundries U.S. Inc. | Producing models for dynamically depleted transistors using systems having simulation circuits |
| CN108389890B (zh) * | 2018-01-12 | 2022-01-07 | 矽力杰半导体技术(杭州)有限公司 | 场效应晶体管及其制造方法 |
| JP2021052150A (ja) * | 2019-09-26 | 2021-04-01 | 株式会社村田製作所 | パワーアンプ単位セル及びパワーアンプモジュール |
| US11217665B2 (en) * | 2020-02-04 | 2022-01-04 | Texas Instruments Incorporated | Bipolar junction transistor with constricted collector region having high gain and early voltage product |
| US11551977B2 (en) * | 2021-05-07 | 2023-01-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Methods for improvement of photoresist patterning profile |
| US12176346B2 (en) * | 2021-10-25 | 2024-12-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices, semiconductor structures and methods for fabricating a semiconductor structure |
| US20250098190A1 (en) * | 2023-09-14 | 2025-03-20 | Globalfoundries U.S. Inc. | Bipolar transistors |
Family Cites Families (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6226850A (ja) * | 1985-07-27 | 1987-02-04 | Nippon Gakki Seizo Kk | 集積回路装置の製法 |
| US5023193A (en) * | 1986-07-16 | 1991-06-11 | National Semiconductor Corp. | Method for simultaneously fabricating bipolar and complementary field effect transistors using a minimal number of masks |
| US5011784A (en) * | 1988-01-21 | 1991-04-30 | Exar Corporation | Method of making a complementary BiCMOS process with isolated vertical PNP transistors |
| JP2625602B2 (ja) * | 1991-01-18 | 1997-07-02 | インターナショナル・ビジネス・マシーンズ・コーポレイション | 集積回路デバイスの製造プロセス |
| US5650340A (en) | 1994-08-18 | 1997-07-22 | Sun Microsystems, Inc. | Method of making asymmetric low power MOS devices |
| US5622880A (en) | 1994-08-18 | 1997-04-22 | Sun Microsystems, Inc. | Method of making a low power, high performance junction transistor |
| US6548642B1 (en) | 1997-07-21 | 2003-04-15 | Ohio University | Synthetic genes for plant gums |
| US6570242B1 (en) * | 1997-11-20 | 2003-05-27 | Texas Instruments Incorporated | Bipolar transistor with high breakdown voltage collector |
| JPH11238817A (ja) * | 1998-02-24 | 1999-08-31 | Rohm Co Ltd | 半導体装置およびその製造方法 |
| US6548842B1 (en) | 2000-03-31 | 2003-04-15 | National Semiconductor Corporation | Field-effect transistor for alleviating short-channel effects |
| US7145191B1 (en) * | 2000-03-31 | 2006-12-05 | National Semiconductor Corporation | P-channel field-effect transistor with reduced junction capacitance |
| JP4003438B2 (ja) * | 2001-11-07 | 2007-11-07 | 株式会社デンソー | 半導体装置の製造方法および半導体装置 |
| US6630377B1 (en) * | 2002-09-18 | 2003-10-07 | Chartered Semiconductor Manufacturing Ltd. | Method for making high-gain vertical bipolar junction transistor structures compatible with CMOS process |
| US6855985B2 (en) * | 2002-09-29 | 2005-02-15 | Advanced Analogic Technologies, Inc. | Modular bipolar-CMOS-DMOS analog integrated circuit & power transistor technology |
| JP2005252158A (ja) * | 2004-03-08 | 2005-09-15 | Yamaha Corp | バイポーラトランジスタとその製法 |
| WO2005093796A1 (ja) * | 2004-03-26 | 2005-10-06 | The Kansai Electric Power Co., Inc. | バイポーラ型半導体装置およびその製造方法 |
| DE102004031606B4 (de) * | 2004-06-30 | 2009-03-12 | Infineon Technologies Ag | Integrierte Schaltungsanordnung mit pin-Diode und Herstellungsverfahren |
| US7419863B1 (en) | 2005-08-29 | 2008-09-02 | National Semiconductor Corporation | Fabrication of semiconductor structure in which complementary field-effect transistors each have hypoabrupt body dopant distribution below at least one source/drain zone |
| US7838369B2 (en) | 2005-08-29 | 2010-11-23 | National Semiconductor Corporation | Fabrication of semiconductor architecture having field-effect transistors especially suitable for analog applications |
| US7642574B2 (en) | 2005-08-29 | 2010-01-05 | National Semiconductor Corporation | Semiconductor architecture having field-effect transistors especially suitable for analog applications |
-
2009
- 2009-03-27 US US12/382,966 patent/US8030151B2/en active Active
-
2010
- 2010-03-24 TW TW099108623A patent/TW201108413A/zh unknown
- 2010-03-25 CN CN2010800138581A patent/CN102365748A/zh active Pending
- 2010-03-25 KR KR1020117025421A patent/KR20120003911A/ko not_active Withdrawn
- 2010-03-25 EP EP10756484.1A patent/EP2412026A4/en not_active Withdrawn
- 2010-03-25 WO PCT/US2010/000884 patent/WO2010110891A1/en not_active Ceased
- 2010-03-25 JP JP2012502010A patent/JP2012522362A/ja active Pending
-
2011
- 2011-08-04 US US13/198,601 patent/US8304308B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| WO2010110891A1 (en) | 2010-09-30 |
| US8030151B2 (en) | 2011-10-04 |
| JP2012522362A (ja) | 2012-09-20 |
| EP2412026A1 (en) | 2012-02-01 |
| CN102365748A (zh) | 2012-02-29 |
| WO2010110891A8 (en) | 2011-08-11 |
| US20100244143A1 (en) | 2010-09-30 |
| EP2412026A4 (en) | 2014-03-19 |
| TW201108413A (en) | 2011-03-01 |
| US8304308B2 (en) | 2012-11-06 |
| US20120181619A1 (en) | 2012-07-19 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0105 | International application |
Patent event date: 20111026 Patent event code: PA01051R01D Comment text: International Patent Application |
|
| PG1501 | Laying open of application | ||
| PC1203 | Withdrawal of no request for examination | ||
| WITN | Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid |