CN102339763A - 装配集成电路器件的方法 - Google Patents

装配集成电路器件的方法 Download PDF

Info

Publication number
CN102339763A
CN102339763A CN2010102368005A CN201010236800A CN102339763A CN 102339763 A CN102339763 A CN 102339763A CN 2010102368005 A CN2010102368005 A CN 2010102368005A CN 201010236800 A CN201010236800 A CN 201010236800A CN 102339763 A CN102339763 A CN 102339763A
Authority
CN
China
Prior art keywords
seal
semiconductor element
lead frame
underboarding
assembling
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2010102368005A
Other languages
English (en)
Other versions
CN102339763B (zh
Inventor
陈伟民
白志刚
王志杰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Priority to CN201010236800.5A priority Critical patent/CN102339763B/zh
Priority to US13/092,162 priority patent/US8536684B2/en
Publication of CN102339763A publication Critical patent/CN102339763A/zh
Application granted granted Critical
Publication of CN102339763B publication Critical patent/CN102339763B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0103—Zinc [Zn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.

Abstract

本发明涉及一种装配集成电路(IC)器件的方法，包括以下步骤：提供引线框或衬底；将半导体管芯连附至引线框或衬底；以及电耦合管芯至引线框或衬底。该方法还包括：使用第一密封件密封管芯；以及使用第二密封件密封第一密封件，其中第二密封件包括提供电磁屏蔽的材料。

Description

装配集成电路器件的方法
技术领域
本发明涉及集成电路(IC)器件，以及具体地涉及保护IC器件不受包括电磁干扰(EMI)或射频干扰(RFI)的外部环境影响的方法。
背景技术
诸如磁性随机存取存储器(MRAM)的集成电路器件在存在除了施加的写场之外的杂散或外部施加的电磁场时可能会出现错误。这样的杂散场可以来自于包括诸如计算机、显示器等的电子装置的各种源，并且可以具有足够的幅值从而在即使没有写场的情况下转换一个或多个存储单元的逻辑状态。
通常通过使用环氧树脂材料密封或在该器件周围转印模塑热塑性树脂来保护集成电路器件不受外部环境的影响。然而，环氧树脂或塑料密封不能提供对于诸如EMI或RFI的辐射的有效屏蔽。
一些传统的屏蔽系统使用导电金属壳来围绕要被屏蔽的电路。其他系统使用磁性箔使器件与磁场屏蔽。然而，所有已知的解决方案都具有某些缺点。例如，使用导电金属壳增加了包装的整体尺寸，并且需要额外的焊接工艺来将该壳附着至该器件，而额外的焊接工艺产生的热可能会损害该器件。另一方面，使用磁性箔导致严重的界面剥离问题，特别是当在覆层结构中使用双箔时更是如此。
因此，需要一种成本有效的部件级屏蔽处理，其能够被用在具有任何半导体管芯尺寸的各种电路装置中。
附图说明
参考附图描述本发明的优选实施例，其中：
图1A至1F示出了根据本发明的一个实施例的在切单之前的在装配的不同阶段的IC器件的放大横截面视图；
图2D至2F示出了根据本发明的另一实施例的IC器件的放大横截面视图；
图3是示出了根据本发明的实施例的装配IC器件的方法的流程图；
图4A至4H示出了根据本发明的又一实施例的在切单之前的在装配的不同阶段的IC器件的放大横截面视图；
图5F至5H示出了根据本发明的另一实施例的IC器件的放大横截面视图；
图6是示出了根据本发明的实施例的装配IC器件的另一方法的流程图；
图7A至7F示出了根据本发明的另一实施例的切单之前的在装配的不同阶段的IC器件的放大横截面视图；
图8D至8F示出了根据本发明的另一实施例的IC器件的放大横截面视图；
图9是示出了根据本发明的实施例的装配IC器件的方法的流程图；
图10A至10F示出了根据本发明的另一实施例的切单之前的装配的不同阶段的IC器件的放大横截面视图；
图11D至11F示出了根据本发明的另一实施例的IC器件的放大横截面视图；以及
图12是示出了根据本发明的又一实施例的装配IC器件的方法的流程图。
具体实施方式
根据本发明的一个方面，提供了一种形成集成电路(IC)器件的方法，包括以下步骤：(i)提供引线框或衬底板；(ii)将半导体管芯连附至引线框或衬底板；(iii)电耦合半导体管芯至引线框或衬底板；(iv)使用第一密封件密封半导体管芯；以及(v)使用第二密封件密封第一密封件，其中所述第二密封件包括提供至少电磁屏蔽功能的材料。
优选地，第一密封件不提供磁屏蔽功能。第一密封件可以包括模塑化合物，例如Hitachi 9200 HF10M化合物或Sumitomo G700化合物。可以通过MAP模塑处理或可选地通过包括用于每个模盖的单个腔的模具应用第一密封件。
第二密封件可以包括用于为IC器件提供电屏蔽的导体材料和/或金属微粒。第二密封件可以包括用于为IC器件提供磁屏蔽的非导磁微粒。可以通过MAP模塑处理或可选地通过包括用于每个模盖的单个腔的模具应用第二密封件。此外，第二密封件应该至少覆盖第一密封件的顶表面和两个侧表面。
衬底可以包括印刷电路板(PCB)。电耦合至引线框或衬底的步骤可以通过线接合来实现。可选地，电耦合至引线框或衬底的步骤可以通过倒装芯片处理来实现。
根据本发明的另一方面，提供了一种包括引线框或衬底板的集成电路(IC)器件；半导体管芯连附并电耦合至引线框或衬底板；第一密封件应用在半导体管芯上；以及第二密封件应用在第一密封件上。第二密封件覆盖第一密封件的顶表面和两个侧面。此外，第二密封件包括提供电磁屏蔽的材料。
现在参考图1A，衬底或引线框板10代表切单之前的条带中的一个板或这样的板的阵列(未示出)。板10可以包括双马来酰亚胺三嗪树脂(BT)衬底。BT衬底适于球栅阵列(BGA)产品。可选地，板10可以包括金属衬底，例如合金42或镀铜、镀铝、镀塑等。镀覆的材料可以包括铜、银或多层镀层，例如镍-钯和金。板10可以被配置为符合标准IC封装装配工具。
如图1A中所示，例如高导电性环氧材料的粘性浆料层11被应用至板10上的某一位置，其被称为标志或管芯连附盘。在从半导体晶片上被切下后，如图1B中所示，使用本领域已知的拾取和放置工具将半导体管芯12放置在粘性浆料11的相应层上。粘性浆料11随后如本领域中已知的那样被固化。
粘性浆料11固化之后，如图1C中所示，通过导线13将半导体管芯12电耦合至板10上的引线接头或衬底垫(未示出)。导线13由诸如铝或金的导电材料形成。在一个实施例中，导线13使用可商业获得的引线接合设备自动点焊至引线接头。
在导线13接合至管芯12之后，执行第一或主模塑密封处理，以在管芯12和导线13上形成模盖或密封件14，如图1D中所示。主密封处理可以包括通过模塑设备(例如转印模塑装置)执行的MAP(模塑阵列封装)模塑处理。
密封件14优选地包括不提供电磁屏蔽的合成材料。密封件14可以包括如下的材料，包括环氧树脂、苯酚硬化剂、二氧化硅、催化剂、色素和脱模剂。在期望更高的导热性时，代替硅石，可以使用氧化硅作为填充剂。例如，密封件14可以包括Hitachi 9200 HF10M化合物或Sumitomo G700化合物，两者都是可商业获得的。
在主模塑密封处理完成之后，第二模塑密封处理被执行以在第一密封件14上形成模盖或第二密封件15，如图1E中所示。第二密封件15包括提供至少电磁屏蔽功能的合成材料。
第二密封件15可以包括诸如导电/金属微粒的添加剂，用于为该器件提供电磁屏蔽。后者可以提供电屏蔽以阻挡电磁场。可选地或附加地，第二密封件15可以包括非导磁微粒，例如钙钛矿或铁酸锌(zinc ferrite)。后者可以通过将磁场吸收至微粒从而为被屏蔽体积周围的磁场线提供路径，由此实现磁屏蔽。
可以通过如上所述的传统的模塑设备(例如MAP)执行第二密封处理。在BGA(球栅阵列)类型器件的情况下，在第二密封处理之后可以进行焊球连附处理，如图1F中所示。在焊球连附处理中，焊球16连附到衬底的底表面，然后，焊球16使得该器件能够被连接到印刷电路板(PCB)。连接处理可以在回流炉中执行或者通过使得焊球16熔化的红外线加热器执行。
第二密封处理之后，使用锯切单或本领域已知的类似技术使各个器件被切单或与模塑阵列组件分开。对于BGA类型的器件，焊球16可以在切单处理之前或之后被连附。
在一些实施例中，可以如图2D至2F中所示地修改图1D至1F中示出的第一和第二模塑密封处理。图2D中示出的处理类似于图1D中示出的处理，不同之处在于，第一密封件17是通过传统模具产生的，其使用了用于每个器件的单个腔。
图2E中示出的处理还类似于图1E中示出的处理，不同之处在于，第二密封件18是通过MAP处理或包括用于器件的单个腔的模具产生的。此外，第二密封件18覆盖第一密封件17的顶表面和两个侧表面，以及第二密封件的侧面接触板10的顶部。
图2F示出了器件上的可选BGA连附处理，对应于结合图1F描述的处理，利用各个腔模塑该器件的第一密封件。
图3中示出了与图1A至1F(或图1A至1C和2D至2F)中示出的处理相关的流程图。图3中的步骤30对应于参考图1A描述的浆料分配步骤。步骤31对应于参考图1B描述的管芯接合步骤，以及步骤32对应于参考图1C描述的线接合步骤。步骤33对应于参考图1D(或图2D)描述的第一或主模塑密封处理，以及步骤34对应于参考图1E(或图2E)描述的第二模塑密封处理。步骤35对应于参考图1F(或图2F)描述的可选的BGA连附处理，以及步骤36对应于也是参考图1F(或图2F)描述的切单步骤。再一次地，应该注意对于BGA器件，焊球可以在切单步骤之前或之后被连附。
现在参考图4A，衬底或引线框板40表示切单之前的条带中的一个板或这样的板的阵列(未示出)。板40在结构和组分上可以类似于上述板10。
如图4A中所示，第一层粘性浆料41应用于板40上的管芯连附盘。电磁屏蔽箔层42以任何适当的形式和通过任何适当的方式被应用于该粘性浆料层41。第二层粘性浆料43被应用于屏蔽箔42，如图4C所示。
如图4D中所示，使用如上所述的拾取和放置工具将半导体管芯44相应地放置在第二层粘性浆料43上。粘性浆料固化之后，如图4E中所示，使用如上所述的可商业获得的线接合设备，通过导线45将每个半导体管芯44电耦合至板40上的引线接头(未示出)。
在导线45接合到管芯44之后，执行第一模塑密封处理以在管芯44和导线45上形成第一模盖或密封件46，如图4F中所示。第一密封件46在组分上类似于上述的第一密封件14之处在于优选地不提供电磁屏蔽功能。
在主模塑密封处理完成之后，执行第二模塑密封处理以在第一密封件46上形成第二模盖或密封件47，如图4G中所示。第二密封件47在组分上可以类似于上述的第二密封件15，其优选地提供至少电磁屏蔽功能。
在BGA产品的情况下，在第二模塑密封处理之后可以进行焊球连附处理，如图4H所示。
在第二模塑密封处理之后，通过将器件彼此切单而形成各个器件。
在一些实施例中，图4F至4H中示出的主模塑密封处理和第二模塑密封处理可以如图5F至5H中所示地被更改。图5F中示出的处理类似于图4F中示出的处理，不同之处在于通过使用用于每个器件的单个腔利用传统模具产生第一密封件48。
图5G中示出的处理还类似于图4G中示出的处理，不同之处在于通过MAP处理或通过包括用于每个模盖的单个腔的模具来形成第二密封件49。
图5H示出了产品上的可选BGA连附处理，与参考图4H描述的处理相对应的，利用单个腔来模塑该产品的第一密封件。
图6中示出了与图4A至4H(或图4A至4E和图5F至5H)中示出的处理相关的流程图。图6中的步骤60对应于参考图4A描述的第一浆料的分配步骤。步骤61对应于参考图4B描述的磁箔放置，以及步骤62对应于参考图4C描述的第二浆料分配步骤。步骤63对应于参考图4D描述的管芯接合步骤，步骤64对应于参考图4E描述的线接合步骤。步骤65对应于参考图4F(或图5F)描述的第一或主模塑密封处理，步骤66对应于参考图4G(或图5G)描述的第二模塑密封处理。步骤67对应于参考图4H(或图5H)描述的BGA连附处理，步骤68对应于也是参考图4H(或图5H)描述的切单步骤。
现在参考图7A，衬底或引线框板70表示切单之前的条带中的一个板或这样的板的阵列(未示出)。板70可以在结构和组分上类似于上述的板10和40。
如图7A中所示，第一层粘性浆料71应用于板70上的管芯连附盘。使用如上所述的拾取和放置工具，将在其底层处具有磁性金属73的半导体管芯72放置在粘性浆料71的相应层上。粘性浆料71固化之后，如图7C中所示，使用上述的可商业获得的线接合设备，通过导线74将每个半导体管芯72电耦合到板70上的引线接头(未示出)。
在导线74接合到管芯72之后，如图7D中所示，进行主模塑密封处理以在管芯72和导线74上形成第一模盖或密封件75。第一密封件75在组分上类似于上述的第一密封件14和46之处在于其优选地不提供电磁屏蔽功能。
在完成主模塑密封处理之后，如图7E中所示，执行第二模塑密封处理以在第一密封件75上形成第二模盖或密封件76。第二密封件76在组分上类似于上述的第二密封件15或47之处在于其至少提供电磁屏蔽功能。
在BGA产品的情况下，如图7F中所示，在第二模塑密封处理之后，可以进行焊球连附处理。
在第二模塑密封处理(以及在BGA产品的情况下的焊球连附处理)之后，各个器件被切单或与模塑阵列组件分开。
在一些实施例中，如图8D至8F中所示，可以改变图7D至7F中示出的主模塑密封处理和第二模塑密封处理。图8D中示出的处理类似于图7D中示出的处理，不同之处在于第一密封件77是通过用于每个模盖的单个腔形式的传统模具产生的。
图8E中示出的处理还类似于图7E中的处理，不同之处在于第二密封件78可以是通过MAP处理或通过包括用于每个模盖的单个腔的模具产生的。
图8F示出了产品上的可选BGA连附处理，与参考图7F描述的处理相对应的，利用单个腔来模塑该产品的第一密封件。
图9中示出了与图7A至7F(或图7A至7C和图8D至8F)中示出的处理相关的流程图。图9中的步骤90对应于参考图7A描述的第一浆料分配步骤。步骤91对应于参考图7B描述的管芯接合步骤，以及步骤92对应于参考图7C描述的线接合步骤。步骤93对应于参考图7D(或图8D)描述的第一或主模塑密封处理，以及步骤94对应于参考图7E(或图8E)描述的第二模塑密封处理。步骤95对应于参考图7F(或图8F)描述的BGA焊球连附处理，以及步骤96对应于也是参考图7F(或图8F)描述的切单步骤。
参考图10A，衬底或引线框板100表示切单之前的条带中的一个板或这样的板的阵列(未示出)。板100可以在组分上类似于上述的板10和40。
如图10B中所示，在其有效表面上具有焊球101的半导体管芯102被放置为活性表面向下在板100上。该组件被放置在回流炉中或暴露于红外加热，这使得焊球熔化并焊接至引线接头。
为了解决机械应力问题，在管芯接合和焊球连附处理之后，进行底部填充处理，如图10C中所示，其中底部填充材料103被注入在管芯102和板100之间。底部填充材料103可以是现有技术中已知的环氧混合物。在底部填充处理之后对底部填充材料进行固化。
在完成底部填充处理之后，如图10D中所示，执行主模塑密封处理以在管芯102上形成第一模盖或密封件104。第一密封件104可以在组分上类似于如上所述的第一密封件14、46和75，类似之处在于其优选地不提供电磁屏蔽功能。
在主模塑密封处理完成之后，如图10E中所示，执行第二模塑密封处理以在第一密封件104上形成第二模盖或密封件105。第二密封件105可以在组分上类似于上述的密封件15、47或76，类似之处在于其至少提供电磁屏蔽功能。
在BGA产品的情况下，在第二模塑密封处理之后，可以进行焊球连附处理，如图10F所示。
在第二模塑密封处理之后，各个器件被切单或与模制阵列组件分开。
在一些实施例中，图10D至10F中示出的主模塑密封处理和第二模塑密封处理可以如图11D至11F中所示的被更改。图11D中示出的处理类似于图10D中示出的处理，不同之处在于通过用于每个模盖的单个腔的形式以传统模具产生第一密封件106。
图11E中示出的处理还类似于图10E中示出的处理，不同之处在于第二密封件107可以是通过MAP处理或通过包括用于每个模盖的单个腔的模具产生的。
图11F示出了产品上的可选BGA连附处理，与参考图10F描述的处理相对应的，利用单个腔来模塑该产品的第一密封件。
图12中示出了与图10A至10F(或图10A至10C和图11D至11F)中示出的处理相关的流程图。图12中的步骤120对应于参考图10A描述的焊剂分配。步骤121对应于参考图10B描述的倒装芯片接合以及回流步骤，以及步骤122对应于参考图10C描述的底部填充和固化步骤。步骤123对应于参考图10D(或图11D)描述的第一或主模塑密封处理，以及步骤124对应于参考图10E(或图11E)描述的第二模塑密封处理。步骤125对应于参考图10F(或图11F)描述的BGA连附处理，以及步骤126对应于也参考图10F(或图11F)描述的切单步骤。
最后，应该理解在不背离本发明的精神或范围的情况下，各种替换、修改和/或增加可以被引入至上述部件的结构和布置中。

Claims (10)

1.一种装配集成电路IC器件的方法，包括以下步骤：
提供引线框或衬底板；
将半导体管芯连附至所述引线框或衬底板；
电耦合所述半导体管芯至所述引线框或衬底板；
使用第一密封件密封所述半导体管芯，其中所述第一密封件至少覆盖所述半导体管芯的顶部和两个侧表面；以及
使用第二密封件密封所述第一密封件，其中所述第二密封件包括提供电磁屏蔽功能的材料，以及其中所述第二密封件至少覆盖所述第一密封件的顶部和两个侧表面。
2.根据权利要求1所述的装配IC器件的方法，其中所述第二密封件包括导体材料和金属微粒，用于为所述IC器件提供电屏蔽。
3.根据权利要求1所述的装配IC器件的方法，其中所述第二密封件包括非导磁微粒，用于为所述IC器件提供磁屏蔽。
4.根据权利要求1所述的装配IC器件的方法，其中所述第一密封件不提供磁屏蔽功能。
5.根据权利要求1所述的装配IC器件的方法，还包括使所述半导体管芯的底表面与所述引线框或衬底板屏蔽的步骤。
6.根据权利要求5所述的装配IC器件的方法，其中所述屏蔽步骤包括在所述半导体器件和所述引线框或衬底板之间布置金属箔。
7.根据权利要求5所述的装配IC器件的方法，其中所述屏蔽步骤包括在所述管芯连附步骤之前在所述半导体管芯上进行背面金属化处理。
8.一种装配集成电路IC器件的方法，包括以下步骤：
提供引线框或衬底板；
将半导体管芯连附至所述引线框或衬底板；
使所述半导体管芯的底表面与所述引线框或衬底板屏蔽；
电耦合所述半导体管芯至所述引线框或衬底板；
使用第一密封件密封所述半导体管芯，其中所述第一密封件至少覆盖所述半导体管芯的顶部和两个侧表面；以及
使用第二密封件密封所述第一密封件，其中所述第二密封件包括提供电磁屏蔽功能的材料，以及其中所述第二密封件至少覆盖所述第一密封件的顶部和两个侧表面。
9.一种集成电路IC器件，包括：
引线框或衬底板；
半导体管芯，连附并电耦合至所述引线框或衬底板；
第一密封件，至少覆盖所述半导体管芯的顶部和两个侧表面；以及
第二密封件，至少覆盖所述第一密封件的顶部和两个侧表面，其中所述第二密封件包括提供电磁屏蔽功能的材料。
10.根据权利要求9所述的IC器件，还包括布置在所述半导体管芯和所述引线框或衬底板之间的屏蔽件。
CN201010236800.5A 2010-07-21 2010-07-21 装配集成电路器件的方法 Active CN102339763B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201010236800.5A CN102339763B (zh) 2010-07-21 2010-07-21 装配集成电路器件的方法
US13/092,162 US8536684B2 (en) 2010-07-21 2011-04-22 Method of assembling shielded integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201010236800.5A CN102339763B (zh) 2010-07-21 2010-07-21 装配集成电路器件的方法

Publications (2)

Publication Number Publication Date
CN102339763A true CN102339763A (zh) 2012-02-01
CN102339763B CN102339763B (zh) 2016-01-27

Family

ID=45492913

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201010236800.5A Active CN102339763B (zh) 2010-07-21 2010-07-21 装配集成电路器件的方法

Country Status (2)

Country Link
US (1) US8536684B2 (zh)
CN (1) CN102339763B (zh)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016033794A1 (zh) * 2014-09-05 2016-03-10 中国科学院微电子研究所 一种封装方法及电子系统产品
US9685605B2 (en) 2015-03-30 2017-06-20 Kabushiki Kaisha Toshiba Magnetic memory device having a magnetic shield structure
CN107195600A (zh) * 2017-06-20 2017-09-22 广东美的制冷设备有限公司 芯片封装结构
CN107622980A (zh) * 2016-07-14 2018-01-23 住友电木株式会社 半导体装置及其制造方法、半导体密封用环氧树脂组合物
CN108666301A (zh) * 2017-03-30 2018-10-16 意法半导体公司 为半导体管芯提供电磁干扰屏蔽的线上流动管芯贴装薄膜和传导模塑料

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8661653B2 (en) * 2010-07-28 2014-03-04 United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Methods of making Z-shielding
KR20150022990A (ko) * 2012-06-08 2015-03-04 히타치가세이가부시끼가이샤 반도체 장치의 제조 방법
JP5813596B2 (ja) * 2012-08-10 2015-11-17 株式会社東芝 不揮発性半導体記憶装置
US9620413B2 (en) 2012-10-02 2017-04-11 STATS ChipPAC Pte. Ltd. Semiconductor device and method of using a standardized carrier in semiconductor packaging
US9496195B2 (en) 2012-10-02 2016-11-15 STATS ChipPAC Pte. Ltd. Semiconductor device and method of depositing encapsulant along sides and surface edge of semiconductor die in embedded WLCSP
US9721862B2 (en) 2013-01-03 2017-08-01 STATS ChipPAC Pte. Ltd. Semiconductor device and method of using a standardized carrier to form embedded wafer level chip scale packages
US9704824B2 (en) 2013-01-03 2017-07-11 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming embedded wafer level chip scale packages
CN104882386B (zh) 2014-02-27 2019-03-01 恩智浦美国有限公司 半导体器件格栅阵列封装
US10103037B2 (en) * 2014-05-09 2018-10-16 Intel Corporation Flexible microelectronic systems and methods of fabricating the same
DE102014217260A1 (de) * 2014-08-29 2016-03-17 Robert Bosch Gmbh Halbleiterbauelement und Verfahren zum Herstellen von Halbleiterbauelementen
JP6280014B2 (ja) * 2014-09-30 2018-02-14 新光電気工業株式会社 半導体装置及びその製造方法
JP6353763B2 (ja) * 2014-09-30 2018-07-04 新光電気工業株式会社 半導体装置及びその製造方法
JP6233285B2 (ja) * 2014-11-28 2017-11-22 三菱電機株式会社 半導体モジュール、電力変換装置
FR3031256B1 (fr) * 2014-12-30 2017-01-13 Thales Sa Boitier hyperfrequence a encombrement reduit en surface et montagne d'un tel boitier sur un circuit.
KR102354370B1 (ko) * 2015-04-29 2022-01-21 삼성전자주식회사 쉴딩 구조물을 포함하는 자기 저항 칩 패키지
US20170032857A1 (en) 2015-07-30 2017-02-02 U.S.A. as represented by the Adminstrator of the National Aeronautics and Space Administration Atomic Number (Z) Grade Shielding Materials and Methods of Making Atomic Number (Z) Grade Shielding
WO2017034515A1 (en) * 2015-08-21 2017-03-02 Hewlett-Packard Development Company, L.P. Circuit package
KR101896435B1 (ko) * 2016-11-09 2018-09-07 엔트리움 주식회사 전자파차폐용 전자부품 패키지 및 그의 제조방법
US10014260B2 (en) 2016-11-10 2018-07-03 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method for forming the same
US10600522B2 (en) 2017-04-10 2020-03-24 United States Of America As Represented By The Administrator Of Nasa Method of making thin atomic (Z) grade shields

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5237205A (en) * 1989-10-02 1993-08-17 Advanced Micro Devices, Inc. Ground plane for plastic encapsulated integrated circuit die packages
US5436203A (en) * 1994-07-05 1995-07-25 Motorola, Inc. Shielded liquid encapsulated semiconductor device and method for making the same
CN1433573A (zh) * 2000-03-30 2003-07-30 Ats服务有限公司 具有窗口盖的、无引线的半导体产品封装装置及其封装方法
US20080265421A1 (en) * 2007-04-30 2008-10-30 Infineon Technologies Ag Structure for Electrostatic Discharge in Embedded Wafer Level Packages

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5557142A (en) 1991-02-04 1996-09-17 Motorola, Inc. Shielded semiconductor device package
US5166772A (en) 1991-02-22 1992-11-24 Motorola, Inc. Transfer molded semiconductor device package with integral shield
US5294826A (en) 1993-04-16 1994-03-15 Northern Telecom Limited Integrated circuit package and assembly thereof for thermal and EMI management
US5679975A (en) 1995-12-18 1997-10-21 Integrated Device Technology, Inc. Conductive encapsulating shield for an integrated circuit
JPH10247696A (ja) 1997-03-04 1998-09-14 Sumitomo Kinzoku Electro Device:Kk 半導体パッケージ気密封止用金属製蓋体
JPH10284873A (ja) 1997-04-04 1998-10-23 Hitachi Ltd 半導体集積回路装置およびｉｃカードならびにその製造に用いるリードフレーム
US6054754A (en) 1997-06-06 2000-04-25 Micron Technology, Inc. Multi-capacitance lead frame decoupling device
US6211462B1 (en) 1998-11-05 2001-04-03 Texas Instruments Incorporated Low inductance power package for integrated circuits
JP3062192B1 (ja) 1999-09-01 2000-07-10 松下電子工業株式会社 リ―ドフレ―ムとそれを用いた樹脂封止型半導体装置の製造方法
US6734552B2 (en) 2001-07-11 2004-05-11 Asat Limited Enhanced thermal dissipation integrated circuit package
JP2005536059A (ja) * 2002-08-14 2005-11-24 ハネウェル・インターナショナル・インコーポレーテッド 電子回路からの電磁放射を低減する方法及び装置
US7030469B2 (en) * 2003-09-25 2006-04-18 Freescale Semiconductor, Inc. Method of forming a semiconductor package and structure thereof
US7015587B1 (en) 2004-09-07 2006-03-21 National Semiconductor Corporation Stacked die package for semiconductor devices
US20090000815A1 (en) * 2007-06-27 2009-01-01 Rf Micro Devices, Inc. Conformal shielding employing segment buildup

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5237205A (en) * 1989-10-02 1993-08-17 Advanced Micro Devices, Inc. Ground plane for plastic encapsulated integrated circuit die packages
US5436203A (en) * 1994-07-05 1995-07-25 Motorola, Inc. Shielded liquid encapsulated semiconductor device and method for making the same
CN1433573A (zh) * 2000-03-30 2003-07-30 Ats服务有限公司 具有窗口盖的、无引线的半导体产品封装装置及其封装方法
US20080265421A1 (en) * 2007-04-30 2008-10-30 Infineon Technologies Ag Structure for Electrostatic Discharge in Embedded Wafer Level Packages

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016033794A1 (zh) * 2014-09-05 2016-03-10 中国科学院微电子研究所 一种封装方法及电子系统产品
US9685605B2 (en) 2015-03-30 2017-06-20 Kabushiki Kaisha Toshiba Magnetic memory device having a magnetic shield structure
CN107622980A (zh) * 2016-07-14 2018-01-23 住友电木株式会社 半导体装置及其制造方法、半导体密封用环氧树脂组合物
CN107622980B (zh) * 2016-07-14 2023-02-14 住友电木株式会社 半导体装置及其制造方法、半导体密封用环氧树脂组合物
CN108666301A (zh) * 2017-03-30 2018-10-16 意法半导体公司 为半导体管芯提供电磁干扰屏蔽的线上流动管芯贴装薄膜和传导模塑料
CN108666301B (zh) * 2017-03-30 2022-08-12 意法半导体公司 为半导体管芯提供电磁干扰屏蔽的线上流动管芯贴装薄膜和传导模塑料
CN107195600A (zh) * 2017-06-20 2017-09-22 广东美的制冷设备有限公司 芯片封装结构

Also Published As

Publication number Publication date
CN102339763B (zh) 2016-01-27
US8536684B2 (en) 2013-09-17
US20120018858A1 (en) 2012-01-26

Similar Documents

Publication Publication Date Title
CN102339763B (zh) 装配集成电路器件的方法
CN104051395B (zh) 芯片堆叠封装及其方法
JP4805901B2 (ja) 半導体パッケージ
US9064781B2 (en) Package 3D interconnection and method of making same
TWI419243B (zh) 一種積體電路封裝體及其製造方法
US20130295723A1 (en) Package 3D Interconnection and Method of Making Same
US8466539B2 (en) MRAM device and method of assembling same
US8247898B2 (en) Semiconductor device and semiconductor device mounted structure
CN100568498C (zh) 半导体器件及其制造方法
WO2007083352A1 (ja) 半導体装置およびその製造方法
CN104428892A (zh) 用于基板核心层的方法和装置
US9099294B1 (en) Molded leadframe substrate semiconductor package
EP4030475A1 (en) Encapsulation structure and electronic apparatus
US9123629B2 (en) Chip package and method for forming the same
CN107680912A (zh) Emi防护的芯片封装结构及封装方法
CN108695269A (zh) 半导体装置封装及其制造方法
CN109640521A (zh) 制造具有嵌入式集群的部件承载件的方法以及部件承载件
KR20150092015A (ko) 박형 샌드위치 임베디드 패키지
US6833619B1 (en) Thin profile semiconductor package which reduces warpage and damage during laser markings
CN108321092B (zh) 电路部件的制造方法和电路部件
CN111384031B (zh) 封装元件及其制备方法
CN101183673A (zh) 堆叠式多芯片半导体封装结构及封装方法
JP6802314B2 (ja) 半導体パッケージ及びその製造方法
TWI287433B (en) Semiconductor device package and manufacturing method thereof
CN112312678A (zh) 无封装芯片直埋印制电路板的结构和方法、芯片封装结构

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CP01 Change in the name or title of a patent holder
CP01 Change in the name or title of a patent holder

Address after: Texas in the United States

Patentee after: NXP America Co Ltd

Address before: Texas in the United States

Patentee before: Fisical Semiconductor Inc.