CN102339757A - 用于制造具有玻璃衬底的半导体器件的方法 - Google Patents

用于制造具有玻璃衬底的半导体器件的方法 Download PDF

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CN102339757A
CN102339757A CN2011101983694A CN201110198369A CN102339757A CN 102339757 A CN102339757 A CN 102339757A CN 2011101983694 A CN2011101983694 A CN 2011101983694A CN 201110198369 A CN201110198369 A CN 201110198369A CN 102339757 A CN102339757 A CN 102339757A
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glass substrate
semiconductor
semiconductor wafer
opening
cavity
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CN102339757B (zh
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G.莱克纳
M.奥托维茨
K.施雷特林格
C.冯科布林斯基
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Infineon Technologies Austria AG
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Infineon Technologies Austria AG
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Abstract

本发明涉及用于制造具有玻璃衬底的半导体器件的方法。公开一种用于制造半导体器件的方法。提供具有第一表面和与第一表面相对的第二表面的半导体晶片。提供第一玻璃衬底,所述第一玻璃衬底在结合表面处具有空腔和开口中的至少一个。第一玻璃衬底被结合到半导体晶片的第一表面,使得金属焊盘被布置在第一玻璃衬底的相应空腔或开口内。半导体晶片的第二表面被机械加工。在半导体晶片的被机械加工的第二表面上形成至少一个金属化区域。

Description

用于制造具有玻璃衬底的半导体器件的方法
技术领域
本描述提及具有玻璃衬底的半导体器件的实施例。在下文中也描述了用于制造具有玻璃衬底的半导体器件的方法的实施例。一个或多个实施例涉及功率半导体器件。
背景技术
为了改善半导体器件的器件特性,已尝试减小半导体材料的最终厚度(尤其是对于功率半导体器件)。期望的是,这种器件的半导体芯片具有刚好足够用于容纳器件或电路的厚度。
由于易碎的半导体材料一旦被减薄就易于折断,所以薄半导体芯片和晶片的制造和处理是复杂的。为改善减薄的半导体材料的机械稳定性,已开发了载体系统,所述载体系统可以被分类为可逆和不可逆载体系统。
不可逆载体系统包括被不可逆地附着到半导体材料的载体。可逆载体系统包括被可逆地连接到半导体材料的载体,即芯片可以在不被损坏的情况下从载体分离,使得载体不将是完成的半导体器件的一部分。与使用哪个载体系统无关,它将与半导体材料一起至少在某种程度上经受各种处理。所述处理的一些在高温下执行。载体和半导体材料之间的结合连接必须经得起这样的高温。
可逆载体系统通常包括仅可以短时间忍受中等温度(例如高达250℃)的结合连接。可逆载体系统可以经得起更高的温度。
然而,通常已知的载体系统仅仅机械地支撑易碎的半导体材料并且便于处理。此外,当在薄半导体衬底上形成厚金属化区域时,衬底可能由于厚金属化而变形。
发明内容
由于这些和其它原因,存在对本发明的需要。
附图说明
附图被包括以提供对实施例的进一步理解,并且被并入本说明书以及构成本说明书的一部分。附图示出实施例并且与描述一起用来解释实施例的原理。其它实施例以及实施例的许多预期优点将容易理解,因为它们通过参考以下详细描述而变得更好理解。附图的元件不一定相对于彼此按比例绘制。相似的参考数字表示对应的类似部件。
图1A到1E示出根据一个实施例的用于制造半导体器件的方法的过程。
图2A到2H示出根据一个实施例的用于制造半导体器件的方法的过程。
图3示出根据一个实施例的半导体器件,诸如功率半导体器件。
图4示出图2F的细节的放大图。
图5A到5D示出根据一个实施例的用于制造半导体器件的方法的过程。
图6A到6C示出根据一个实施例的用于制造半导体器件的方法的过程。
图7A到7B示出根据一个实施例的用于制造半导体器件的方法的过程。
图8A到8B示出根据一个实施例的用于制造半导体器件的方法的过程。
图9A到9C示出根据一个实施例的用于制造半导体器件的方法的过程。
具体实施方式
在以下详细描述中,参考附图,这些附图形成了本文件的一部分并且在这些图中通过说明的方式示出了其中可以实施本发明的具体实施例。在这点上,方向性术语,诸如“顶部”、“底部”、“前”、“后”、“前部”、“尾部”等等,是参考所描述的(一幅或多幅)图的取向来使用的。由于实施例的部件可以被定位在许多不同的取向上,因此方向性术语用于说明的目的并且决不是进行限制。要理解的是,可以利用其它实施例并且可以做出结构或逻辑改变而不脱离本发明的范围。因此,以下详细描述不要在限制性意义上进行理解,并且本发明的范围由所附权利要求来限定。被描述的实施例使用具体语言,其不应当被理解为限制所附权利要求的范围。
要理解的是,除非另外明确指出,在此描述的各个实施例的特征可以彼此组合。例如,作为一个实施例的一部分示出或描述的特征可以连同其它实施例的特征一起使用以又产生另外的实施例。意图是本描述包括这样的修改和变型。
如在本说明书中使用的术语“横向”旨在描述平行于半导体衬底的主表面的取向。
如在本说明书中使用的术语“竖直”旨在描述垂直于半导体衬底的主表面布置的取向。
在本说明书中,半导体衬底的第二表面被认为是由下表面或背面表面形成,而第一表面被认为是由半导体衬底的上、前或主表面形成。如在本说明书中使用的术语“在…上”、“在…下面”因此在考虑该取向的情况下描述一个结构特征与另一个结构特征的相对位置。
如在本说明书中使用的术语“半导体部件”旨在描述在半导体晶片中或在半导体晶片上至少部分地处理的半导体器件。部分地处理意味着半导体器件没有完全完成并且需要另外的过程,诸如掺杂区域、接触区域和金属化的形成、以及切割,以获得可操作的半导体器件。
半导体器件至少是两端器件,示例是二极管。半导体器件也可以是三端器件,诸如举几个来说场效应晶体管(FET)、绝缘栅双极晶体管(IGBT)、结型场效应晶体管(JFET)、以及晶闸管。半导体器件也可以包括三个以上的端子。
在此描述的具体实施例涉及(而不限于此)功率半导体器件并且尤其涉及通过场效应进行控制的器件。
根据一个或多个实施例,提供一种用于制造半导体器件的方法。提供具有第一表面和与第一表面相对的第二表面的半导体晶片,其中所述半导体晶片包括布置在第一表面上或在第一表面处的多个掺杂区域和金属焊盘。提供第一玻璃衬底,所述第一玻璃衬底具有结合表面以及在结合表面处的空腔和开口中的至少一个。第一玻璃衬底利用它的结合表面而结合到半导体晶片的第一表面,使得金属焊盘被布置在第一玻璃衬底的相应空腔或开口内。半导体晶片的第二表面被机械加工(machine)以减小半导体晶片的厚度。在半导体晶片的被机械加工的第二表面上形成至少一个金属化区域,并且切割半导体晶片和第一玻璃衬底以获得分离的半导体器件。
根据一个或多个实施例,提供一种用于制造半导体器件的方法。提供半导体晶片和玻璃衬底。在玻璃衬底中沿预先限定的折断线形成沟槽。玻璃衬底被结合到半导体晶片,并且通过沿沟槽折断来切割半导体晶片和玻璃衬底。
参考图1A到1E,描述用于制造半导体器件的方法的第一实施例。提供半导体晶片10,所述半导体晶片10包括第一表面11和与第一表面11相对布置的第二表面12。半导体晶片10包括在图1A中未示出的多个掺杂区域。示出已完成半导体器件的放大细节的图2H和3包括掺杂区域。掺杂区域例如形成在第一表面11处并且形成例如二极管的阳极区域。在FET的情况下,掺杂区域可以是体区域和/或源区域。
半导体衬底10可以由适合于制造半导体器件的任何半导体材料制成。这种材料的示例包括(而不限于此)举几个来说元素半导体材料(诸如硅(Si))、IV族化合物半导体材料(诸如碳化硅(SiC)或锗硅(SiGe))、二元,三元或四元III-V半导体材料(诸如砷化镓(GaAs)、磷化镓(GaP)、磷化铟(InP)、氮化镓(GaN)、铝镓氮(AlGaN)、铟镓磷(InGaPa)或铟镓砷磷(InGaAsP))、以及二元或三元II-VI半导体材料(诸如碲化镉(CdTe)和碲镉汞(HgCdTe))。上述半导体材料也被称作同质结半导体材料。当组合两种不同的半导体材料时形成异质结半导体材料。异质结半导体材料的示例包括(而不限于此)硅(SixC1-x)和SiGe异质结半导体材料。对于功率半导体应用而言,目前主要使用Si、SiC和GaN材料。
金属焊盘14、15被布置在第一表面11上。金属焊盘14可以是例如栅焊盘结构,而金属焊盘15可以是例如源焊盘结构。
半导体晶片10包括多个普通处理的半导体部件,即仍未完成的半导体器件。图1A通过指示几个形成在半导体晶片10中的半导体部件31、32、33和34来对此举例说明。在该实施例中,每个半导体部件31、32、33和34包括一个金属焊盘14和一个金属焊盘15。金属焊盘14、15可以由相同金属或由不同金属构成。此外,金属焊盘14、15可以有不同的高度和结构。例如,用作源金属化的金属焊盘通常将大于用作栅金属化的金属焊盘。
根据一个或多个实施例,完成用于在第一表面11处形成半导体部件31、32、33和34的结构的过程。这通常包括金属焊盘14、15的形成,所述金属焊盘14、15稍后被用作用于结合线连接的着陆焊盘(landing pad)。
根据一个或多个实施例,半导体部件31、32、33和34也可以是半完成的。通常,包括位于第一表面11处或附近的掺杂区域的大部分结构已经形成。
如图1B中所示,提供具有结合表面22的第一玻璃衬底20。第一玻璃衬底20包括在结合表面处的空腔和开口中的至少一个。在本实施例中,第一玻璃衬底20包括形成在结合表面22处的多个空腔21。在其它实施例中,参见例如图5A到5D,玻璃衬底包括开口。
在本说明书中,空腔仅对玻璃衬底的结合表面敞开,而开口对玻璃衬底的结合表面敞开并且对与结合表面相对的表面敞开。因此,空腔是单侧敞开而开口是双侧敞开。
空腔21的尺寸适于容纳相应半导体部件31、32、33和34的金属焊盘14、15。在该实施例中,每个空腔21被定尺寸以容纳金属焊盘14、15两者。在其它实施例中,参见例如图6A和6D,空腔被定尺寸以仅容纳金属焊盘中的一个。
第一玻璃衬底20利用它的结合表面20被结合到半导体晶片20的第一表面11,使得金属焊盘14、15被布置在第一玻璃衬底20的相应空腔21内。
在另外的过程中,如图1C中所示,半导体晶片10的第二表面12被机械加工以减小半导体晶片10的厚度。机械加工可以包括用于减小半导体晶片10的厚度的任何合适的工艺。示例是机械磨削、化学机械抛光、研磨和蚀刻。机械加工半导体晶片10的第二表面12将半导体晶片10的初始厚度d1减小到目标厚度d2,所述目标厚度d2小于初始厚度。目标厚度d2可以在从大约20μm到大约100μm的范围中。在一个或多个实施例中,目标厚度d2可以从大约20μm到大约50μm。
机械加工半导体晶片10的第二表面12产生如图1C中所示的被机械加工的第二表面12'。
在图1D中示出的另外的过程中,在半导体晶片10的被机械加工的第二表面12'上形成至少一个金属化区域17、18。形成金属化区域可以包括形成薄金属种子层17以及随后形成厚金属层18。金属种子层17可以是大约0.1μm到大约2μm厚,而金属层18可以具有高达100μm的厚度。金属种子层17可以通过任何合适的工艺(诸如金属溅射或蒸发)形成。用于金属种子层17的合适材料举几个来说是银(Ag)、钛(Ti)或铝(Al)。
例如可以通过电镀或印刷来形成金属化18。种子层17实现在被机械加工的第二表面12'上的金属电镀。事实上可以在被机械加工的第二表面12'上形成任何类型的金属化。
在如图1E中示出的另外的过程中,半导体晶片10与第一玻璃衬底20一起被切割以获得分离的半导体器件。半导体晶片10和玻璃衬底20沿其被切割的分离线在图1E中由竖直虚线示出。
下面将结合图2A到2H描述根据一个或多个实施例的更详细的工艺顺序。
类似于上述实施例,提供具有第一表面11和第二表面12的半导体晶片10,如图2A中所示。此外,多个部分完成的半导体器件即半导体部件31、32、33、34形成在半导体晶片10中或在半导体晶片10上,尤其是在第一表面11处。半导体部件31、32、33、34中的每一个都包括至少一个掺杂区域和至少一个布置在第一表面11上并且与掺杂区域电接触的金属焊盘14、15。通常,半导体部件31、32、33、34有相同的类型。例如,所有半导体部件31、32、33、34都是功率FET,即三端器件。
在另外的过程中,预先结构化的第一玻璃衬底20利用它的结合表面22而结合到半导体晶片10的第一表面11。第一玻璃衬底20可以由任何合适的玻璃材料诸如纯石英或任何类型的商业上可得到的浮法玻璃构成。
空腔21形成在第一玻璃衬底20的结合表面22上。空腔21具有相应尺寸,即深度和宽度,其大得足够容纳形成在半导体晶片10的第一表面11上的半导体部件31、32、33、34的结构。
例如可以通过蚀刻来预先形成空腔21。为此,可以在结合表面22上形成限定空腔的尺寸和位置的掩模。可以使用任何合适的蚀刻工艺,例如基于氢氟酸(HF)的湿法化学蚀刻工艺。
为了将第一玻璃衬底20结合到半导体晶片10,可以采用任何合适的结合工艺。例如,可以使用阳极结合来将第一玻璃衬底20直接结合在半导体晶片10上。
当半导体晶片20的第一表面21例如被薄绝缘层覆盖时,其它结合工艺更合适。例如,玻璃粉结合提供可靠的结合连接。玻璃粉结合使用玻璃焊料,所述玻璃焊料具有比第一玻璃衬底20的熔化温度更低的熔化温度。可熔的玻璃焊料被熔化并且提供可以经得起高达500℃温度的粘性结合。合适的玻璃焊料是具有足够高含量的氧化铅以减小玻璃的粘度和熔化温度的铅玻璃。玻璃焊料例如可以被沉积在第一玻璃衬底20或半导体晶片10上作为薄玻璃层并且被预先上釉(pre-glazed)。然后半导体晶片10和第一玻璃衬底20在玻璃焊料的设计的熔化温度下进行接触。还施加压力来保持半导体晶片10和第一玻璃衬底20密切接触。
另一个选项是熔融结合。通过将半导体晶片10和第一玻璃衬底20接合在一起来执行熔融结合。为此,使半导体晶片10的第一表面11和第一玻璃衬底20的结合表面22为疏水性的或亲水性的,并且然后在高温下将两者进行接触和退火。
阳极结合、玻璃粉结合和熔融结合产生可以经得起大于500℃的极高温度的结合连接。阳极结合和熔融结合通常产生可以忍受甚至更高温度的结合连接。
也可以应用使用玻璃粘合剂的粘合剂结合。例如,可以使用硅酸盐粘合剂,所述硅酸盐粘合剂例如在商业上可从Dow Corning得到。取决于玻璃粘合剂的性质,粘合剂结合连接可以在惰性气氛中短时间经得起高达250℃至300℃的温度。这对于许多制造工艺来说足以,其中半导体晶片经受这些制造工艺来完成半导体部件。
当期望结构化时,玻璃粘合剂以及还有玻璃焊料也可以是可光结构化的。
另外的选项包括在半导体晶片10上形成类金刚石碳层(DLC)以便于阳极结合。
结合后所得到的结构在图2B中示出。
在结合第一玻璃衬底20后,半导体晶片10被减薄到目标厚度d2。减薄过程包括(而不限于此)对第二表面12的磨削、蚀刻和抛光以获得被机械加工的第二表面12'。
由于空腔并不完全延伸通过玻璃衬底20,因此在半导体晶片20的减薄期间在第一表面11上和在第一表面11处的半导体部件31、32、33、34的结构被玻璃衬底20保护。半导体部件31、32、33、34的结构因此在该处理期间被预先结构化的玻璃衬底20密封。
在另外的过程中,在半导体晶片20的第二表面22上形成薄金属种子层17。金属种子层17可以形成在整个第二表面12上。金属种子层17在稍后过程中被用于电镀金属化。当使用其它工艺来形成金属化时,可以省去金属种子层。此外,如果需要的话,也可以在稍后阶段形成种子层17。可以根据具体需要来选择金属种子层17的厚度。也可能提供具有变化厚度的金属种子层17。金属种子层17的材料可以是例如银(Ag)、钛(Ti)或铝(Al)。
提供具有形成在结合表面42处的多个空腔41的预先结构化的第二玻璃衬底40。空腔41被定尺寸成小于最终半导体器件的尺寸。图2A到2H的实施例示出具有与第一玻璃衬底20的空腔21的尺寸类似的尺寸的空腔41。
第二玻璃衬底40利用它的结合表面42而在半导体晶片10的第二表面12'处结合到半导体晶片10。当半导体晶片10的第二表面12'被薄金属种子层17覆盖时,使用如上所述的玻璃粉结合或粘合剂结合来结合第二玻璃衬底40。当不使用金属种子层17时,可以使用任何类型的上述结合工艺。所得到的结构在图2C中示出。
为获得足够的结合强度,相应玻璃衬底20、40和半导体晶片10之间的接触区域应当足够大。由于玻璃衬底20、40的相应结合表面22、42被结构化,所以接触区域也被结构化。对于许多应用而言,当相邻空腔之间的壁厚是大约50 μm或更大时,提供具有50 μm及更大的尺寸的接触区域是足够的。
在结合前第一和第二玻璃衬底20、40与半导体晶片10对准,使得相应空腔21、41与相应半导体部件31、32、33、34对准。布置在相应玻璃衬底20、40和半导体晶片10的外围区域中的对准结构便于对准。
图2D示出另外的过程。第二玻璃衬底40在它的与结合表面42相对的表面处被机械加工以暴露空腔41。通常,第二玻璃衬底40的厚度被减小直到空腔41被暴露为止,其然后在第二玻璃衬底40中形成开口41'。可以根据具体需要来选择第二玻璃衬底40的最终厚度。被机械加工的第二玻璃衬底40应当足够厚以为薄半导体晶片10提供足够的机械稳定性。第二玻璃衬底10可以被磨削或抛光或者首先被磨削并且然后被抛光。
图2E示出用于在半导体晶片10的第二表面22上制造金属化区域的过程。被机械加工的第二玻璃衬底40被用作具有限定金属化区域的尺寸和位置的暴露的空腔或开口41'的掩模。在实施例中,每个半导体部件31、32、33、34可以被提供有完全填充开口41'的一个大金属化区域19。通过将第二玻璃衬底40用作掩模,形成具有彼此分离的金属化区域19的结构化金属化。
可以通过例如电镀、印刷或裱糊(pasting)来形成金属化区域19。通常,通过金属、金属化合物或金属合金来填充暴露的空腔或开口41'。形成在半导体晶片的整个第二表面12'上的金属种子层17便于电镀,其可以是电解电镀或化学电镀。通常,以足够的厚度电镀铜以提供优良的电连接并且也提供用于在半导体器件的工作期间使热耗散的装置。另一个选项是印刷或电镀,其中导电膏剂被带到第二玻璃衬底20上并且通过刮板(squeegee)或刮刀被均匀分布。然后膏剂被退火以形成导电金属化区域。退火温度应当小于第一和第二玻璃衬底20、40与半导体晶片10之间的相应结合连接可以忍受的温度。印刷和裱糊是成本高效的工艺。由于铜的优良电属性和热属性,铜或铜化合物通常被用于印刷或裱糊。
在另外的过程中,第一玻璃衬底20被机械加工以暴露空腔21和布置在空腔21内的金属焊盘14、15。图2F中所示的所得到的结构包括具有小于空腔21的深度的厚度的第一玻璃衬底20,使得形成横向包围金属焊盘14、15的开口21'。
在一个或多个实施例中,第一和/或第二玻璃衬底20、40为半导体晶片10提供机械支撑并且形成不可逆载体系统。一个或多个玻璃衬底保持附着到半导体晶片10并且形成最终半导体器件的主要部分。一个或多个玻璃衬底的最终厚度并不限于特定值并且可以根据具体需要而改变。如在此描述的不可逆载体系统也允许处理非常薄的半导体晶片10。当使用第一和第二玻璃衬底20、40时,每个玻璃衬底可以被制得相当薄。在半导体晶片的两侧上都提供玻璃衬底也改善了机械属性,因为形成了对称支撑。
此外,一个或多个玻璃衬底可以充当器件钝化。这允许省去常用的聚酰亚胺钝化。由于玻璃优于聚酰亚胺的更好介电属性,玻璃钝化改善了电绝缘。
第二玻璃衬底40提供掩模,所述掩模允许结构化该金属化而不需要另外的掩模。这也便于随后的器件分离,如下面将描述的。
当沿图2F中由虚线指示的分离线分离电子部件31、32、33、34时,通过具有类似机械属性的材料发生分离。图2F示出分离线延伸通过第一和第二玻璃衬底20、40的壁并且也通过半导体晶片10。分离线不延伸通过金属化的厚部分(即本实施例中的金属化区域19)并且仅通过可选的薄金属种子层17。玻璃衬底20、40和半导体晶片10具有类似机械属性,因为两种材料都易碎。与此不同,厚金属化由具有与半导体晶片10和玻璃衬底20、40的机械属性不同的机械属性的韧性金属构成。机械属性的这一差别在切割期间可能造成困难,所述困难可以通过如在此描述的方法而被减小或避免。
根据一个或多个实施例,形成在半导体晶片10的第二表面12'上的背金属化被结构化以具有分离的厚金属区域,所述分离的厚金属区域彼此横向间隔开。分离的金属化区域之间的空间被用于切割;因此分离线沿所述空间延伸但不通过金属化区域。这允许金属化区域的厚度的甚至进一步增加以改善热耗散。金属化区域可以具有与玻璃衬底的厚度类似的厚度。例如,可能提供高达100μm厚或甚至更厚的金属化区域。在半导体晶片10的第二表面12上的金属化的结构化也减小了半导体晶片10的翘曲。由于所述分离不通过厚金属化,因此在分离期间分离工具(诸如锯)也未被装上金属,这改善了分离工艺。
切割通过玻璃衬底20、40和半导体晶片10而不切割通过厚金属化甚至允许通过折断进行分离。对于切割,可以使用任何合适的切割工艺,诸如划线和折断、激光切割以及锯割。可选的薄金属种子层17并不明显干扰上述切割工艺。当切割图2F中所示的结构时,形成分离的半导体器件,每个分别具有半导体芯片10'、第一玻璃芯片20'和第二玻璃芯片40'。
根据一个或多个实施例,玻璃衬底20、40的至少一些或全部壁沿相邻半导体部件之间的分离线延伸。稍后形成半导体器件的相邻半导体部件通过相应玻璃衬底20、40的壁而彼此绝缘。
图2G示出在切割后的半导体器件的三维图。也示出将在稍后阶段形成的结合线连接。如所示,金属焊盘14、15完全被具有暴露的空腔或开口21'的第一玻璃芯片20'横向包围。第一和第二玻璃芯片20'、40'连同半导体芯片10'一起具有公共横向分离表面69,在所述分离表面69处金属种子层17在存在时被暴露。因此,半导体器件的侧面69主要由半导体芯片10'的半导体材料与第一和第二玻璃芯片20'、40'的玻璃材料形成,而不是由在这里没有示出的厚金属化区域19形成。
图2H示出最终半导体器件。半导体器件被附着到由绝缘材料制成的载体衬底50。载体衬底50包括引线结构51、52、53。引线结构51和53包括布置在载体衬底50的上侧上的结合焊盘51'和53',而引线结构52包括大焊盘52',半导体器件利用它的形成在半导体芯片10'的第二表面上的金属化区域19而附着到所述大焊盘52'。金属焊盘14和结合焊盘51'之间、以及金属焊盘15和结合焊盘53'之间的电连接分别由结合线55提供。
图2H也示出半导体器件的另外的结构。金属焊盘14在该实施例中形成栅电极,所述栅电极通过栅介电层60与芯片10'的半导体材料绝缘。掺杂区域也被示出。61表示源区域而62表示与源区域61以及与芯片10'的半导体材料相反掺杂的体区域。漏区域63形成在芯片10'的第二表面处。漏区域63通过金属化区域19电连接到焊盘52',而源区域61电连接到金属焊盘15。
最终,半导体器件可以被封装在绝缘材料65诸如环氧树脂中以形成半导体模块。
虽然图2H示出三端器件诸如FET或IGBT,但图3示出根据一个或多个实施例的两端器件诸如功率二极管。
半导体器件包括至少两个端子,所述两个端子在本实施例中由引线结构56和57形成。这些引线结构从载体衬底58横向延伸。半导体器件进一步包括半导体衬底,该半导体衬底在本实施例中由具有第一表面11和第二表面12的半导体芯片10'形成。半导体芯片10'具有至少一个掺杂区域62和金属焊盘15。掺杂区域62形成在第一表面11处并且与布置在第一表面11上的金属焊盘15电接触。在本实施例中金属焊盘15形成功率二极管的阳极。掺杂区域62被与半导体芯片10'的材料相反地掺杂,在功率器件的情况下所述半导体芯片10'的材料通常具有低n掺杂浓度。另外的掺杂区域63形成在第二表面12处并且有与芯片10'的半导体材料相同的掺杂类型,但是具有更高的掺杂浓度。
具有至少一个开口21'的第一玻璃衬底或玻璃芯片20'被结合到半导体衬底10'的第一表面11,使得金属焊盘15被布置在第一玻璃衬底20'的开口21'内。具有至少一个开口41'的第二玻璃衬底或玻璃芯片40'被结合到半导体衬底10'的第二表面12。至少一个金属化区域19被布置在半导体衬底或半导体芯片10'的第二表面12上。金属化区域19填充第二玻璃衬底40'的开口41'并且在掺杂区域67和引线结构56的焊盘结构56'之间提供欧姆接触。在本实施例中金属化区域19形成功率二极管的阴极。金属种子层在本实施例中未示出,但是如果期望的话可以提供。
金属焊盘15通过结合线55电连接到引线结构57的焊盘结构57'。半导体器件被封装在绝缘材料65诸如环氧树脂中。
半导体器件具有由第一和第二玻璃衬底20' 和 40'以及半导体衬底10'形成的公共横向分离面69。
图4示出来自图2F的由点划框指示的地方的放大细节。半导体晶片10包括布置在第一表面11上的薄氧化物层70。第一玻璃衬底20通过粘合剂结合(其可以采用可光结构化的粘合剂71)、玻璃粉结合或熔融结合而被结合到该氧化物层70。在一个实施例中,氧化物层70可以被类金刚石碳层代替。在这种情况下,阳极结合也将是可能的。
因此,根据一个或多个实施例,氧化物层70或者通常是绝缘层70在结合第一玻璃衬底20之前形成在第一表面11上。
第二玻璃衬底40通过使用玻璃粘合剂层72的粘合剂结合而被半导体晶片10结合在薄金属种子层17上。为第一和第二玻璃衬底20、40选择的结合工艺取决于玻璃衬底被结合到的表面的特性。由于半导体晶片10的第一和第二表面11、12可以被不同地处理,所以相应表面可以展现不同的顶层并且因此展现不同的特性,使得将使用不同的结合工艺。
所述结合可以包括热退火工艺。当将第二玻璃衬底40结合到半导体晶片时,退火温度应当被调整为在半导体部件的热预算内并且也在半导体晶片10和第一玻璃衬底20之间的结合连接的可忍受范围内。
关于图5A到5D,描述另外的实施例。用相同的参考数字表示与上述结构特征类似的结构特征。此外,省去类似过程的描述以及包括对应的引用。
类似于上述实施例,提供具有第一表面11和第二表面12的半导体晶片10。半导体晶片10包括多个半导体部件31、32、33、34,所述多个半导体部件31、32、33、34中的每一个包括布置在第一表面11上的至少一个金属焊盘14、15。本实施例示出针对每个半导体部件31、32、33、34的两个金属焊盘14、15。此外,每个半导体部件31、32、33、34包括至少一个掺杂区域。
如图5B中所示,提供预先结构化的第一玻璃衬底25,所述第一玻璃衬底25具有多个延伸通过第一玻璃衬底25的开口26。第一玻璃衬底25包括结合表面27。可以通过合适的工艺诸如蚀刻来预先形成开口26。开口26的尺寸适于允许容纳如下面描述的金属焊盘14、15。
第一玻璃衬底25利用它的结合表面27而被结合到半导体晶片10的第一表面11,使得一个半导体部件31、32、33、34的金属焊盘14、15被布置在第一玻璃衬底25的一个开口26内。出于对准目的,使用布置在半导体晶片10和第一玻璃衬底上的对准标记。第一玻璃衬底25可以通过上述结合工艺中的任何一个而被结合到半导体晶片10。
第一玻璃衬底25具有对应于金属焊盘14、15的高度或大于所述金属焊盘的高度的厚度。随后,第一玻璃衬底25的开口26可以被可选的箔35覆盖以在随后的过程期间保护半导体部件31、32、33、34和布置在半导体晶片10的第一表面11上的结构。
在另外的过程中,半导体衬底10如上所述地被减薄到目标厚度d2。半导体衬底10然后具有经处理的第二表面12'。如上所述,薄金属种子层17形成在整个机械加工的第二表面12'上。
提供第二玻璃衬底45,所述第二玻璃衬底45具有多个延伸通过第二玻璃衬底45的开口46。第二玻璃衬底45具有结合表面47,第二玻璃衬底45通过上述合适的结合工艺中的任何一个而利用所述结合表面47被结合到半导体晶片10上,尤其是结合到金属种子层17。第一和第二玻璃衬底25、45彼此对准。箔35可以在该阶段或在稍后阶段被除去。所得到的结构在图5C中示出。
在另外的过程中,通过任何合适的工艺(诸如电镀、裱糊或印刷)在如上所述的开口46中形成相应金属化区域19。随后,沿预定的分离线(其在图5D中由虚线指示)切割半导体晶片10。如上所述,通过半导体晶片10和相应玻璃衬底25、45的壁但是不通过厚金属化区域19发生分离。
在图5A到5D中示出的实施例与上述实施例的不同之处在于预先结构化的玻璃衬底25、45包括开口26、46。不要求用于减薄玻璃衬底25、45的工艺,但是如果需要的话可以执行所述工艺。
也可能组合来自不同的实施例的工艺。例如,如上面进一步所述的具有空腔21的玻璃衬底20可以被用作第一玻璃衬底并且被结合到半导体晶片10。具有开口46的玻璃衬底45可以被用作第二玻璃衬底并且被结合到半导体晶片10的被机械加工的第二表面12'。在该变型中,当减薄半导体晶片10时在半导体晶片10的第一表面11处的结构被第一玻璃衬底20保护,因为空腔21仍没有被暴露。此外,由于第一玻璃衬底20相当厚,所以它在更大程度上稳定减薄的半导体晶片10。例如可以在被机械加工的第二表面12'上形成金属化区域19后机械加工第一玻璃衬底20以暴露半导体部件的结构,尤其是金属焊盘。
图6A到6C示出另外的实施例。用相同的参考数字表示与上述结构特征类似的结构特征。此外,省去类似过程的描述以及包括对应的引用。
提供具有第一表面11、第二表面12、以及半导体部件31、32、33、34的半导体晶片10,所述半导体部件31、32、33、34每一个包括至少两个布置在第一表面11上的金属焊盘14、15。半导体部件31、32、33、34中的每一个也包括至少一个掺杂区域,通常是多个掺杂区域。
提供玻璃衬底70,所述玻璃衬底70包括多个形成在玻璃衬底70的结合表面73处的空腔71、72。每个空腔71、72被定尺寸以允许容纳仅一个金属焊盘14、15。每个半导体部件31、32、33、34的金属焊盘14、15可以具有不同的尺寸,尤其是不同的横向范围。因此,相应空腔71、72也可以有不同的尺寸。在该特定实施例中,空腔71被定尺寸以允许容纳金属焊盘14而空腔72被定尺寸以允许容纳金属焊盘15。在该实施例中,空腔72大于空腔71。
玻璃衬底70被对准并且然后通过使用如上所述的任何合适结合工艺而被结合。所得到的结构在图6A中示出。每个金属焊盘14、15被相应空腔71、72容纳和封装,使得相同半导体部件31、32、33、34的相邻金属焊盘14、15通过玻璃衬底70并且尤其是通过布置在相邻金属焊盘14、15之间的玻璃衬底70的壁而彼此绝缘。
在另外的过程中,半导体晶片10可以被减薄。此外,玻璃衬底70可以被机械加工以暴露空腔71、72并且形成开口71'、72'以允许接近半导体部件31、32、33、34的金属焊盘14、15。相邻金属焊盘14、15通过玻璃衬底70的壁而保持彼此绝缘,如图6B中所示。在另外的过程中,如上所述地沿分离线切割半导体晶片10以形成具有半导体芯片10'和玻璃芯片70'的半导体器件。
在图6C中示出这种半导体器件的三维图示。例如分别形成功率FET的栅焊盘和源焊盘的金属焊盘14和15通过玻璃衬底70而彼此绝缘。其它结构元件可以类似于上述元件。半导体器件可以尤其包括结合到半导体芯片10'的第二表面的另外的玻璃衬底或玻璃芯片40'。
结合图7A和7B来描述另外的实施例。用相同的参考数字表示与上述结构特征类似的结构特征。此外,省去类似过程的描述以及包括对应的引用。
在本实施例中,提供半导体晶片10和结合到半导体晶片10的玻璃衬底40。玻璃衬底40包括多个开口41'以暴露半导体晶片10的表面部分。所述开口限定稍后将形成的金属化区域的尺寸和位置。玻璃衬底40利用它的结合表面42而被结合到半导体晶片10的第二表面12'。如上所述,被结合的玻璃衬底40可以在它的结合表面处包括空腔,所述空腔稍后通过磨削或抛光被结合的玻璃衬底而被暴露。在其它实施例中,玻璃衬底40可以被结合有已经暴露的空腔(即开口)。可以使用如上所述的任何合适的结合工艺。
多个半导体部件31、32、33、34的金属焊盘14、15可以被布置在半导体晶片10的第一表面11上。半导体晶片10也可以如上所述地包括多个掺杂区域。此外,金属种子层17可以在结合玻璃衬底40之前形成在第二表面12'上。
玻璃衬底40的开口41'被填充有金属或金属化合物以形成金属化区域19,如图7B中所示。用于形成金属化区域19的合适工艺是(而不限于此)电镀、印刷和裱糊。如上所述,当形成金属化区域19时,玻璃衬底40用作掩模。
在另外的过程中,如上所述地沿分离线切割半导体晶片10以获得分离的半导体器件。
结合图8A和8B来描述另外的实施例。用相同的参考数字表示与上述结构特征类似的结构特征。此外,省去类似过程的描述以及包括对应的引用。
提供包括第一表面11和第二表面12的半导体晶片10以及结合到半导体晶片10的第一表面11的玻璃衬底70。半导体晶片10包括掺杂区域以形成多个半导体部件31、32、33、34。玻璃衬底70包括暴露半导体晶片10的第一表面11的相应部分的多个开口71'、72'。所述开口71'、72'限定稍后形成的焊盘区域的尺寸和位置。
玻璃衬底70可以通过上述结合工艺中的任何一个被结合到第一表面11。通常,金属种子层可以在结合之前形成在第一表面上。当期望为相同的半导体部件31、32、33、34形成分离的焊盘区域时,金属种子层通常不形成在整个第一表面11上以避免短路。金属种子层可以在结合玻璃衬底70后形成在每个开口71'、72'内。
当如上所述地被结合时,玻璃衬底70可以已经包括开口71'、72'。在一个实施例中,玻璃衬底70可以包括多个空腔,通过在如上所述地结合后机械加工玻璃衬底来暴露所述多个空腔。
在另外的过程中,开口71'、72'被填充有金属或金属化合物诸如金属合金以提供多个分离的金属焊盘区域14'、15',如图8B中所示。金属焊盘结构14'、15'可以通过电镀、裱糊或印刷来形成以获得厚金属焊盘结构。可能需要退火工艺来完成金属焊盘区域14'、15'的制造。厚金属焊盘区域14'、15'可以被用作用于如上所述的结合线连接的着陆焊盘。由于它们的厚度,金属焊盘区域14'、15'保护在底层结构免受在结合期间发生的机械应力的影响。金属焊盘区域14'、15'的厚度可以由玻璃衬底70的厚度限定。例如,当使用100μm厚的玻璃衬底70时,金属焊盘区域14'、15'在通过裱糊形成时将具有类似的厚度。也可能形成具有其它厚度的金属焊盘区域14'、15'。
在另外的过程中,如上所述地沿分离线切割半导体晶片10以获得分离的半导体器件。
上述实施例可以被组合。例如,如图8A和8B中所示的在半导体晶片10的第一表面11上形成金属焊盘区域14'、15'可以与如图7A和7B中所示的在半导体晶片10的第二表面12'上形成金属化区域19相组合。此外,可以在如上所述地将玻璃衬底结合到第一表面11之后来减薄半导体晶片10。
结合图9A到9C来描述另外的实施例。用相同的参考数字表示与上述结构特征类似的结构特征。此外,省去类似过程的描述以及包括对应的引用。
该实施例尤其示出便于分离半导体部件以形成分离的半导体器件的选项。如图9A中所示,提供具有第一表面11和第二表面12'的半导体晶片10。至少一个玻璃衬底例如被提供在第一表面11上。在一个实施例中,玻璃衬底被提供在第二表面12'上。也可能在第一表面11上提供第一玻璃衬底80并且在第二表面12'上提供第二玻璃衬底90。
沿预先限定的折断线在第一和第二玻璃衬底80、90之一或两者中形成沟槽83。图9A示出沟槽83形成在第一玻璃衬底80中而沟槽93形成在第二玻璃衬底90中。沟槽83和93基本上彼此对准。
可以在结合玻璃衬底80、90之前或在将玻璃衬底80、90结合到相应表面11、12之后形成沟槽83、93。沟槽83、93的深度可以例如等于相应玻璃衬底80、90的厚度的至少一半或者甚至比此更大。在结合之后形成沟槽83、93允许形成深沟槽,因为否则玻璃衬底将在机械上变得非常易碎。例如可以通过锯割或通过任何其它合适的工艺来形成沟槽83、93。
如上所述,半导体晶片10可以包括多个半导体部件31、32、33、34,所述多个半导体部件31、32、33、34中的每一个可以包括布置在第一表面11上的至少一个金属焊盘14、15。相应半导体部件的金属焊盘14、15被容纳在第一玻璃衬底80的开口81内。
在第二表面12'上,可以如上所述地形成金属化区域19。
在另外的过程中,通过沿沟槽83、93折断,半导体晶片10和玻璃衬底80、90被分离成管芯。这在图9B和9C中示出,图9B和9C示出来自图9A的由点划线指示的放大细节。沟槽83、93便于折断,因为半导体晶片10与第一和第二玻璃衬底80、90的总材料强度沿沟槽83、93被明显减小。应当注意的是,开口81和91被相应玻璃衬底的壁85、95横向包围,如图2G和6C中示出的三维图示中所示。因此,这些开口81、91不提供折断线。沟槽83、93因此形成额定的(rated)折断线。
上述分离过程可以被称作“划线和折断”。此外,分离通过类似机械属性的材料且不通过形成在第二表面12'处的厚金属化区域而发生。这避免了与通常已知的分离工艺关联的困难,所述通常已知的分离工艺通过切穿易碎的半导体晶片和厚韧性金属层来分离半导体器件。由于上述实施例主要切穿类似机械属性的材料,所以切割过程可以更好地适于材料属性。
结合图9A到9C描述的实施例可以与上述实施例中的任何其它实施例组合。例如,可能结合具有空腔的玻璃衬底并且然后机械加工玻璃衬底来暴露空腔。此外,可以通过使用相应玻璃衬底作为掩模而如上所述地在第二表面上和/或在第一表面上形成金属化区域。而且,半导体晶片可以如上所述被减薄。
上面描述了不可逆载体系统,其中一个或两个结构化的玻璃衬底被结合到半导体晶片以在第一表面上或在第二表面上或在两者表面上机械地支撑半导体。一个或多个玻璃衬底甚至在切割后仍然是该器件的一部分并且可以用作钝化。此外,结构化的玻璃衬底可以用作掩模以形成分离且间隔开的金属化区域,使得对于切割而言不需要切穿金属化区域。玻璃衬底可以被结构化使得它们允许例如在第一表面上容纳金属焊盘。此外,玻璃衬底可以被结构化使得它们可以被用作例如在第一和/或第二表面上形成金属化区域的掩模。
在第一表面上或在第二表面上或在两者表面上的金属化区域的厚度可以不同并且根据具体需要来选择。在此描述的载体系统允许处理非常薄的半导体晶片。
被玻璃衬底支撑在单侧上的半导体晶片可以被减薄到期望的目标厚度。随后,另外的结构化玻璃衬底可以被结合到半导体晶片被减薄所在的一侧以获得双侧支撑的半导体晶片。所述另外的玻璃衬底在被结构化时可以被用来形成各种厚度的分离且间隔开的金属化区域。
要理解的是,除非另外具体说明,在此描述的各种示例实施例的特征可以彼此组合。
尽管在此示出并描述了具体实施例,但本领域的普通技术人员将意识到各种备选和/或等价实施方式可以替代示出和描述的具体实施例而不脱离本发明的范围。本申请旨在覆盖在此讨论的具体实施例的任何改编或变型。因此,本发明旨在仅由权利要求及其等价物来限制。

Claims (24)

1.一种用于制造半导体器件的方法,包括:
提供包括第一表面和与第一表面相对的第二表面的半导体晶片,所述半导体晶片包括布置在第一表面上或在第一表面处的多个掺杂区域和金属焊盘;
提供第一玻璃衬底,所述第一玻璃衬底包括结合表面以及在结合表面处的空腔和开口中的至少一个;
利用第一玻璃衬底的结合表面将第一玻璃衬底结合到半导体晶片的第一表面,使得一个或多个金属焊盘被布置在第一玻璃衬底的相应空腔或开口内;
机械加工半导体晶片的第二表面;
在半导体晶片的被机械加工的第二表面上形成至少一个金属化区域;以及
切割半导体晶片和第一玻璃衬底以获得分离的半导体器件。
2.根据权利要求1的方法,进一步包括通过阳极结合、粘合剂结合、熔融结合和玻璃粉结合中的至少一个而将第一玻璃衬底结合到半导体晶片的第一表面。
3.根据权利要求1的方法,进一步包括机械加工第一玻璃衬底以暴露空腔。
4.根据权利要求1的方法,进一步包括在形成金属化区域之前在半导体晶片的第二表面上形成金属种子层。
5.根据权利要求1的方法,进一步包括:
提供包括开口的第二玻璃衬底;
将第二玻璃衬底结合到半导体晶片的第二表面;以及
利用金属或金属化合物来填充第二玻璃衬底的开口以形成相应金属化区域。
6.根据权利要求1的方法,进一步包括:
提供包括结合表面和在结合表面处的空腔的第二玻璃衬底;
利用第二玻璃衬底的结合表面将第二玻璃衬底结合到半导体晶片的第二表面;
机械加工第二玻璃衬底以暴露空腔;以及
利用金属或金属化合物来填充第二玻璃衬底的暴露的空腔以形成相应金属化区域。
7.根据权利要求1的方法,其中所述金属化通过电镀、裱糊和印刷中的至少一个形成。
8.根据权利要求1的方法,进一步包括:
在第一玻璃衬底中沿预先限定的折断线提供沟槽;以及
通过沿沟槽折断来切割半导体晶片和第一玻璃衬底。
9.根据权利要求8的方法,进一步包括:
在第二玻璃衬底中沿预先限定的折断线提供沟槽;以及
通过沿沟槽折断来切割半导体晶片、第一玻璃衬底和第二玻璃衬底。
10.根据权利要求1的方法,进一步包括:
在包括至少一个结合焊盘的相应载体衬底上固定分离的半导体器件;
在金属焊盘和载体衬底的相应一个或多个结合焊盘之间形成相应线结合;以及
将固定到相应载体衬底的半导体器件封装在绝缘材料中。
11.一种用于制造半导体器件的方法,包括:
提供包括第一表面和与第一表面相对的第二表面的半导体晶片,所述半导体晶片包括布置在第一表面上或在第一表面处的多个掺杂区域和金属焊盘;
提供第一玻璃衬底,所述第一玻璃衬底包括结合表面以及形成在结合表面处的空腔;
利用第一玻璃衬底的结合表面将第一玻璃衬底结合到半导体晶片的第一表面,使得金属焊盘被布置在第一玻璃衬底的相应空腔内;
提供第二玻璃衬底,所述第二玻璃衬底包括结合表面以及形成在结合表面处的空腔;
利用第二玻璃衬底的结合表面将第二玻璃衬底结合到半导体晶片的第二表面;
机械加工第二玻璃衬底以暴露空腔;
通过电镀、裱糊和印刷中的至少一个而在第二玻璃衬底的暴露的空腔内形成金属化区域;以及
切割半导体晶片、第一玻璃衬底和第二玻璃衬底以获得分离的半导体器件。
12.根据权利要求11的方法,进一步包括在结合第二玻璃衬底之前机械加工半导体晶片的第二表面以减小半导体晶片的厚度。
13.根据权利要求11的方法,进一步包括在结合第二玻璃衬底之后机械加工第一玻璃衬底以暴露空腔。
14.一种用于制造半导体器件的方法,包括:
提供半导体晶片和结合到所述半导体晶片的玻璃衬底,其中所述玻璃衬底包括用于暴露半导体晶片的表面部分的多个开口,所述开口限定金属化区域;
利用金属或金属化合物来填充玻璃衬底的开口以形成金属化区域;以及
切割半导体晶片和玻璃衬底以获得分离的半导体器件。
15.根据权利要求14的方法,其中半导体衬底包括第一表面、第二表面、多个掺杂区域和金属焊盘,其中金属焊盘被布置在第一表面上,并且其中玻璃衬底被结合到半导体晶片的第二表面。
16.根据权利要求14的方法,其中玻璃衬底包括结合表面和形成在结合表面处的多个空腔,并且其中玻璃衬底利用它的结合表面被结合到半导体晶片,所述方法进一步包括:
机械加工玻璃衬底来暴露空腔以在玻璃衬底中形成开口;以及
利用金属或金属化合物来填充玻璃衬底中的开口以形成金属化区域。
17.根据权利要求14的方法,进一步包括:
在玻璃衬底中沿预先限定的折断线提供沟槽;以及
通过沿沟槽折断来切割半导体晶片和玻璃衬底。
18.一种用于制造半导体器件的方法,包括:
提供半导体晶片;
提供玻璃衬底;
在玻璃衬底中沿预先限定的折断线形成沟槽;
将玻璃衬底结合到半导体晶片;以及
通过沿沟槽折断来切割半导体晶片和玻璃衬底。
19.根据权利要求18的方法,其中在将玻璃衬底结合到半导体晶片之后形成沟槽。
20.根据权利要求18的方法,其中玻璃衬底包括暴露半导体晶片的部分的开口,并且其中在所述开口中形成金属化区域。
21.根据权利要求18的方法,其中玻璃衬底包括面向半导体晶片的空腔,所述方法进一步包括:
机械加工玻璃衬底来暴露空腔以在玻璃衬底中形成开口;以及
利用金属或金属化合物来填充玻璃衬底中由此形成的开口以形成金属化区域。
22.一种半导体器件,包括:
至少两个端子;
包括第一表面和第二表面的半导体衬底,所述半导体衬底包括布置在第一表面上的至少一个掺杂区域和金属焊盘;
包括至少一个开口的第一玻璃衬底,第一玻璃衬底被结合到半导体衬底的第一表面,使得金属焊盘被布置在第一玻璃衬底的开口中;
包括至少一个开口的第二玻璃衬底,第二玻璃衬底被结合到半导体衬底的第二表面;
在半导体衬底的第二表面上的至少一个金属化区域,所述金属化区域填充第二玻璃衬底的开口。
23.根据权利要求22的半导体器件,其中第一玻璃衬底、第二玻璃衬底和半导体衬底形成公共横向表面。
24.根据权利要求22的半导体器件,进一步包括载体衬底,所述载体衬底包括至少一个结合焊盘和结合线连接,所述结合线连接电连接半导体衬底的第一表面上的金属焊盘与载体衬底的结合焊盘。
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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103035520A (zh) * 2012-08-13 2013-04-10 上海华虹Nec电子有限公司 Igbt器件的制作方法
CN104167389A (zh) * 2013-05-15 2014-11-26 英飞凌科技股份有限公司 带有玻璃基板的半导体器件及其制造方法
CN105336718A (zh) * 2014-08-04 2016-02-17 英飞凌科技股份有限公司 源极向下半导体器件及其制造方法
CN107799429A (zh) * 2016-09-02 2018-03-13 英飞凌科技股份有限公司 用于形成半导体器件的方法以及半导体器件
CN107968070A (zh) * 2012-03-08 2018-04-27 英飞凌科技股份有限公司 制造半导体器件的方法
CN109920773A (zh) * 2019-01-31 2019-06-21 厦门云天半导体科技有限公司 一种基于玻璃的芯片再布线封装结构及其制作方法
CN111524820A (zh) * 2020-04-29 2020-08-11 绍兴同芯成集成电路有限公司 晶圆双面铅锡合金凸块形成工艺
CN111524819A (zh) * 2020-04-29 2020-08-11 绍兴同芯成集成电路有限公司 一种2.5d、3d封装中的玻璃载板开窗工艺及双面金属化工艺

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8202786B2 (en) 2010-07-15 2012-06-19 Infineon Technologies Austria Ag Method for manufacturing semiconductor devices having a glass substrate
US9029200B2 (en) 2010-07-15 2015-05-12 Infineon Technologies Austria Ag Method for manufacturing semiconductor devices having a metallisation layer
US8865522B2 (en) 2010-07-15 2014-10-21 Infineon Technologies Austria Ag Method for manufacturing semiconductor devices having a glass substrate
US9219020B2 (en) 2012-03-08 2015-12-22 Infineon Technologies Ag Semiconductor device, wafer assembly and methods of manufacturing wafer assemblies and semiconductor devices
US8921203B2 (en) 2012-04-27 2014-12-30 Freescale Semiconductor, Inc. Method of forming an integrated circuit having varying substrate depth
US8980676B2 (en) 2012-06-25 2015-03-17 Raytheon Company Fabrication of window cavity cap structures in wafer level packaging
US10186458B2 (en) * 2012-07-05 2019-01-22 Infineon Technologies Ag Component and method of manufacturing a component using an ultrathin carrier
DE102014105077B4 (de) 2013-04-18 2024-01-18 Infineon Technologies Austria Ag Verfahren zum Herstellen von Halbleiterbauelementen mit einem Glassubstrat, sowie Halbleiterbauelement
US9847235B2 (en) 2014-02-26 2017-12-19 Infineon Technologies Ag Semiconductor device with plated lead frame, and method for manufacturing thereof
FR3028664B1 (fr) * 2014-11-14 2016-11-25 Soitec Silicon On Insulator Procede de separation et de transfert de couches
WO2020214825A2 (en) * 2019-04-16 2020-10-22 Next Biometrics Group Asa Systems and methods for manufacturing flexible electronics
CN112234016B (zh) * 2020-10-19 2023-06-23 绍兴同芯成集成电路有限公司 一种晶圆厚膜金属层、pad金属图案的制作工艺

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5798557A (en) * 1996-08-29 1998-08-25 Harris Corporation Lid wafer bond packaging and micromachining
US20040159920A1 (en) * 2002-11-27 2004-08-19 Seiko Epson Corporation Semiconductor device, method of manufacturing the same, cover for semiconductor device, and electronic equipment
US20070099395A1 (en) * 2005-11-03 2007-05-03 Uppili Sridhar Wafer level packaging process
JP2007158212A (ja) * 2005-12-08 2007-06-21 Matsushita Electric Ind Co Ltd 電子部品とその切断方法
US20080217743A1 (en) * 2007-03-06 2008-09-11 Olympus Corporation Method of manufacturing semiconductor device and semiconductor device

Family Cites Families (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4235645A (en) 1978-12-15 1980-11-25 Westinghouse Electric Corp. Process for forming glass-sealed multichip semiconductor devices
JPS58222553A (ja) * 1982-06-18 1983-12-24 Sanyo Electric Co Ltd 半導体装置の製造方法
US5259737A (en) * 1990-07-02 1993-11-09 Seiko Epson Corporation Micropump with valve structure
US5825092A (en) 1996-05-20 1998-10-20 Harris Corporation Integrated circuit with an air bridge having a lid
US6146917A (en) * 1997-03-03 2000-11-14 Ford Motor Company Fabrication method for encapsulated micromachined structures
JP2991168B2 (ja) * 1997-09-24 1999-12-20 日本電気株式会社 半導体装置およびその製造方法
JP2000186931A (ja) * 1998-12-21 2000-07-04 Murata Mfg Co Ltd 小型電子部品及びその製造方法並びに該小型電子部品に用いるビアホールの成形方法
US6265246B1 (en) * 1999-07-23 2001-07-24 Agilent Technologies, Inc. Microcap wafer-level package
US6630725B1 (en) * 2000-10-06 2003-10-07 Motorola, Inc. Electronic component and method of manufacture
JP2002208574A (ja) * 2000-11-07 2002-07-26 Nippon Telegr & Teleph Corp <Ntt> 化学的機械研磨方法及び研磨剤
KR20030077754A (ko) * 2002-03-27 2003-10-04 삼성전기주식회사 마이크로 관성센서 및 그 제조 방법
JP4465949B2 (ja) * 2002-07-16 2010-05-26 セイコーエプソン株式会社 ダイシング方法
US6621135B1 (en) * 2002-09-24 2003-09-16 Maxim Integrated Products, Inc. Microrelays and microrelay fabrication and operating methods
US6822326B2 (en) * 2002-09-25 2004-11-23 Ziptronix Wafer bonding hermetic encapsulation
DE10245631B4 (de) 2002-09-30 2022-01-20 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Halbleiterbauelement
US7098117B2 (en) * 2002-10-18 2006-08-29 The Regents Of The University Of Michigan Method of fabricating a package with substantially vertical feedthroughs for micromachined or MEMS devices
KR100512971B1 (ko) * 2003-02-24 2005-09-07 삼성전자주식회사 솔더볼을 이용한 마이크로 전자 기계 시스템의 제조 방법
WO2005031861A1 (en) * 2003-09-26 2005-04-07 Tessera, Inc. Structure and method of making capped chips including a flowable conductive medium
JP2005243499A (ja) * 2004-02-27 2005-09-08 Fujitsu Ltd フラットディスプレイパネルの電極形成方法
US7204737B2 (en) * 2004-09-23 2007-04-17 Temic Automotive Of North America, Inc. Hermetically sealed microdevice with getter shield
TWI267927B (en) * 2005-01-19 2006-12-01 Touch Micro System Tech Method for wafer level package
KR100661169B1 (ko) 2005-06-03 2006-12-26 삼성전자주식회사 패키징 칩 및 그 패키징 방법
JP4939530B2 (ja) * 2006-03-29 2012-05-30 浜松ホトニクス株式会社 光電変換デバイスの製造方法
US7435664B2 (en) 2006-06-30 2008-10-14 Intel Corporation Wafer-level bonding for mechanically reinforced ultra-thin die
JP2008016628A (ja) 2006-07-05 2008-01-24 Sharp Corp 半導体装置及びその製造方法
EP2122670A4 (en) 2006-08-07 2013-05-15 Semi Photonics Co Ltd METHOD FOR DISCONNECTING SEMICONDUCTOR CHIPS
JP2009014469A (ja) * 2007-07-04 2009-01-22 Hitachi Ulsi Systems Co Ltd 半導体装置及びその製造方法
US7951688B2 (en) 2007-10-01 2011-05-31 Fairchild Semiconductor Corporation Method and structure for dividing a substrate into individual devices
TWI464835B (zh) * 2008-04-04 2014-12-11 Fujikura Ltd 半導體封裝體及其製造方法
JP5324890B2 (ja) * 2008-11-11 2013-10-23 ラピスセミコンダクタ株式会社 カメラモジュールおよびその製造方法
JP4851549B2 (ja) * 2009-02-10 2012-01-11 日本電波工業株式会社 圧電デバイス
JP2010187326A (ja) * 2009-02-13 2010-08-26 Seiko Instruments Inc 圧電振動子の製造方法、圧電振動子および発振器
US8202786B2 (en) 2010-07-15 2012-06-19 Infineon Technologies Austria Ag Method for manufacturing semiconductor devices having a glass substrate

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5798557A (en) * 1996-08-29 1998-08-25 Harris Corporation Lid wafer bond packaging and micromachining
US20040159920A1 (en) * 2002-11-27 2004-08-19 Seiko Epson Corporation Semiconductor device, method of manufacturing the same, cover for semiconductor device, and electronic equipment
US20070099395A1 (en) * 2005-11-03 2007-05-03 Uppili Sridhar Wafer level packaging process
JP2007158212A (ja) * 2005-12-08 2007-06-21 Matsushita Electric Ind Co Ltd 電子部品とその切断方法
US20080217743A1 (en) * 2007-03-06 2008-09-11 Olympus Corporation Method of manufacturing semiconductor device and semiconductor device

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107968070A (zh) * 2012-03-08 2018-04-27 英飞凌科技股份有限公司 制造半导体器件的方法
CN103035520A (zh) * 2012-08-13 2013-04-10 上海华虹Nec电子有限公司 Igbt器件的制作方法
CN104167389A (zh) * 2013-05-15 2014-11-26 英飞凌科技股份有限公司 带有玻璃基板的半导体器件及其制造方法
CN104167389B (zh) * 2013-05-15 2017-06-09 英飞凌科技股份有限公司 带有玻璃基板的半导体器件及其制造方法
CN105336718A (zh) * 2014-08-04 2016-02-17 英飞凌科技股份有限公司 源极向下半导体器件及其制造方法
US9911686B2 (en) 2014-08-04 2018-03-06 Infineon Technologies Ag Source down semiconductor devices and methods of formation thereof
CN105336718B (zh) * 2014-08-04 2018-06-15 英飞凌科技股份有限公司 源极向下半导体器件及其制造方法
CN107799429A (zh) * 2016-09-02 2018-03-13 英飞凌科技股份有限公司 用于形成半导体器件的方法以及半导体器件
CN107799429B (zh) * 2016-09-02 2022-02-18 英飞凌科技股份有限公司 用于形成半导体器件的方法以及半导体器件
CN109920773A (zh) * 2019-01-31 2019-06-21 厦门云天半导体科技有限公司 一种基于玻璃的芯片再布线封装结构及其制作方法
CN111524820A (zh) * 2020-04-29 2020-08-11 绍兴同芯成集成电路有限公司 晶圆双面铅锡合金凸块形成工艺
CN111524819A (zh) * 2020-04-29 2020-08-11 绍兴同芯成集成电路有限公司 一种2.5d、3d封装中的玻璃载板开窗工艺及双面金属化工艺

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