JP2007096356A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2007096356A JP2007096356A JP2007003382A JP2007003382A JP2007096356A JP 2007096356 A JP2007096356 A JP 2007096356A JP 2007003382 A JP2007003382 A JP 2007003382A JP 2007003382 A JP2007003382 A JP 2007003382A JP 2007096356 A JP2007096356 A JP 2007096356A
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- Prior art keywords
- active element
- substrate
- semiconductor device
- electrode
- external connection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
有効面積率を向上させ接合部分の耐熱応力性を向上させる。
【解決手段】
半導体基板60の所定領域に能動素子が形成され、能動素子の電極パッドと接続される外部接続用電極は、基板から分離、若しくは、他の半導体基板から形成されたブロック片であり、ブロック片と能動素子は配線基板、若しくは、他の能動素子形成した半導体基板100を介し、或いは、直接的に接合され、ブロック片、及びブロック片と接合される能動素子の電極パッド、若しくは、配線基板或いは他の半導体基板上に形成された回路パターン上には、それぞれバンプ電極121、131が形成され、各バンプ電極121、131表面にはバリアメタル膜122、132、接合金属123、133が積層形成され、バリアメタル膜122、132上に形成された接合金属123、133で接合する。
【選択図】 図1
Description
61 能動素子形成領域
62 外部接続電極
63 外部接続電極
63A 外部接続用電極領域
64 外部接続電極
64A 外部接続用電極領域
66 エピタキシャル層
66A コレクタ領域
71 ベース領域
72 エミッタ領域
75 ベース電極
76 エミッタ電極
77 接続電極
78 樹脂層
79 メッキ層
80 スリット孔
81 高濃度拡散領域
100 第2の半導体基板
101 N+埋め込み領域
102 エピタキシャル層
104 ベース領域
105 エミッタ領域
111 メッキ層
114 メッキ層
121 バンプ電極
131 バンプ電極
Claims (8)
- 第1の能動素子が形成された第1の半導体基板と、第2の能動素子が形成された第2の半導体基板とを備え、
前記第2の半導体基板は、前記第1の能動素子と前記第2の能動素子とが対向するように積層され、
前記第1の半導体基板は、前記第1の能動素子と絶縁分離され、且つ、前記第1の半導体基板の表面と裏面とを電気的に接続する外部接続電極部を備え、
前記第1の能動素子は、前記第2の能動素子を介して前記外部接続電極部と電気的に接続されていることを特徴とする半導体装置。 - 前記第2の能動素子は、前記第1の能動素子上および前記外部接続電極部上に配置されていることを特徴とする請求項1に記載の半導体装置。
- 前記第1の能動素子と前記第2の能動素子とは、第1のバンプ電極部を介して接続されており、
前記第2の能動素子と前記外部接続電極部とは、第2のバンプ電極部を介して接続されていることを特徴とする請求項2に記載の半導体装置。 - 前記第2の能動素子は、前記外部接続電極部上にまで延在した延在配線と接続されていることを特徴とする請求項2または請求項3に記載の半導体装置。
- 前記延在配線と前記外部接続電極部とは、第3のバンプ電極部を介して接続されていることを特徴とする請求項4に記載の半導体装置。
- 前記第2の半導体基板の表面上には、前記第2の能動素子と絶縁分離してパターン配線が形成されており、
前記パターン配線は、前記第1の能動素子上から前記外部接続電極部上まで延在しており、
前記第1の能動素子は、前記パターン配線を介して前記外部接続電極部と接続されていることを特徴とする請求項1ないし請求項5のいずれかに記載の半導体装置。 - 前記第1の能動素子と前記パターン配線とは、第4のバンプ電極を介して接続されており、
前記パターン配線と前記外部電極とは、第5のバンプ電極を介して接続されていることを特徴とする請求項6に記載の半導体装置。 - 前記第2の能動素子は、前記第1の能動素子を制御するための制御回路を構成することを特徴とする請求項1ないし請求項7のいずれかに記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007003382A JP4318723B2 (ja) | 2007-01-11 | 2007-01-11 | 半導体装置 |
Applications Claiming Priority (1)
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---|---|---|---|
JP2007003382A JP4318723B2 (ja) | 2007-01-11 | 2007-01-11 | 半導体装置 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3955897A Division JP4026882B2 (ja) | 1997-02-24 | 1997-02-24 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007096356A true JP2007096356A (ja) | 2007-04-12 |
JP4318723B2 JP4318723B2 (ja) | 2009-08-26 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2007003382A Expired - Fee Related JP4318723B2 (ja) | 2007-01-11 | 2007-01-11 | 半導体装置 |
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JP (1) | JP4318723B2 (ja) |
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- 2007-01-11 JP JP2007003382A patent/JP4318723B2/ja not_active Expired - Fee Related
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JP4318723B2 (ja) | 2009-08-26 |
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