JP2006121071A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
- Publication number
- JP2006121071A JP2006121071A JP2005295145A JP2005295145A JP2006121071A JP 2006121071 A JP2006121071 A JP 2006121071A JP 2005295145 A JP2005295145 A JP 2005295145A JP 2005295145 A JP2005295145 A JP 2005295145A JP 2006121071 A JP2006121071 A JP 2006121071A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- substrate
- semiconductor device
- chip
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Landscapes
- Bipolar Transistors (AREA)
Abstract
【解決手段】半導体素子を有する第2の半導体基板100を、接着性絶縁膜を介して、能動素子を有する第1の半導体基板60に対向配置し、前記第2の半導体基板に設けられた前記半導体素子の電気的動作に寄与する配線を、前記第1の半導体基板と前記接着性絶縁膜の間に延在して形成することにより、外部電極と接続する金属製のリード端子を不要とする。
【選択図】図19
Description
Claims (5)
- 少なくとも1つの能動素子を有する第1の半導体基板と、
少なくとも1つの半導体素子を有する第2の半導体基板とから成り、
前記第2の半導体基板は、接着性絶縁膜を介して前記第1の半導体基板に対向配置され、
前記第2の半導体基板に設けられた前記半導体素子の電気的動作に寄与する配線が、前記第1の半導体基板と前記第2の半導体基板が重畳する領域において、
前記第1の半導体基板と前記接着性絶縁膜の間に延在して形成されることを特徴とする半導体装置。 - 前記第2の半導体基板の側面には絶縁樹脂が形成されることを特徴とする請求項1記載の半導体装置。
- 前記第1の半導体基板には、前記第1の半導体基板に形成された半導体素子と電気的に接続された電極が設けられ、前記電極が設けられた上層の層に前記配線が設けられる請求項1に記載の半導体装置。
- 第1の半導体チップと、前記第1の半導体チップの上に第2の半導体チップが載置される半導体装置の製造方法であり、
前記第2の半導体チップと一端が電気的に接続され、他端が前記第2の半導体チップの搭載領域の外側に延在される配線が設けられた第1の半導体チップを用意し、
前記第1の半導体チップに設けられた前記配線と電気的に接続されるように、前記第2の半導体チップを設けることを特徴とした半導体装置の製造方法。 - 半導体ICチップと、前記半導体ICチップの上に半導体チップが載置される半導体装置の製造方法であり、
前記半導体チップと一端が電気的に接続され、他端が前記半導体チップの搭載領域の外側に延在される配線が設けられた前記半導体ICチップを用意し、
前記半導体ICチップに設けられた前記配線と電気的に接続されるように、前記半導体チップをフェイスダウンで設け、
前記半導体ICチップと前記半導体チップの間に接着性の樹脂を設けることを特徴とした半導体装置の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005295145A JP2006121071A (ja) | 2005-10-07 | 2005-10-07 | 半導体装置およびその製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005295145A JP2006121071A (ja) | 2005-10-07 | 2005-10-07 | 半導体装置およびその製造方法 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4676697A Division JP4127872B2 (ja) | 1997-02-28 | 1997-02-28 | 半導体装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2006121071A true JP2006121071A (ja) | 2006-05-11 |
Family
ID=36538607
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005295145A Pending JP2006121071A (ja) | 2005-10-07 | 2005-10-07 | 半導体装置およびその製造方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2006121071A (ja) |
-
2005
- 2005-10-07 JP JP2005295145A patent/JP2006121071A/ja active Pending
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100272686B1 (ko) | 반도체장치및그제조방법 | |
JP4026882B2 (ja) | 半導体装置 | |
JP2009516369A (ja) | チップアセンブリ及びそのチップアセンブリの製造方法 | |
US6075279A (en) | Semiconductor device | |
JP2023099739A (ja) | 半導体装置 | |
JP3500015B2 (ja) | 半導体装置及びその製造方法 | |
JP3819483B2 (ja) | 半導体装置 | |
JP4127872B2 (ja) | 半導体装置 | |
JPH1027767A (ja) | 半導体装置の製造方法 | |
JP2007027654A (ja) | 半導体装置 | |
JP3717597B2 (ja) | 半導体装置 | |
JP2006005366A (ja) | 半導体装置 | |
JP3663036B2 (ja) | 半導体装置及びその製造方法 | |
JP4318723B2 (ja) | 半導体装置 | |
JP2006121071A (ja) | 半導体装置およびその製造方法 | |
JP2006024926A (ja) | 半導体装置 | |
JPH1022336A (ja) | 半導体装置の製造方法 | |
JP2006032985A (ja) | 半導体装置および半導体モジュール | |
JP3883612B2 (ja) | 半導体装置 | |
JP3609542B2 (ja) | 半導体装置 | |
JP3639390B2 (ja) | 半導体装置 | |
JP3609540B2 (ja) | 半導体装置 | |
JP4190518B2 (ja) | 半導体装置 | |
JP2004356643A (ja) | 半導体装置 | |
JP3960641B2 (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Effective date: 20080908 Free format text: JAPANESE INTERMEDIATE CODE: A971007 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20080916 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20081113 |
|
A131 | Notification of reasons for refusal |
Effective date: 20090728 Free format text: JAPANESE INTERMEDIATE CODE: A131 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20091201 |