CN102150258B - 堆叠式装置中的信号传递 - Google Patents
堆叠式装置中的信号传递 Download PDFInfo
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- CN102150258B CN102150258B CN200980135828.5A CN200980135828A CN102150258B CN 102150258 B CN102150258 B CN 102150258B CN 200980135828 A CN200980135828 A CN 200980135828A CN 102150258 B CN102150258 B CN 102150258B
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
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- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/53—Means to assemble or disassemble
- Y10T29/5313—Means to assemble electrical device
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/53—Means to assemble or disassemble
- Y10T29/5313—Means to assemble electrical device
- Y10T29/5317—Laminated device
Abstract
一些实施例包括设备、系统及方法,其具有:基底、第一裸片、与所述第一裸片及所述基底布置成堆叠的第二裸片以及位于所述堆叠中且在所述第一裸片及第二裸片中的至少一者外侧并经配置以在所述基底与所述第一裸片及第二裸片中的至少一者之间传送信号的结构。
Description
相关申请案交叉参考
相关申请案此专利申请案主张2008年9月11日申请的第12/209,052号美国申请案的优选权权益,所述美国申请案以引用的方式并入本文中。
背景技术
计算机及其它电子产品(例如,电视、数码相机及蜂窝式电话)通常使用一个或一个以上装置来执行电功能。举例来说,计算机或蜂窝式电话可使用逻辑装置(例如,处理器)来执行逻辑功能且使用存储器装置来存储信息。所述装置可以在其之间传递的电信号的形式彼此通信。随着这些产品中的一些产品中的装置的数目的增加,在这些装置之间传递信号可提出挑战。
附图说明
图1是根据本发明的各种实施例的设备的框图,所述设备包括集成电路封装(IC)。
图2展示根据本发明的各种实施例的IC封装的一些组件的分解图。
图3展示根据本发明的各种实施例的IC封装的部分截面图,所述IC封装具有若干装置及一互连体。
图4展示根据本发明的各种实施例的IC封装的部分截面图,所述IC封装具有若干装置及一互连体,其中所述装置中的一者包括裸片堆叠。
图5展示根据本发明的各种实施例的IC封装的部分截面图,所述IC封装具有若干装置而无互连体。
图6展示根据本发明的各种实施例的IC封装的部分截面图,所述IC封装具有若干装置而无互连体且其中所述装置中的一者包括裸片堆叠。
图7展示根据本发明的各种实施例的IC封装的部分截面图,所述IC封装具有若干装置及用以将信号传送到所述装置中的一者的顶侧的结构。
图8展示根据本发明的各种实施例的IC封装的部分截面图,所述IC封装具有若干装置,其中所述装置中的一者包括裸片堆叠。
图9展示根据本发明的各种实施例的IC封装的部分截面图,所述IC封装具有若干装置及具有多个层的互连体。
图10是展示根据本发明的各种实施例的在IC封装中传送信号的方法的流程图。
图11是展示根据本发明的各种实施例的将包括裸片的组件布置成堆叠的方法的流程图。
图12展示根据本发明的各种实施例的包括IC封装的系统。
具体实施方式
图1是包括根据本发明的各种实施例的IC封装101的设备100的框图。设备100可包括存储器装置、处理器、计算机、电视、数码相机、蜂窝式电话或另一电子装置或系统或者包括于其中。
设备100可包括装置110、120及123,其中一个或一个以上装置(例如,装置110及120)可包括于相同IC封装(例如,IC封装101)内。装置110、120及123中的每一者可包括用以执行例如存储功能(例如,存储器装置的功能)及逻辑功能(例如,处理器的功能)的一个或一个以上功能的电路。IC封装101可包括存储功能及逻辑功能两者以及装置110使得装置110可包括存储器装置且装置120可包括逻辑装置(例如,通用处理器、专用集成电路(ASIC)或微控制器)。
设备100还可包括电力单元114以从例如电池或交流/直流(AC/DC)电源的源接收电力(例如,电力信号Vcc及Vss)。电力单元114可经由线路115向IC封装101及装置123提供电力。
IC封装101可经由线路116与装置123交换信息。因此,传送到封装101及从IC封装101传送的信息可包括线路115上的电力信号及线路116上的例如数据、地址、时钟及控制等的其它信号。
IC封装101可包括以下参考图2到图10所描述的IC封装。
图2展示根据本发明的各种实施例的IC封装200的一些组件的分解图。IC封装200可包括具有单独裸片211、212、213及214的装置210、装置220及基底290。IC封装200还可具有包括互连体230及结构部分241、242、243、244、245及246的结构。IC封装200的例如装置210及220的一些组件可以与图1的IC封装101的装置110及120的框图类似或相同的示意性框图来表示。
IC封装200的组件(包括基底290、装置210及220、互连体230及结构部分241到246)可在其彼此附接后于z维度上布置成堆叠。可使用焊接或其它附接技术将IC封装200的组件彼此附接。
装置210的裸片211、212、213及214中的每一者可包括电路组件位于其中的基于半导体的材料(例如,硅)。裸片211、212、213及214可由硅晶片形成。装置220还可包括装置220的电路组件位于其中的一个或一个以上裸片。装置的一个裸片(或若干裸片)的材料可类似于装置210的裸片的材料。
互连体230及结构部分241到246可包括与裸片211、212、213及214的材料相同或不同的材料。基底290可包括在x维度及y维度上布置成格栅图案的导电元件(例如,焊料球)299,及贯穿基底290以将信息传送到IC封装200及从IC封装200传送信息的导电路径。基底290可包括无机(例如,陶瓷)衬底或有机衬底。有机衬底的实例包括多层双马来酰亚胺三嗪(BT)衬底。图2展示具有球形状的导电元件299作为实例。然而,导电元件299可包括其它形状,例如针形状、矩形形状及其它形状。
IC封装200可使用传送到基底290的导电元件299及从基底的290的导电元件299传送的信号与其它装置通信。如图2中所展示,所述信号可包括:电力信号Vcc及Vss;数据信号D1、D2、D3、D4及D5;地址信号A1、A2及A3;时钟信号CK1及CK2以及控制信号CTL1及CTL2。Vcc信号包括具有正电压值的信号。Vss信号包括具有零电压值或接地电位值的信号。图2用双向箭头使所述信号中的一些信号(例如,D1到D5,及CTL1与CTL2)相关联以指示这些信号可从IC封装200传送或传送到IC封装200。
IC封装200可使用互连体230及结构部分241到246在基底290与装置210及220中的一者或两者之间传送所述信号的至少一个子集。所述信号的一子集包括仅一个信号或所述信号中的信号群组。如本说明书中所描述,所述信号的至少一子集意指所述信号中的仅一个信号、或一些信号、或全部信号。在图2中,所述信号的一子集包括电力信号中的一者或一者以上、数据信号中的一者或一者以上、地址信号中的一者或一者以上、时钟信号中的一者或一者以上、控制信号中的一者或一者以上或者这些信号的组合。所述信号的一子集还可包括仅电力信号中的一者或一者以上、仅数据信号中的一者或一者以上、仅地址信号中的一者或一者以上、仅时钟信号中的一者或一者以上或者仅控制信号中的一者或一者以上。举例来说,IC封装200可使用互连体230及结构部分241到246将仅电力信号(例如,仅Vcc及Vss信号)中的一者或一者以上从基底290传送到装置220。在另一实例中,IC封装200可将所述信号的至少一个子集从基底290传送到装置210且从装置210传送到装置220。在另一实例中,IC封装200可将所述信号(例如,数据信号)的至少一个子集从基底290传送到装置210、从装置210传送到互连体230且接着从所述互连体传送到装置220。
图3展示根据本发明的各种实施例的IC封装300的部分截面图,所述IC封装具有装置310及320以及互连体330。IC封装300还可包括基底390,所述基底具有用以将信息传送到IC封装300及从IC封装300传送信息的导电元件399。IC封装300可使用包括互连体330以及结构部分341、342及343的结构在基底390与/或装置310及320两者之间传送信号。如图3中所展示,基底390、装置310及320以及互连体330在z维度上布置成堆叠且通过导电接头301(例如,焊料、铜或其它材料)彼此附接。IC封装300可包括外壳302及内部303,所述内部可填充有例如基于环氧树脂的模制化合物的绝缘材料。IC封装300的组件(例如装置310及320、互连体330,以及结构部分341、342及343)可包封于外壳302内侧。
基底390可包括与图2的基底290相同或类似的功能及材料。如图3中所展示,基底390可包括导电触点393及394以及延伸穿过基底390且耦合到导电触点393及394的导通孔(有时称作通孔)395。基底390还可包括贯穿其的导电路径396。导电路径396可包括位于导通孔395内侧的导电材料397以在导电触点393与394之间提供电连接。为简单起见,图3展示基底390中的4个导电路径396。然而,基底390可包括与导电路径396类似或相同的众多导电路径。基底390可包括例如电阻器、电感器及电容器的无源组件以执行例如电力信号滤波的功能,从图3中省略这些组件以帮助将焦点集中于本文所描述的实施例上。
装置310可包括与图1的装置110或图2的装置210类似或相同的功能及材料。如图3中所展示,装置310可包括例如裸片311及312的多个裸片,所述裸片在x维度上彼此并排地定位且在垂直于x维度的z维度上定位于相同堆叠层级上。裸片311及312中的每一者可包括位于裸片的相对表面处的导电触点313及314以及延伸穿过所述裸片且耦合到导电触点313及314的导通孔315。裸片311及312中的每一者还可包括贯穿裸片的导电路径316。导电路径316可包括导通孔315内侧的导电材料317。裸片311及312中的每一者还可包括额外导电路径(图3中未展示)以在基底390与装置320之间传送信号。所述额外导电路径可不贯穿延伸穿过裸片的导通孔。装置310可包括存储器装置,其中裸片311及312中的每一者可包括其它组件,例如存储器单元及相关电路,从图3中省略所述其它组件以帮助将焦点集中于本文所描述的实施例上。
如图3中所展示,结构部分341可位于装置310的侧351处、结构部分342可位于装置310的侧352处,且结构部分343可位于装置310的裸片311与312之间。结构部分341、342及343中的每一者可包括位于所述结构部分的相对表面处的导电触点343及344以及延伸穿过所述结构部分且耦合到导电触点343及344的导通孔345。结构部分341、342及343中的每一者还可包括贯穿所述结构部分的导电路径346。导电路径346可包括导通孔345内侧的导电材料347。如图3中所展示,装置310及结构部分341、342及343在z维度上具有相等高度355。为简单起见,图3展示位于结构部分341、342及343中的每一者中的两个导电路径346。然而,结构部分341、342及343中的每一者可包括与导电路径346类似或相同的众多导电路径。
装置320可包括与图1的装置120或图2的装置220类似或相同的功能及材料。在图3中,装置320可包括导电触点323及耦合到导电触点323的导电路径326以提供去往展示为框图的电路328的电连接。电路328可包括经配置以执行与图1的装置120类似或相同的功能(例如,逻辑功能)的组件。
图3中的互连体330包括相对表面331及332、位于表面331处的导电触点333、位于表面332处的导电触点334以及从表面331延伸到表面332且耦合到导电触点333及334的导通孔335。互连体330还可包括贯穿其的导电路径336。导电路径336还可包括导通孔335内侧的导电材料337。互连体330还可包括额外导电路径(图3中未展示)以在基底390与装置320之间或在装置310与装置320之间传送信号。互连体330的额外导电路径可不贯穿从互连体330的表面331延伸到表面332的导通孔。互连体330可在z维度上包括彼此电分离的多个层。所述多个层中的每一者可包括导电材料以传送不同类型的信号。举例来说,互连体330可包括三个层,其中第一层可传送具有正电压值(例如,Vcc)的电力信号、第二层可传送具有接地电位值(例如,Vss)的电力信号,且第三层可传送数据或其它类型的信号。
互连体330具有在边缘356与357之间测量的长度339。长度339可大于裸片311的长度353、大于裸片312的长度354且大于长度353与354的和。如图3中所展示,具有大于装置310的长度的互连体330允许其不仅穿过装置310及结构部分343且还穿过结构部分341及342耦合到基底390。IC封装300中的信号传递结构(包括互连体330及结构部分341、342及343)可改善IC分装300中的信号传递。举例来说,在基底390处所接收的电力信号可更均匀地从基底390分配到装置320。IC封装300可省略包括互连体330及结构部分341、342及343的结构,且将电力信号中的一些或全部电力信号从基底390传送到装置310且接着从装置310传送到装置320。然而,在一些情况下,省略互连体330可降低从基底390至装置320的信号分配(例如,电力信号的分配)的均匀性。
图3展示其中装置310及320、互连体330以及结构部分341、342及343是彼此物理分离的实例。然而,结构部分341及343中的一者或两者可并入到相同裸片(例如,裸片311)中,或者结构部分342及343中的一者或两者可并入到相同裸片(例如,裸片312)中。图3还展示其中装置310包括在x维度上是彼此物理分离的裸片311及312的实例。然而,装置320可在x维度上仅包括单个裸片。在单个裸片的情形下,结构部分341、342及343中的一者或一者以上可并入到单个裸片中或可从IC封装300中省略。举例来说,在单个裸片的情形下,结构部分341可并入到单个裸片中或从IC封装300中省略,且结构部分341及342可保持与单个裸片分离或可并入到单个裸片中。简单地说,互连体330以及结构部分341、342及343中的至少一者可与装置310的一个裸片或若干裸片物理分离,使得互连体330以及结构部分341、342及343中的至少一者可位于装置310、装置320的一个裸片或若干裸片外侧,或者两者仅位于IC封装300的外壳302内侧。
图3展示其中装置310具有在z维度上位于一个堆叠层级上的裸片(例如,裸片311及312)的IC封装300的实例。然而,装置320可包括在z维度上的裸片堆叠。
图4展示根据本发明的各种实施例的IC封装400的部分截面图,所述IC封装具有装置410及420以及互连体430且其中装置410包括裸片堆叠。除图4的装置410以及结构部分堆叠401、402及403外,IC封装400可包括类似于IC封装300的组件的组件。因此,为简单起见,图3与图4之间的类似特征具有相同参考标记且从图4的描述中省略。如图4中所展示,装置410可包括裸片堆叠461及裸片堆叠462,所述堆叠在垂直于z维度的x维度上彼此并排地布置于基底390与第二装置420之间。装置410可包括贯穿裸片堆叠461及裸片堆叠462的导电路径416以将信息传送到裸片堆叠461及裸片堆叠462且从裸片堆叠461及裸片堆叠462传送信息。结构部分401、402及403的堆叠中的每一者可包括如图4中所展示布置成堆叠的多个结构及贯穿所述堆叠以在基底490与互连体430之间提供电连通的导电路径446。如图4中所展示,装置410及结构部分401、402及403的堆叠具有相同高度435。
图5展示根据本发明的各种实施例的IC封装500的部分截面图,所述IC封装具有装置510及520而无互连体。IC封装500可包括类似于图3的IC封装300的组件的组件,但不具有例如图3的互连体430的互连体。为简单起见,图3与图5之间的类似特征具有相同参考标记且从图5的描述中省略。由于IC封装500不具有互连体,因此装置510以及结构部分541、542及543可直接连接到基底590及装置520。装置520具有长度529,裸片511具有裸片511的长度553,且裸片512具有长度554。如图5中所展示,长度529可大于长度553、大于长度554且大于长度553与554的和,使得结构部分541及542可直接耦合到基底590及装置520(耦合于装置510周围)。IC封装500可使用结构部分541、542及542将在基底590的导电元件599处接收的信号的至少一个子集传送到装置520。
图6展示根据本发明的各种实施例的IC封装600的部分截面图,所述IC封装具有装置610及620而无互连体,且其中装置610包括裸片堆叠。除图6的装置610以及结构部分601、602及603外,IC封装600可包括类似于IC封装500的组件的组件。因此,为简单起见,图5与图6之间的类似特征具有相同参考标记且从图6的描述中省略。如图6中所展示,装置610可包括裸片堆叠661及裸片堆叠662,所述堆叠在x维度上彼此并排地布置。装置620可包括贯穿裸片堆叠661及裸片堆叠662的导电路径616以将信息传送到裸片堆叠661及裸片堆叠662且从裸片堆叠661及裸片堆叠662传送信息。结构部分601、602及603的堆叠中的每一者可包括如图6中所展示布置成堆叠的多个结构及贯穿所述堆叠以在基底690与装置620之间提供电连通的导电路径646。如图6中所展示,装置610以及结构部分601、602及603具有相同高度635。
图7展示根据本发明的各种实施例的IC封装700的部分截面图,所述IC封装具有装置710及720以及用以将信号从装置720的顶侧传送到装置720的结构。IC封装700可包括结构部分740、741、742及743,所述结构形成用以将在基底790的导电元件799处接收的信号的至少一个子集传送到装置720的结构。基底790可包括与图2到图6的基底290、390、490、590及690的组件类似或相同的组件。在各种实施例中,可从IC封装700中省略结构部分743。装置710可包括例如导电触点713及714,导通孔715、导电路径716及导电材料717的组件,所述组件与图3的装置310的相应导电触点713及314、导通孔315、导电路径316及导电材料317类似或相同,或者与图5的装置510的导电触点513及514、导通孔515及导电路径516以及导电材料517类似或相同。
在图7中,装置720可包括分别与图2、图3、图4、图5及图6的装置220、320、420、520及620类似或相同的功能。然而,如图7中所展示,装置720可包括位于表面722(在装置720的顶侧处)的导电触点724以从结构部分740接收信号。装置720还可包括位于与表面722相对的表面721处(例如,在装置720的底侧处的表面)的导电触点723以及从表面721延伸到表面722且耦合到导电触点723及724的导通孔725。装置720还可包括贯穿其的导电路径726。导电路径726可包括导通孔725内侧的导电材料727。
结构部分741、742及743可包括例如导电触点743及744、导通孔745、导电路径746以及导电材料747的组件,所述组件与导电触点743及744、导通孔745、导电路径746以及导电材料747类似或相同。结构部分741及742可将信号的至少一部分从基底790传送到结构部分740的导电触点743。结构部分740可包括分配网路747,所述分配网路可包括耦合于导电触点743与748之间的一个或一个以上导电线路层以允许将信号从导电触点743传送到导电触点748,且接着从导电触点748传送到装置720。
结构部分740具有长度749且装置720具有长度729。如图7中所展示,长度749可大于长度729,使得结构部分741及742可直接耦合到基底790及结构部分740(耦合于装置710及720周围)。裸片711具有长度753,且裸片712具有长度754。如图7中所展示,装置720的长度729可大于长度753、大于长度754且大于长度753及754的和,使得结构部分743可直接耦合于基底790与装置720之间(耦合于装置710周围)。
图8展示根据本发明的各种实施例的IC封装800的部分截面图,所述IC封装具有装置810及820,其中装置820包括裸片堆叠。除图8的装置810及结构部分801、802及803的堆叠外,IC封装800可包括类似于IC封装700的组件的组件。因此,为简单起见,图7与图8之间的类似特征具有相同参考标记且从图8的描述中省略。如图8中所展示,装置810可包括裸片堆叠861及裸片堆叠862,所述堆叠在x维度上彼此并排地布置。装置810可包括贯穿裸片堆叠861及裸片堆叠862的导电路径816以将信息传送到裸片堆叠861及裸片堆叠862且从裸片堆叠861及裸片堆叠862传送信息。结构部分801、802及803的堆叠中的每一者还可包括贯穿所述堆叠的导电路径846以在基底890与装置820之间提供电连通。在一些变化形式中,IC封装800可省略堆叠803。
图9展示根据本发明的各种实施例的IC封装900的部分截面图,所述IC封装具有装置910及920以及具有多个层971及972的互连体930。IC封装900可包括类似于图3的IC封装300的组件的一些组件。因此,为简单起见,从图9的描述中省略图3与图9之间的类似特征。举例来说,图9的导电路径926及936可分别类似于图3的导电路径326及336。
在图9中,IC封装900可使用包括互连体930以及结构部分941及942的结构以在基底990与装置910及920中的一者或两者之间传送信号。如图9中所展示,结构部分941可位于装置910的一侧处,且结构部分942可位于装置910的另一侧处。IC封装900可使用结构部分941及942的导电路径946以将电力信号从基底990传送到互连体930。基底990可包括用以将电力信号传送到装置910及920的导电路径996及将例如数据及其它信息的信号传送到装置910及920且从装置910及920传送例如数据及其它信息的信号的导电路径998。
装置920可包括与图1的装置120、图2的装置220及图3的装置300类似或相同的功能及材料。举例来说,装置920可包括电路928,所述电路可包括经配置以执行与图1的装置120类似或相同的功能(例如,逻辑功能)的组件。
装置910可包括与图1的装置110或图2的装置210类似或相同的功能及材料。图9的装置910可包括耦合到基底990的导电路径996以接收电力信号的导电路径916及耦合到基底990的导电路径998以传送例如数据、地址及/或控制信号的其它信号的导电路径918。导电路径916及918中的每一者可包括导通孔915内侧的导电材料917。
装置910可包括耦合到基底990的导电路径998中的一者的导电路径912以传送例如数据信号的信号。导电路径912可包括导通孔913及914以及电路961的至少一部分。如图9中所展示,导通孔913及914中的每一者可仅部分地延伸穿过装置910的裸片911。电路961可处理或操纵在导电路径912上传送的信号。
装置910还可包括耦合到基底990的导电路径998中的一者的导电路径953以传送例如数据信号的信号。导电路径953可包括导通孔954及955、导电段956及电路962的至少一部分。如图9中所展示,导通孔954及955中的每一者可仅部分地延伸穿过装置910的裸片911。导电段956可沿x维度且垂直于导通孔954及955横向延伸。电路962可处理或操纵在导电路径953上传送的信号。
图9展示IC封装900作为实例,其中装置910仅具有位于基底990与装置920之间的一个裸片911。然而,装置910可包括类似于图3的装置310的裸片的在x维度上布置的多个裸片。装置910还可包括类似于图4的装置410的裸片的在z维度上布置的多个裸片。图9展示IC900的组件中的某一数目的导电路径作为实例。IC900中的导电路径的数目可变化。
图9中的互连体930可包括用以传送不同信号的不同导电路径936、998及399。举例来说,导电路径936可将具有正电压值(例如,Vcc)的电力信号传送到装置920且导电路径939可将具有接地电位值(例如,Vss)的电力信号传送到装置920。导电路径938可在装置910与920之间传送数据或其它类型的信号。在图9中,导电路径938与导电部分988及989物理及电分离。导通孔986及导电路径936的导电部分987连接在一起。导通孔989及导电路径939的导电部分988连接在一起但与导通孔986及导电路径936的导电部分987物理及电分离。
如图9中所展示,互连体930的导电路径936及939中的一些导电路径可不贯穿从互连体930的表面951延伸到表面952的导通孔。举例来说,导电路径936中的一些导电路径可部分地贯穿导通孔986中的互连体930且耦合到导电部分987。导通孔986可从表面951到导电部分987仅部分地延伸穿过互连体930,导电部分987在互连体930的层971中在x维度上横向延伸。在另一实例中,导电路径939中的一些导电路径可部分地贯穿导通孔989中的互连体930且耦合到导电部分988。导通孔989可从表面952到导电部分988仅部分地延伸穿过互连体930,导电部分988在互连体930的层972中在x维度上横向延伸。
在上文参考图1到图9所描述的设备中,不同导通孔可具有不同大小(例如在x维度上截取的不同截面)以传送不同类型的信号。举例来说,传送电力信号的导通孔可具有比传送数据信号的导通孔大的大小。
图10是展示根据本发明的各种实施例的在IC封装中传送信号的方法1000的流程图。方法1000可在与上文参考图1到图9所描述的设备100以及IC封装101、200、300、400、500、600、700、800及900类似或相同的设备及IC封装中使用。因此,方法1000中使用的设备及装置的组件可包括上文参考图1到图9所描述的设备100以及IC封装101、200、300、400、500、600、700、800及900的组件。
方法1000的活动1010可包括在IC封装的基底处接收信号。所述IC封装可包括第一装置以及与第一装置及基底一起布置成堆叠的第二装置。第一装置可包括穿过其的至少一个导电路径。活动1020可包括使用堆叠中的结构的导电路径将所述信号的至少一个子集从基底传送到第二装置。所述结构的至少一部分可位于第一装置及第二装置的外侧。所述结构的导电路径的至少一部分贯穿所述结构的导通孔。所述信号的子集可包括电力信号、数据信号、地址信号、时钟信号或控制信号或者这些信号的组合。另一选择为,所述信号的子集可仅包括电力信号,例如,仅Vcc及Vss信号。方法1000可包括与上文参考图1到图9所描述的传送信号的活动类似或相同的其它活动。
图11是展示根据本发明的各种实施例的将包括裸片的组件布置成堆叠的方法1100的流程图。方法1100可用于布置与上文参考图1到图9所描述的设备100以及IC封装101、200、300、400、500、600、700、800及900类似或相同的设备及IC封装的组件。因此,在方法1100中使用的设备及装置的组件可包括上文参考图1到图9所描述的设备110以及IC封装101、200、300、400、500、600、700、800及900的组件。
方法1100的活动1110可包括将第一装置与第二装置布置成堆叠。所述第一装置可包括穿过第一装置的至少一个导电路径。活动1120可包括将结构布置于所述堆叠中以在基底与第一裸片及第二裸片中的至少一者之间传送信号的至少一个子集。所述结构可包括用以传送所述信号的导电路径且所述导电路径的至少一部分可贯穿所述结构的导通孔。方法1100可以与布置上文参考图1到图9所描述的设备110以及IC封装101、200、300、400、500、600、700、800及900的组件类似或相同的方式布置其它组件。
图12展示根据本发明的各种实施例的系统1200。系统1200可包括具有存储器装置1210及处理器1220的IC封装1201、存储器装置1224、图像传感器装置1226、存储器控制器1230、图形控制器1240、输入及输出(I/O)控制器1250、显示器1252、键盘1254、指向装置1256、外围装置1258、收发器1259或电力单元1260或其组合。系统1200还可包括总线1261以在系统1200的组件之间传送信息且向这些组件中的至少一些组件提供电力。系统1200可进一步包括其中可附接系统的组件中的一些组件的电路板1202及用以将信息以无线方式发射到系统1200且从系统1200以无线方式接收信息的天线1270。收发器1259可操作以在天线1270与系统1200的组件中的一者或一者以上(例如,IC封装1201及存储器装置1224中的至少一者)之间传送信息。
图像传感器装置1220可包括具有CMOS像素阵列的互补金属氧化物半导体(CMOS)图像传感器或具有CCD像素阵列的电荷耦合装置(CCD)图像传感器。
显示器1252可包括模拟显示器或数字显示器。显示器1252可从其它组件接收信息。举例来说,显示器1252可接收由IC封装1201、存储器装置1224、图像传感器装置1226及图形控制器1240中的一者或一者以上处理的信息以展示例如文本或图像的信息。
处理器1220可包括通用处理器或ASIC。处理器1220可包括单核心处理器或多核心处理器。处理器1220可执行一个或一个以上编程命令以处理信息。所述信息可包括由系统1200、存储器装置1210或图像传感器装置1226的其它组件提供的信息。
处理器1220可包括本文所描述的各种装置(例如上文参考图1到图9所描述的装置120、220、320、420、520、620、720、820或920)中的一者或一者以上的实施例。
存储器装置1210及1224中的每一者可包括易失性存储器装置、非易失性存储器装置或两者的组合。举例来说,存储器装置1220及1224中的每一者可包括动态随机存取存储器(DRAM)装置、静态随机存取存储器(SRAM)装置、快闪存储器装置、相变存储器装置或这些存储器装置的组合。
存储器装置1210可包括本文所描述的各种装置(例如上文参考图1到图9所描述的装置110、210、310、410、510、610、710、810、或910)中的一者或一者以上的实施例。图12展示彼此物理分离的存储器装置1220及1224。然而,存储器装置1220及1224可为单个存储器装置,其可包括于IC封装1201中。
设备(例如,设备100以及IC封装101、200、300、400、500、600、700、800及900)及系统(例如,系统1200)的图解说明打算提供对各种实施例的结构的一般理解且不打算提供对可使用本文所描述的结构的设备及系统的所有组件及特征的完整描述。
上文所描述的任何组件可以若干方式(包括经由软件的模拟)来实施。因此,本文可将上文所描述的设备(例如,设备100以及IC封装101、200、300、400、500、600、700、800及900)以及系统(例如,系统1200)全部表征为“模块(或若干模块)”。如设备(例如,设备100以及IC封装101、200、300、400、500、600、700、800及900)及系统(例如,系统1200)的设计师所期望且如适合于各种实施例的特定实施方案,此些模块可包括硬件电路、单处理器及/或多处理器电路、存储器电路、软件程序模块以及对象及/或固件及其组合。举例来说,此等模块可包括于系统操作模拟封装中,例如软件电信号模拟封装、电力使用及分配模拟封装、电容/电感模拟封装、电力/热量耗散模拟封装、信号发射/接收模拟封装及/或用于操作或模拟各种潜在实施例的软件与硬件的组合。
各种实施例的设备及系统可包括或包括于在高速计算机中使用的电子电路、通信及信号处理电路、单处理器模块或多处理器模块、单嵌入式处理器或多嵌入式处理器、多核处理器、数据开关以及包括多层、多芯片模块的专用模块中。此等设备及系统可进一步包括各种电子系统内的子组件,例如电视、蜂窝式电话、个人计算机(例如,膝上型计算机、桌上型计算机、手持式计算机、平板计算机等等)、工作站、无线电、视频播放器、音频播放器(例如,MP3(动画专家组,音频层3)播放器)、交通工具、医学装置(例如,心脏监视器、血压监视器等等)、机顶盒及其它。
本文所描述的一个或一个以上实施例包括设备、系统及方法,其具有:基底、第一裸片、与第一裸片及基底布置成堆叠的第二裸片以及位于所述堆叠中且在第一裸片及第二裸片中的至少一者外侧并经配置以在基底与第一裸片及第二裸片中的至少一者之间传送信号的结构。上文参考图1到图11描述包括额外设备及方法的其它实施例。
以上描述及图式图解说明本发明的一些实施例以使得所属领域的技术人员能够实践本发明的实施例。其它实施例可并入有结构、逻辑、电、过程及其它改变。在图式中,遍及数个视图以相同特征或相同编号描述大致类似的特征。实例仅代表可能的变化形式。一些实施例的部分及特征可包括于其它实施例的部分及特征中或替代其它实施例的部分及特征。在阅读并理解上文说明后,所属领域的技术人员将即刻明了许多其它实施例。
本文提供发明摘要以遵循37C.F.R.§1.72(b),其需要将允许读者快速查明技术揭示内容的本质及要旨的摘要。提交本摘要应理解为其将不用于解释或限定权利要求书。
Claims (43)
1.一种堆叠式装置中的信号传递设备,其包含:
基底(390/490),其经配置以接收信号;
第一裸片(311/410),其包括至少部分地穿过所述第一裸片的导电路径;
第二裸片(320/420),其与所述第一裸片及所述基底布置成堆叠;及
结构(330/430,341,342,343),其位于所述堆叠中且在所述第一裸片及所述第二裸片中的至少一者外侧并经配置以在所述基底与所述第一裸片及所述第二裸片中的至少一者之间传送所述信号的至少一个子集,所述结构包括位于所述第一裸片的第一侧处的第一结构部分(341/401)及位于所述第一裸片的第二侧处的第二结构部分(342/402),所述第一结构部分和所述第二结构部分的每一者包括第一表面、与所述第一表面相对的第二表面、位于所述第一表面处且耦合至所述基底的第一导电触点、位于所述第二表面处且耦合至所述第二裸片的第二导电触点以及将所述第一导电触点耦合至所述第二导电触点的导电路径。
2.根据权利要求1所述的堆叠式装置中的信号传递设备,其中所述第一裸片位于所述基底与所述第二裸片之间,所述第一结构部分位于所述基底与所述第二裸片之间,所述第二结构部分位于所述基底与所述第二裸片之间。
3.根据权利要求1所述的堆叠式装置中的信号传递设备,其中所述结构包括位于所述第一裸片与所述第二裸片之间的互连体(330/430),所述互连体包括耦合到所述第一裸片及所述第二裸片的导电路径。
4.根据权利要求1所述的堆叠式装置中的信号传递设备,其中所述结构包括具有耦合到所述第二裸片的导电路径的一部分,且所述第一裸片及所述第二裸片位于所述基底与所述部分之间。
5.根据权利要求1所述的堆叠式装置中的信号传递设备,其中所述基底包括具有有机材料及穿过所述有机材料的导电路径的衬底。
6.根据权利要求1所述的堆叠式装置中的信号传递设备,其中所述基底包括用以执行信号滤波的电路组件。
7.一种堆叠式装置中的信号传递设备,其包含:
基底(390/490),其经配置以接收信号;及
第一装置(310/410),其包括至少部分地穿过所述第一装置的第一导电路径;
第二装置(320/420);
互连体(330/430),其与所述基底、所述第一装置及所述第二装置布置成堆叠,所述互连体位于所述第一装置与第二装置之间且经配置以将所述信号的至少一个子集传送到所述第一装置及第二装置中的一者,所述互连体包括第一表面、与所述第一表面相对的第二表面、位于所述第一表面处且耦合到所述第一装置的第一导电触点、位于所述第二表面处且耦合到所述第二装置的第二导电触点及将所述第一导电触点耦合到所述第二导电触点的第二导电路径;及
位于所述第一装置的第一侧处的第一结构部分(341/401)及位于所述第一装置的第二侧处的第二结构部分(342/402),所述第一结构部分和所述第二结构部分的每一者包括第一表面、与所述第一表面相对的第二表面、位于所述第一表面处且耦合至所述基底的第一导电触点、位于所述第二表面处且耦合至所述互连体的第二导电触点以及将所述第一导电触点耦合至所述第二导电触点的导电路径。
8.根据权利要求7所述的堆叠式装置中的信号传递设备,其中所述第一结构的导电路径耦合到所述基底及所述互连体,且所述第二结构的导电路径耦合到所述基底及所述互连体。
9.根据权利要求8所述的堆叠式装置中的信号传递设备,其中所述第一装置包括彼此并排地布置的第一裸片堆叠及第二裸片堆叠。
10.根据权利要求9所述的堆叠式装置中的信号传递设备,其进一步包含位于所述第一裸片堆叠与所述第二裸片堆叠之间的第三结构部分(343/403),所述第三结构部分包括耦合到所述基底及所述互连体的导电路径。
11.根据权利要求10所述的堆叠式装置中的信号传递设备,其中所述第一结构部分、第二结构部分及第三结构部分中的至少一者并入到所述第一裸片堆叠及第二裸片堆叠中的至少一者的裸片。
12.根据权利要求7所述的堆叠式装置中的信号传递设备,其中所述互连体包括在所述互连体的边缘之间测量的长度,所述互连体的所述长度大于所述第一装置的长度。
13.根据权利要求7所述的堆叠式装置中的信号传递设备,其中所述互连体包括从所述第一表面延伸到所述第二表面的导通孔,所述第二导电路径中的一者的至少一部分穿过所述导通孔。
14.根据权利要求7所述的堆叠式装置中的信号传递设备,其中所述互连体包括多个层,所述多个层中的每一者包括耦合到第二导电路径中的至少一者的至少一个导电部分以传送所述信号的不同子集。
15.根据权利要求7所述的堆叠式装置中的信号传递设备,其中所述互连体包括耦合到所述第二导电路径的第一选定导电路径的第一导电部分以传送具有正值的第一电力信号,及耦合到所述第二导电路径的第二选定导电路径的第二导电部分以传送具有接地电位的第二电力信号,所述第一导电部分及第二导电部分中的至少一者在垂直于所述第一选定导电路径及第二选定导电路径的维度上延伸。
16.根据权利要求15所述的堆叠式装置中的信号传递设备,其中所述第一选定导电路径贯穿仅部分地延伸穿过所述互连体的导通孔。
17.根据权利要求16所述的堆叠式装置中的信号传递设备,其中所述第二选定导电路径贯穿仅部分地延伸穿过所述互连体的额外导通孔。
18.根据权利要求17所述的堆叠式装置中的信号传递设备,其中所述第一装置包括耦合到所述第一导电路径的选定导电路径的导电段以传送数据信号,所述导电段在垂直于所述选定导电路径的维度上延伸。
19.一种堆叠式装置中的信号传递设备,其包含:
基底(390/490),其经配置以接收信号;及
第一装置(310/410),其包括至少部分地穿过所述第一装置的第一导电路径;
第二装置(320/420),其与所述基底及所述第一装置布置成堆叠,所述第一装置位于所述基底与所述第二装置之间,所述第一装置具有比所述第二装置的长度小的长度;及
结构(330/340,341,342,343),其经配置以将所述信号的至少一个子集传送到所述第二装置,所述结构包括位于所述第一装置的第一侧处的第一结构部分(341/401)及位于所述第一装置的第二侧处的第二结构部分(342/402),所述第一结构部分及第二结构部分中的每一者包括第一表面、与所述第一表面相对的第二表面、位于所述第一表面处且耦合到所述基底的第一导电触点、位于所述第二表面处且耦合到所述第二装置的第二导电触点及将所述第一导电触点耦合到所述第二导电触点的第二导电路径。
20.根据权利要求19所述的堆叠式装置中的信号传递设备,其中所述第一结构部分包括从第一结构部分的所述第一表面延伸到所述第二表面的第一导通孔,所述第二导电路径中的一者的至少一部分穿过所述第一导通孔,且所述第二结构部分包括从所述第二结构部分的所述第一表面延伸到所述第二表面的第二导通孔,所述第二导电路径中的一者的至少一部分穿过所述第二导通孔。
21.根据权利要求19所述的堆叠式装置中的信号传递设备,其中所述结构的高度等于所述第一装置的高度。
22.根据权利要求19所述的堆叠式装置中的信号传递设备,其中所述第一装置包括彼此并排地布置的第一裸片堆叠及第二裸片堆叠。
23.根据权利要求22所述的堆叠式装置中的信号传递设备,其中所述结构进一步包括位于所述第一裸片堆叠与所述第二裸片堆叠之间的第三结构部分,第三结构部分包括耦合到所述基底及所述第二装置的导电路径。
24.一种堆叠式装置中的信号传递设备,其包含:
基底(790),其经配置以接收信号;及
第一装置(710),其包括至少部分地穿过所述第一装置的导电路径;
第二装置(720),其包括第一表面、与所述第一表面相对的第二表面、位于所述第一表面处且耦合到所述第一装置的第一导电触点及位于所述第二表面处的第二导电触点;及
结构(740,741,742,743),其包括经配置以将所述信号的至少一个子集传送到所述第二装置的导电路径,所述结构包括与所述基底、所述第一装置及所述第二装置布置成堆叠的第一结构部分(740),所述第一装置及第二装置在所述基底与所述第一结构部分之间,所述结构包括位于所述第一装置的第一侧处的第二结构部分(741)及位于所述第一装置的第二侧处的第三结构部分(742),所述第二结构部分及所述第三结构部分的每一者包括第一表面、与所述第一表面相对的第二表面、位于所述第一表面处且耦合到所述基底的第一导电触点、位于所述第二表面处的第二导电触点及将所述第一导电触点耦合到所述第二导电触点的导电路径。
25.根据权利要求24所述的堆叠式装置中的信号传递设备,其中所述第二结构部分的导电路径耦合到所述基底及所述第一结构部分,且所述第三结构部分的导电路径耦合到所述基底及所述第一结构部分。
26.根据权利要求25所述的堆叠式装置中的信号传递设备,其中所述第二结构部分及第三结构部分中的每一者的所述第二导电触点耦合至所述第一结构部分。
27.根据权利要求25所述的堆叠式装置中的信号传递设备,其中所述第一装置包括彼此并排地布置的第一裸片堆叠及第二裸片堆叠。
28.根据权利要求27所述的堆叠式装置中的信号传递设备,其进一步包含位于所述第一裸片堆叠与所述第二裸片堆叠之间的第四结构部分(743),第四结构部分包括耦合到所述基底及所述第二装置的导电路径。
29.根据权利要求24所述的堆叠式装置中的信号传递设备,其中所述第一结构部分具有比所述第二装置的长度大的长度。
30.一种堆叠式装置中的信号传递系统,其包含:
处理器;
存储器装置,其与所述处理器一起被包封于集成电路封装中且包括裸片,所述裸片具有至少部分地穿过所述裸片的导电路径;
基底(390/490),其与所述存储器装置及所述处理器布置成堆叠且经配置以接收信号;
结构(330/340,341,342,343),其位于所述堆叠中且在所述处理器及所述存储器装置中的至少一者外侧并经配置以在所述基底与所述处理器及所述存储器装置中的至少一者之间传送所述信号的至少一个子集,所述结构包括位于所述存储器装置的第一侧处的第一结构部分(341/401)及位于所述存储器装置的第二侧处的第二结构部分(342/402),所述第一结构部分及所述第二结构部分的每一者包括第一表面、与所述第一表面相对的第二表面、位于所述第一表面处且耦合到所述基底的第一导电触点、位于所述第二表面处且耦合到所述处理器的第二导电触点及将所述第一导电触点耦合到所述第二导电触点的导电路径。
31.根据权利要求30所述的堆叠式装置中的信号传递系统,其中所述存储器装置包括裸片堆叠。
32.根据权利要求30所述的堆叠式装置中的信号传递系统,其中所述集成电路封装耦合到天线。
33.一种堆叠式装置中的信号传递方法,其包含:
在集成电路封装的基底处接收信号,所述集成电路封装包括第一装置及第二装置,所述第二装置与所述第一装置及所述基底布置成堆叠,所述第一装置包括至少部分地穿过所述第一装置的至少一个导电路径;及
使用在所述堆叠内侧且在所述第一装置及所述第二装置中的至少一者外侧的结构的导电路径将所述信号的至少一个子集从所述基底传送到所述第二装置,所述结构的所述导电路径的至少一部分贯穿所述结构的导通孔,所述结构包括位于所述第一装置的第一侧处的第一结构部分(341/401)及位于所述第一装置的第二侧处的第二结构部分(342/402),所述第一结构部分及所述第二结构部分的每一者包括第一表面、与所述第一表面相对的第二表面、位于所述第一表面处且耦合到所述基底的第一导电触点、位于所述第二表面处且耦合到所述第二装置的第二导电触点及将所述第一导电触点耦合到所述第二导电触点的导电路径。
34.根据权利要求33所述的堆叠式装置中的信号传递方法,其中传送所述信号的至少一个子集包括将所述信号中的至少一个数据信号从所述基底传送到所述第二装置且将所述信号中的至少一个电力信号从所述基底传送到所述第二装置。
35.根据权利要求33所述的堆叠式装置中的信号传递方法,其中传送所述信号的至少一个子集包括仅将电力信号从所述基底传送到所述第二装置。
36.根据权利要求33所述的堆叠式装置中的信号传递方法,其进一步包含:
将所述信号的额外子集从所述基底传送到所述第一装置;及
将所述信号的所述额外子集从所述第一装置传送到所述第二装置。
37.根据权利要求36所述的方法,其中所述信号的所述额外子集将电力信号排除在外。
38.根据权利要求36所述的堆叠式装置中的信号传递方法,其中将所述信号的所述额外子集从所述第一装置传送到所述第二装置包括将所述信号的所述额外子集从所述第一装置传送到所述结构的一部分及将所述信号的所述额外子集从所述结构的所述部分传送到所述第二装置。
39.根据权利要求36所述的堆叠式装置中的信号传递方法,其中将所述信号的所述额外子集从所述第一装置传送到所述第二装置包括穿过所述第一装置的至少一个裸片堆叠的至少一个导通孔传送所述信号的所述额外子集。
40.一种堆叠式装置中的信号传递方法,其包含:
将第一装置与第二装置布置成堆叠,所述第一装置包括至少部分地穿过所述第一装置的至少一个导电路径;及
将结构(330/340,341,342,343,740,741,742,743)布置于所述堆叠中以在基底与所述第一装置及第二装置中的至少一者之间传送信号的至少一个子集,所述结构包括用以传送所述信号的导电路径,所述导电路径的至少一部分贯穿所述结构的导通孔,其中布置所述结构包括在所述第一装置的第一侧处布置第一结构部分(341/401/741)以及在所述第一装置的第二侧处布置第二结构部分(342/402/742),所述第一结构部分及所述第二结构部分的每一者包括第一表面、与所述第一表面相对的第二表面、位于所述第一表面处且耦合到所述基底的第一导电触点、位于所述第二表面处且耦合到所述第二装置的第二导电触点及将所述第一导电触点耦合到所述第二导电触点的导电路径。
41.根据权利要求40所述的堆叠式装置中的信号传递方法,其中布置所述结构包括将所述结构的第三部分(330/430)置于所述第一装置与第二装置之间。
42.根据权利要求40所述的堆叠式装置中的信号传递方法,其中将所述结构的第三部分置于所述第一装置与第二装置之间包括将所述第三部分的导电路径耦合至所述第一装置与所述第二装置。
43.根据权利要求40所述的堆叠式装置中的信号传递方法,其中布置所述结构包括将所述第一装置及第二装置置于所述结构的一部分(740)与所述基底之间。
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