CN102097460A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN102097460A
CN102097460A CN201010556614.XA CN201010556614A CN102097460A CN 102097460 A CN102097460 A CN 102097460A CN 201010556614 A CN201010556614 A CN 201010556614A CN 102097460 A CN102097460 A CN 102097460A
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CN102097460B (zh
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李宗霖
余绍铭
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明公开了一种半导体装置及其制造方法，其中一实施例提供一种含至少三个有源区的半导体装置。此至少三个有源区彼此相邻。此至少三个有源区的纵轴相互平行且每一有源区包含一边缘与所对应区域的纵轴相交。此至少三个有源区的边缘形成一弧形。本发明可减少图案中围绕有源区的浅沟槽隔离区所导致的应力。

Description

半导体装置及其制造方法
技术领域
本发明涉及一种半导体装置及其制造方法，且特别是涉及一种具有不规则有源区的半导体装置及其制造方法。
背景技术
一般而言，半导体基材单位面积中的晶体管有源区皆具有相同长度，以使此单位面积中所含的有源区为矩形，且每一有源区的长度即为矩形的长度。然而，图案化可能会在每一有源区中导致较高的角隅应力，且在每一有源区中及有源区旁的浅沟槽隔离(STI)中导致较高的应力。例如，浅沟槽隔离中的氧化物可在浅沟槽隔离中导致拉伸应力，及在有源区中导致压缩应力。再者，图案化通常使工艺更为困难(特别是蚀刻)，其可能是因为邻近的有源区之间有时具有不同的间距，造成不同的负载效应(loading effects)及化学反应，使有源区的尺寸或排列难以保持规则。
上述问题随晶体管尺寸微缩更显严重。此外，这些问题可能同时存在于平面场效应晶体管及鳍式场效应晶体管中，但在鳍式场效应晶体管中也较为严重。因此，业界所需的是一种解决上述问题及缺点的方法。
发明内容
为克服现有技术的缺陷，本发明提供一种半导体装置，包括：至少三个有源区，其中此至少三个有源区彼此紧邻，其中此至少三个有源区的纵轴相互平行，其中每一有源区各自包含一边缘与此有源区的纵轴相交(intersecting)，且此至少三个有源区的边缘形成一弧形。
本发明也提供一种半导体装置的制造方法，包含：提供一半导体基材；形成一光致抗蚀剂层于此半导体基材上；图案化此半导体基材上的此光致抗蚀剂层，以使用一光掩模来暴露出此半导体基材的一暴露部分，其中此光掩模包含一含曲线边缘的透明区域，且其中此曲线边缘定义此半导体基材的此暴露区域的一边缘；以及蚀刻此半导体基材的此暴露部分，以使此半导体基材的此暴露部分的此边缘定义有源区的边缘，其中每一有源区包含一与所对应的边缘相交的纵长。
本发明还提供一种半导体装置的制造方法，包含：提供一半导体基材；在此半导体基材上形成多个鳍；以及
图案化此些鳍以使每一鳍皆包含一边缘，且此些鳍的此些边缘形成一弧形。
本发明可减少图案中围绕有源区的浅沟槽隔离区所导致的应力。
为让本发明的上述和其他目的、特征、和优点能更明显易懂，下文特举出较佳实施例，并配合附图，作详细说明如下。
附图说明
图1A显示依照本发明一实施例的含晶体管有源区的半导体基材区的布局。
图1B显示依照本发明又一实施例的具有另一种边缘的有源区，其为图1A中的布局的一部分。
图2显示依照本发明一实施例的含具有有源区的鳍式场效应晶体管的半导体基材的立体图。
图3显示依照本发明另一实施例的含具有有源区的鳍式场效应晶体管的半导体基材的布局。
图4显示依照本发明另一实施例的含具有有源区的鳍式场效应晶体管的半导体基材的立体图。
图5A显示依照本发明一实施例的半导体基材的立体图。
图5B显示依照图5A所示的实施例中的半导体基材的剖面图。
图6A显示依照本发明一实施例的蚀刻工艺后的用于鳍式场效应晶体管的半导体基材。
图6B显示依照图6A所示实施例的半导体基材的剖面图。
图7A显示依照本发明一实施例的在沉积介电层后的半导体基材。
图7B显示依照图7A所示实施例的半导体基材的剖面图。
图8显示依照本发明一实施例的具有鳍及保护掩模的半导体基材的俯视图。
图9显示依照图8所示实施例的经蚀刻工艺后的基材的立体图。
图10显示依照本发明一实施例的具有鳍及切割掩模的半导体基材的俯视图。
图11显示依照图10所示实施例的经蚀刻工艺的基材的立体图。
图12显示依照图9或图11所示实施例的完成鳍式场效应晶体管制造的基材的剖面图。
【主要附图标记说明】
2、4、6、8、10、12、14、16、18、20、20’～有源区
22、24、26、28、30、32、34、36、38、40～有源区
50～半导体基材
52、54、56、58、60～有源区
62、64～栅极电极
66、68、70、72、74、76、78、80～鳍式场效应晶体管
82～隔离区
84、86、88～凸状弧形
150～半导体基材
152、154、156、158、160～有源区
162、164～栅极电极
166、168、170、172、174、176、178、180～鳍式场效应晶体管
182～隔离区
184、186、188～凹状弧形
200～半导体基材
202、204、206、208、210～鳍
202’、204’、206’、208’、210’～鳍
202”、204”、206”、208”、210”～鳍
212、214、216～暗区
218～介电层
220～栅极介电层
222～栅极电极
具体实施方式
本发明接下来将详加讨论各种的实施例的制造及使用。值得注意的是，本发明所提供的这些实施例仅提供本发明的发明概念，且其可以宽广的形式应用于各种特定情况下。在此所讨论的实施例仅用于举例说明，并非以各种形式限制本发明。
在以下所描述的实施例，可称为用于鳍式场效应晶体管(FinFET)的有源区的不规则图案。其他实施例也可包含对于其他晶体管的应用，例如平面场效应晶体管，或用于不同的设计目的，例如增进性能或可靠度。
图1A显示为依照本发明实施例的含晶体管有源区的半导体基材区的布局。此布局包含有源区2至20的图案。图案为非规则性的，在此图案中，有源区群组的边缘顺应(conform to)于凸状弧形(convex arc)的形状(相对于群组的中央)。值得注意的是，凸状弧形的半径可延伸至图案中的一点，或延伸至图案外的一点。上述的顺应于弧形的边缘为有源区的边缘及/或表面，其与有源区的纵轴相交(intersect)。此纵轴为一直线，沿着有源区的通道宽度方向延伸，或者，在本发明附图中，为沿着X轴延伸。单一有源区的一边缘可实质上顺应于弧形，但其也可经过圆化(rounded)以使各个独立的边缘实质上未顺应于弧形，特别是在考虑到工艺容忍度的时候。这两种情况显示于图1B。图1B显示一实施例为如图1A所示的有源区20的边缘，具有实质上顺应于弧形的边缘，及另一实施例为如有源区20’的圆化边缘。上述每一实施例皆可视为在本发明的范围中。
图2显示为依照本发明实施例的半导体基材50的相似区域的立体图，此区域内包含具有有源区的鳍式场效应晶体管。此结构包含有源区，或形成鳍式场效应晶体管66至80的鳍52至60及栅极电极62、64。此结构还包含围绕有源区52至60的隔离区82。在此，省略其他元件以作简化，例如介电层，特别是栅极介电层。与图1A类似，有源区具有不规则的边缘。如图2所示，鳍式场效应晶体管66至74的有源区52至60的右侧边缘顺应于凸状弧形84。再者，有源区52及54的左侧边缘顺应于凸状弧形86。同样地，鳍式场效应晶体管76、78及80的有源区56至60的左侧边缘顺应于凸状弧形88。
由图1A、图1B及图2所示的实施例，可了解到相较于传统含规则图案的有源区的优点。在所示的实施例中，靠近不规则图案的边缘的有源区可具有较小的尺寸。相对于位于图案中央的有源区，以此方式缩减有源区的边界尺寸可减少此图案中围绕有源区的浅沟槽隔离区所导致的应力。缩减有源区的边界尺寸可使浅沟槽隔离区变得较大，而可使浅沟槽隔离区中的拉伸应力获得缓解，因而可防止浅沟槽隔离区崩溃及防止漏电流。
图3显示依照本发明其他实施例的含晶体管有源区的半导体基材区的布局，此基材区中包含有源区22至40。图案为非规则性的，在此图案中，有源区群组的边缘顺应于凹状弧形的形状(相对于群组的中央)。与图1B类似，由于工艺上的考量，有源区的各个独立边缘可由每一边缘未实质上顺应于弧形的方式形成。
图4显示依照本发明实施例的含具有有源区的鳍式场效应晶体管的半导体基材150的相似区域的立体图。此结构包含有源区，或形成鳍式场效应晶体管166至180的鳍152至160及栅极电极162及164。此结构还包含围绕有源区166至180的隔离区182。与图3相似，有源区具有不规则的边缘。如图4所示，鳍式场效应晶体管166至174的有源区152至160的边缘顺应于凹状弧形(concave arc)184。再者，有源区152及154的边缘顺应于凹状弧形186。同样地，鳍式场效应晶体管176、178及180的有源区156至160的边缘顺应于凹状弧形188。
由图3及图4所示的实施例，可了解到相较于传统含规则图案的有源区的优点。在这些实施例中，靠近非规则图案的边缘的有源区可具有较大的尺寸。增大边界有源区的尺寸可使接触点增大，而可减少有源区的接触电阻，即因此，可减少装置的总体电阻。再者，通过缩减尺寸，可具有较佳的源/漏极外延轮廓，而可通过增加有源区的接触区域及减少有源区的缺陷来减少接触及总体电阻。因此，可利于减少集成电路中发生的信号延迟(RC timedelay)。
图5A至图12显示依照本发明实施例的工艺，以了解上述结构。图5A显示一半导体基材200，例如硅、锗化硅或其类似物。图5B显示半导体基材200沿着图5A所示线段A-A的剖面图。图6A显示为经过蚀刻工艺后的半导体基材200，以形成鳍式场效应晶体管的鳍202、204、206、208及210。图6B显示半导体基材200沿着图6A所示线段A-A的剖面图。图7A显示以例如沉积及化学机械研磨(CMP)形成介电层218形成于鳍202、204、206、208及210的半导体基材200，以形成浅沟槽隔离(STI)。图7B显示半导体基材200沿着图7A所示线段A-A的剖面图。这些工艺步骤皆为现有技术，因此对于这些步骤的详细讨论将予以省略以示简洁。
图8至图11显示形成不规则鳍式有源区图案的步骤。在图8至图10所示内容是有关于光致抗蚀剂，虽然其未显示于图中以作简化。本领域普通技术人员将轻易得知此光致抗蚀剂的应用及功能。图8显示具有鳍202、204、206、208、210及介电层218的半导体基材200的俯视图。半导体基材具有光致抗蚀剂层(未显示)形成于其上，其中此光致抗蚀剂层是经掩模(例如暗区212)曝光。不规则的有源区图案将存在于暗区212所定义的区域中。此掩模使光致抗蚀剂位于鳍202、204、206、208及210上的部分被移除而可被曝光。例如，掩模可为搭配正光致抗蚀剂使用的暗场掩模(dark tonemask)。经曝光后的正光致抗蚀剂变得可溶而自表面移除。正光致抗蚀剂在鳍202、204、206、208及210上的部分为未曝光的部分，将皆保留下来。
掩模的暗区212的边缘(未与X轴平行的部分)，代表相对于暗区212内部的凸状弧形。有源区将顺应凸状弧形的的轮廓(outline)。进行蚀刻工艺以移除鳍202、204、206、208及210的暴露部分。蚀刻工艺使用蚀刻剂以选择性蚀刻鳍202、204、206、208及210，但未蚀刻介电层218。图9显示基材200在进行如图8所述的蚀刻工艺后的基材200的立体图。鳍202’、204’、206’、208’及210’为经蚀刻后所剩余的部分，且形成不规则的有源区图案，其边缘顺应于凸状弧形。
图10及图11显示蚀刻的另一方法。图10显示具有鳍202、204、206、208、210及介电层218的半导体基材200的平面图。半导体基材具有光致抗蚀剂(未显示)形成于其上，其依照如暗区214及216所示的切割掩模(cuttingmask)曝光。暗区214及216之外的透明区定义了不规则有源区图案将存在的地方。切割掩模使光致抗蚀剂的位于鳍202、204、206、208及210上的部分不会被移除及曝光。例如，此切割掩模可为搭配负光致抗蚀剂使用的亮场掩模(clear tone mask)。未曝光的负光致抗蚀剂为可溶的并被移除。负光致抗蚀剂的未位于暗区214及216的部分被曝光，且光致抗蚀剂仍存在于这些区域内。
掩模的暗区214及216的边缘(未与X轴平行的部分)，代表相对于鳍202、204、206、208及210的内部部分(位于经曝光的光致抗蚀剂上)的凹状弧形。有源区将顺应至凹状弧形的外廓。进行蚀刻工艺以移除鳍202、204、206、208及210被光致抗蚀剂所覆盖的部分，需注意的是，在此所指的光致抗蚀剂为受暗区214、216所覆盖而未曝光的光致抗蚀剂。图11显示经如图10所述的蚀刻后的基材200。鳍202”、204”、206”、208”及210”为经历切割工艺后所剩余的部分，并形成边缘顺应于凹状弧形的不规则有源区图案。
在经过如图8、图9或图10、图11的工艺后，可使用传统方法形成鳍式场效应晶体管的剩余部分。例如，在图12中，凹蚀介电层218，并形成栅极介电层220及栅极电极222。因此，可形成如图2或图4所示的结构。
虽然许多实施例及其优点已详述如上，可知的是，在不脱离本发明权利要求所定义的精神及范围下，也可对这些实施例作各种改变、替换或取代。例如，切割掩模及保护掩模皆可使用于形成凸状或凹状弧形，且以上说明未限制可使用的掩模型态。此外，本领域普通技术人员也可知的是，在本发明实施例范围中，可变换各种工艺来形成鳍式场效应晶体管的剩余部分。使用深埋氧化层(BOX)或绝缘层上覆硅(SOI)为常见的现有技术，且可用于替换上述的结构及工艺。再者，可由外延成长来完成鳍式有源区的制造。更进一步地，可考虑在实施例中作任何可减少有源区的接触电阻或降低浅沟槽隔离的应力的应用。
虽然本发明已以多个较佳实施例公开如上，然其并非用以限定本发明，任何本领域普通技术人员，在不脱离本发明的精神和范围内，当可作任意的更动与润饰，因此本发明的保护范围当视所附的权利要求所界定的范围为准。再者，本发明的范围并不限于说明书中所述的特定程序、机器、制造、物质的组合、功能、方法或步骤的实施例，本领域普通技术人员将可依照本发明所公开的现有或未来所发展的特定程序、机器、制造、物质的组合、功能、方法或步骤达成相同的功能或相同的结果。因此本发明的保护范围包含这些程序、机器、制造、物质的组合、功能、方法或步骤。此外，本发明的各个保护范围可视为各别的实施例，且各种保护范围及实施例的组合也在本发明的范围中。

Claims (10)

1.一种半导体装置，包括：
至少三个有源区，其中该至少三个有源区彼此紧邻，其中该至少三个有源区的纵轴相互平行，其中每一有源区各自包含一边缘与该有源区的纵轴相交，且该至少三个有源区的边缘形成一弧形。
2.根据权利要求1所述的半导体装置，其中该弧形为凸状。
3.根据权利要求1所述的半导体装置，其中该弧形为凹状。
4.根据权利要求1所述的半导体装置，还包含一栅极电极及一栅极介电层，其中该栅极电极位于该至少三个有源区的至少一有源区上，该栅极介电层位于该栅极电极上，且该至少三个有源区的其中之一、该栅极介电层及该栅极电极形成一鳍式场效应晶体管。
5.一种半导体装置的制造方法，包含：
提供一半导体基材；
形成一光致抗蚀剂层于该半导体基材上；
图案化该半导体基材上的该光致抗蚀剂层，以使用一光掩模来暴露出该半导体基材的一暴露部分，其中该光掩模包含一含曲线边缘的透明区域，且其中该曲线边缘定义该半导体基材的该暴露区域的一边缘；以及
蚀刻该半导体基材的该暴露部分，以使该半导体基材的该暴露部分的该边缘定义有源区的边缘，其中每一有源区包含一与所对应的边缘相交的纵长。
6.根据权利要求5所述的半导体装置的制造方法，还包含在进行图案化之前，形成含有有源区的条状物于半导体基材中。
7.根据权利要求5所述的半导体装置的制造方法，其中该有源区为鳍式有源区。
8.一种半导体装置的制造方法，包含：
提供一半导体基材；
在该半导体基材上形成多个鳍；以及
图案化所述多个鳍以使每一鳍皆包含一边缘，且所述多个鳍的所述多个边缘形成一弧形。
9.根据权利要求8所述的半导体装置的制造方法，其中该弧形为凸状。
10.根据权利要求8所述的半导体装置的制造方法，其中该弧形为凹状。
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