CN101154662B - 晶体管及其制造方法 - Google Patents

晶体管及其制造方法 Download PDF

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CN101154662B
CN101154662B CN2007101617812A CN200710161781A CN101154662B CN 101154662 B CN101154662 B CN 101154662B CN 2007101617812 A CN2007101617812 A CN 2007101617812A CN 200710161781 A CN200710161781 A CN 200710161781A CN 101154662 B CN101154662 B CN 101154662B
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semiconductor substrate
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南炳虎
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SK Hynix Inc
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Abstract

本发明公开了一种晶体管及其制备方法,该晶体管包含:包含由器件隔离层所界定的有源区的半导体基板;在该半导体基板的有源区上隔开特定间隔的栅线;及在与栅线端部接触的半导体基板的有源区中蚀刻至特定深度的凹结构的沟槽。

Description

晶体管及其制造方法
技术领域
本发明涉及一种半导体器件,且更具体地涉及一种能够降低漏电流的晶体管及其制造方法。
背景技术
一般来说,晶体管包含形成于半导体基板上的线路中的栅电极(下文中称为“栅线”),以及通过在栅电极的两侧暴露的半导体基板中注入n型或p型导电杂质而形成的源极/漏极区。
随着半导体器件的高度集成的趋势,栅线的宽度已变得愈来愈小。栅线宽变得较小时,当电压从晶体管的源极被施加至漏极时,由于热电子感应贯穿(HEIP)效应,故可能在栅线的端部产生漏电流,因而降低操作特性。
此外,栅线的端部,亦即,外围电路区中毗邻器件隔离层的边缘部,形成为具有比有源区中的栅线宽度还宽的宽度的垂片形状(tab form),以防止该漏电流由于HEIP效应而产生。
图1A到1C为用于解释传统晶体管的示意图。图1B与1C为沿着图1A中线A-A’与B-B’取的晶体管剖面图。
参照图1A到1C,传统晶体管包括在半导体基板的有源区10上以指定间隔设置的栅线20。与毗邻器件隔离区的有源区10接触的每一栅线20的端部30形成为垂片形状,该垂片形状具有比栅线20的线宽还宽的宽度。将连接到源极/漏极区的接触电极40设置于栅线20之间的有源区10上。在此,该器件隔离区(未示出)为除了有源区10以外的剩余区域。
在具有上述配置的晶体管中,栅线20(示于图1C)的端部30形成为垂片形状,该垂片形状具有比设置于有源区10(示于图1B)上的栅线20的线宽还宽的宽度。亦即,与毗邻器件隔离区的有源区10接触的栅线20端部30形成为具有大的宽度的垂片形状,以减少当电压从晶体管的源极施加至漏极时,由于HEIP效应而在外围电路区中栅线20的端部30上产生的漏电流。
然而,需要用于垂片的额外空间,以形成具有大宽度的垂片形状的栅线20的端部30,因而增加器件芯片的整体尺寸。因此,降低器件集成度。
发明内容
在一个方面中,本发明提供一种晶体管,其通过将端部形成为台阶部(stepped portion)并增加沟道长度,能够最小化在置为毗邻器件隔离层的栅线的端部上产生的漏电流。
在另一方面中,本发明提供一种用以晶体管的制造方法,该方法可以通过增加沟道长度来最小化在置为毗邻器件隔离层的栅线的端部上所产生的漏电流。
依据本发明的一个方面,晶体管包含:包含由器件隔离层界定的有源区的半导体基板;在该半导体基板的有源区上隔开特定间隔的栅线;及在与该栅线的端部接触的该半导体基板中蚀刻至特定深度的凹结构的沟槽。
在该晶体管中,该凹结构的沟槽优选地形成为矩形形状并置于半导体基板的有源区的端部中。此外,优选地,此凹结构的沟槽置为毗邻器件隔离层。
优选地,该栅线的端部具有T形剖面。
此晶体管优选地还包含形成于该栅线的两侧上的接触区。
至少一条该栅线优选地包含在外围电路区中的NMOS晶体管或PMOS晶体管内。
依据本发明的另一方面,晶体管包含:包含由器件隔离层界定的有源区的半导体基板;在该半导体基板的有源区上隔开特定间隔的栅线;及凸形结构的突出物,在与该栅线的端部接触的部分内从该半导体基板的表面突出特定高度。
在此晶体管中,该凸形结构的突出物优选地形成为矩形形状,并置于半导体基板的有源区的端部中。此外,该凸形结构的突出物优选地置为毗邻器件隔离层。
优选地,该栅线的端部具有反U形剖面,该凹陷的剖面面对半导体基板。
该晶体管优选地还包含形成于栅线的两侧上的接触区。
至少一条该栅线优选地包含于外围电路区中的NMOS晶体管或PMOS晶体管内。
依据本发明的再一方面,一种晶体管的制造方法包含:在包含单元区与外围电路区的半导体基板中形成器件隔离层;在该外围电路区中的有源区的端部内形成凹结构的沟槽;及形成与该凹结构的沟槽啮合的栅线。
在该晶体管的制造方法中,形成凹结构的沟槽优选地可包含形成光敏抗蚀剂膜图案,以覆盖半导体基板的单元区并露出外围电路区中毗邻器件隔离层的有源区;及通过光敏抗蚀剂膜图案的掩模蚀刻该外围电路区中的该露出区,以形成该凹结构的沟槽。
该形成凹沟槽的步骤优选地包含形成光敏抗蚀剂膜图案,以在半导体基板的单元区中露出用于形成凹陷沟道的区域,并在外围电路区中露出毗邻该器件隔离层的有源区;及使用光敏抗蚀剂膜图案的掩模执行蚀刻工艺,以在单元区中形成凹陷沟道并在外围电路区中形成凹结构的沟槽。
优选地,该凹结构的沟槽优选地形成为矩形形状并置为毗邻器件隔离层。
优选地,该栅线的端部具有T形剖面。
依据本发明另一方面,一种晶体管的制造方法包含:在包含单元区与外围电路区的半导体基板中形成器件隔离层;在该外围电路区中的有源区的端部内形成具有平坦上表面的凸形结构的突出物;及形成与凸形结构的突出物啮合的栅线。
在该晶体管的制造方法中,形成凸形结构的突出物的步骤优选地包含形成光敏抗蚀剂膜图案,以覆盖半导体基板的单元区,并露出外围电路区中毗邻器件隔离层的有源区;及通过光敏抗蚀剂膜图案的掩模蚀刻该外围电路区中的露出区域,以形成凸形结构的突出物。
形成凸形结构的突出物的步骤还包含形成光敏抗蚀剂膜图案,以露出在半导体基板的单元区中用于形成鳍形突出物的区域,及露出在外围电路区中毗邻该器件隔离层的有源区;及使用光敏抗蚀剂膜图案的掩模执行蚀刻工艺,以在单元区中形成鳍形突出物并在外围电路区中形成凸形结构的突出物。
优选地,该凸形结构的突出物形成为矩形形状并置为毗邻器件隔离层。
优选地,该栅线的端部具有反U形剖面。
附图说明
本发明的上述与其它观点、特征及其它优点将从下列详细说明并结合附加图式而可被清楚了解,其中:
图1A到1C为说明传统晶体管的示意图;
图2为说明依照本发明配置的晶体管的结构的示意图;
图3到6为说明单元区与外围电路区中栅线的端部的示意图;
图7显示栅线的剖面示意图;及
图8A-8C、9A-9C、10A-10C和11A-11C为依据本发明的实施例晶体管的制造方法的示意图。
10、100:                                  有源区
20、110、202、204、206、208、210、212、214、
216、306、308、314、316、322、324、332、334:  栅线
30、120:                                  端部
40、130:                                  接触电极
105:                                      器件隔离区
200、300:                                 半导体基板
205、207、209、304、311、312:             沟槽
213、215、217、320、328、330:             突出物
302、310、318、326:                       光敏抗蚀剂膜图案
d:                                        深度
具体实施方式
本发明的优选实施例现在将参照附图详细说明如下。这些实施例仅用以说明本发明的目的,而本发明并不限于此。
图2为依照本发明配置的晶体管的结构的示意图。
参照图2,依据本发明配置的晶体管包含在半导体基板的有源区100上隔开特定间隔的栅线110。置于毗邻器件隔离区105的半导体基板的有源区100上的每一栅线110的端部120啮合蚀刻至特定深度的凹结构的沟槽或突出特定高度的凸形结构。在此,该晶体管在外围电路区中包括NMOS晶体管及PMOS晶体管。器件隔离区105为除了有源区100以外的剩余区,且器件隔离区105与有源区100由如浅沟槽隔离(STI)的器件隔离层(未示出)分隔。在图式中,“X”指示栅线延伸的方向,“Y”指示垂直X方向的方向。
再者,虽然图中未示出,间隔物形成于栅线110的两侧壁上,且源极/漏极区形成于在栅线110的两侧面上露出的基板的有源区100中。再者,接触电极130形成于有源区100上,使得接触电极130垂直连接到源极/漏极区。
由于形成于毗邻器件隔离区的半导体基板的有源区100中的凹结构的沟槽,栅线110的端部120可具有T形剖面。再者,由于形成于毗邻器件隔离区的半导体基板的有源区100中形成的凸形结构的突出物,栅线110的端部120可具有反U形剖面,其中该剖面中的凹陷面向基板。
在本发明的晶体管中,与半导体基板的有源区100接触的栅线端部120形成为具有一宽度,该宽度等于形成于有源区100上的栅线110的线宽。由于形成于有源区中的凹结构的沟槽或凸形结构的突出物,栅线110的端部120具有T形剖面或反U形剖面,其中该反U形剖面中的凹陷面向基板。因此,栅线的沟道长于传统栅线的沟道。由此,所有栅线可设计成具有相同线宽,同时可降低当电压从晶体管的源极施加至漏极时由于HEIP效应在每一栅线的端部上产生的漏电流。
此后,将描述单元区与外围电路区中的栅线的端部。
图3到6示出图2中沿线C-C’截取的外围电路区的剖面图。图7示出沿线D-D’截取的外围电路区中栅线的剖面图。
参照图3,本发明晶体管的第一栅线结构包含单元区内的栅线202,该栅线在半导体基板200上形成为具有平坦底面。该第一栅线结构还包括在包含NMOS与PMOS区域的外围电路区中的栅线204,其中栅线204的端部啮合凹结构的沟槽205,该凹结构的沟槽205是通过从基板表面蚀刻基板至特定深度而形成于毗邻器件隔离区的半导体基板200的有源区中。再者,“X”指示栅线延伸的方向,且“Y”指示垂直X方向的方向。下面省略有关X与Y的说明。
参照图4,本发明晶体管的第二栅线结构包含单元区内的栅线206,该栅线啮合用于凹陷沟道的沟槽207,其中该沟槽207是通过从基板表面蚀刻基板至特定深度而形成的。该第二栅线结构还包括外围电路区中的栅线208,其中栅线208的端部啮合凹结构的沟槽209,其中该沟槽209是通过从基板表面蚀刻基板至特定深度而形成于毗邻器件隔离层的半导体基板200的有源区中。
参照图5,本发明晶体管的第三栅线结构包含单元区内的栅线210,该栅线210形成为在毗邻器件隔离层的半导体基板200有源区上的具有平坦底面并具有栅线端部。第三栅线结构还包括在包含NMOS与PMOS区的外围电路区中的栅线212,其中栅线212的端部啮合凸形结构的突出物,该突出物形成于毗邻器件隔离层的半导体基板200有源区上,以从基板的表面突出特定高度。
参照图6,本发明晶体管的第四栅线结构包含单元区内的栅线214,栅线214啮合从半导体基板200的表面突出特定高度的突出物。第四栅线结构还包括在包含NMOS与PMOS区域的外围电路区中的栅线216,其中栅线216的端部啮合具有平坦顶面的凸形结构的突出物217,该突出物形成于毗邻器件隔离层的半导体基板200有源区上,以从基板的表面突出特定高度。
如图3到6中所示,在外围电路区中,晶体管的栅线的端部形成为啮合该凹结构的沟槽205与209或者该凸形结构的突出物213与217。因此,栅线的端部可形成为具有与图7所示栅线的线宽b相同的线宽a。
之后,将依据本发明实施例描述本发明晶体管的制造方法。
图8A到8C为本发明第一实施例的晶体管的制造方法的示意图,其中栅线的端部与凹结构的沟槽啮合。
参照图8A,光敏抗蚀剂膜图案302形成于包含器件隔离区的半导体基板300上,以覆盖单元区中的基板300并选择性地露出外围电路区中的基板300。在外围电路区中,优选地仅露出毗邻器件隔离区的将与栅线端部啮合的区域。
参照图8B,在外围电路区中,与栅线端部啮合的该露出区域通过光敏抗蚀剂膜图案302的掩模被蚀刻,使得形成凹结构的沟槽304。该凹结构的沟槽304可以形成为矩形形状。
接着,如图8C中所示,隔开特定间隔的栅线306与308通过在半导体基板300上沉积和图案化栅绝缘薄膜(未示出)与栅电极而形成。具体而言,具有平坦底面的栅线306形成于单元区中,且栅线308形成于外围电路区中,其中栅线308的端部与毗邻器件隔离区的凹结构的沟槽304啮合。栅线308的端部由于形成于半导体基板上的该凹结构的沟槽304而具有T形剖面。再者,“X”指示栅线延伸的方向,且“Y”指示垂直该X方向的方向。此后将省略X与Y方向的说明。
图9A到9C为本发明第二实施例的晶体管的制造方法的示意图,其中栅线的端部与凹结构的沟槽啮合。
参照图9A,光敏抗蚀剂膜图案310形成于包含器件隔离区的半导体基板300上,以选择性地露出单元区与外围电路区中的基板300。在此情况下,单元区与外围电路区中的露出区域为用于分别形成凹陷沟道与沟槽的区域。在外围电路区中,优选地仅露出毗邻器件隔离区的将与栅线端部啮合的半导体基板300有源区。
参照图9B,在单元区与外围电路区中的露出区域通过光敏抗蚀剂膜图案310的掩模被蚀刻,形成凹结构的沟槽311与312。该凹结构的沟槽312可以形成为矩形形状。
接着,如图9C所示,隔开特定间隔的栅线314与316通过在半导体基板300上沉积和图案化栅绝缘薄膜(未示出)与栅极而形成。具体而言,在单元区中形成用于凹陷沟道的栅线314,在外围电路区中形成栅线316,其中栅线316的端部与毗邻器件隔离区的该凹结构的沟槽312啮合。由于该凹结构的沟槽312,外围电路区中形成的栅线316的端部具有T形剖面。在此情况下,在用于凹陷沟道的沟槽311形成于单元区中时,该凹结构的沟槽312同时形成于外围电路区中,因此光刻工艺中的许多步骤可以减少。
如上所述,在外围电路区中,栅线的端部啮合形成于毗邻器件隔离区的半导体基板的有源区中的该凹结构的沟槽。因此,该沟道可以被延长,同时该栅线的端部形成为具有与栅线宽度相同的线宽。因此,相邻栅线之间的间隔可进一步缩短,由此改善器件的集成度。再者,由于毗邻器件隔离区的栅线的端部形成为具有与栅线宽度相同的线宽,故其可防止垂片之间的接触并改善器件的特性。
图10A到10C为本发明第三实施例的制造晶体管的方法的示意图,其中栅线的端部啮合凸形结构的突出物。
参照图10A,光敏抗蚀剂膜图案318形成于包含器件隔离区的半导体基板300上,以覆盖单元区中的基板300并选择性地覆盖外围电路区中的基板300。在外围电路区中,优选地仅覆盖毗邻器件隔离区的将与栅线端部啮合的半导体基板300有源区。
参照图10B,在外围电路区中,外围电路区中的露出区域通过光敏抗蚀剂膜图案318被蚀刻,使得形成具有平坦顶面的凸形结构的突出物,其中该突出物从基板的表面突出。该凸形结构的突出物320可以形成为矩形形状。在此情况下,凸形结构的突出物320可通过从基板表面蚀刻半导体基板300至特定深度c而形成。
接着,如图10C所示,隔开特定间隔的栅线322与324通过在半导体基板300上沉积和图案化栅绝缘薄膜(未示出)与栅极而形成。栅线324的端部具有反U形剖面,其中该反U形剖面中的凹陷面对半导体基板300。
图11A到11C为本发明第四实施例的晶体管制造方法的示意图,其中栅线的端部与凸形结构的突出物啮合。
参照图11A,光敏抗蚀剂膜图案326形成于包含器件隔离区的半导体基板300上,以选择性地覆盖单元区与外围电路区中的基板300。在外围电路区中,优选地仅覆盖毗邻器件隔离区的将啮合栅线端部的半导体基板300有源区。
参照图11B,单元区与外围电路区中的露出区通过光敏抗蚀剂膜图案326的掩模被蚀刻,使得鳍形突出物328形成于单元区中,且具有平坦顶面的凸形结构的突出物330形成于外围电路区中从基板的表面突出。该凸形结构的突出物330可以形成为矩形形状。这种情况下,该凸形结构的突出物330可通过从基板表面蚀刻半导体基板300至特定深度d来形成。
接着,如图11C所示,隔开特定间隔的栅线332与334通过在半导体基板300上沉积与图案化栅绝缘薄膜与栅电极而形成。具体而言,用于鳍沟道的栅线332形成于单元区中,且栅线334形成于外围电路区中,其中由于形成于半导体基板300上的凸形结构的突出物330,栅线334的端部具有反U形剖面。在此情况下,当用于鳍沟道的突出物328形成于单元区中时,凸形结构的突出物330同时形成于外围电路区中,因此光刻工艺中的许多步骤可以减少。
如上所述,毗邻器件隔离区的栅线端部啮合外围电路区中的凸形结构的突出物。因此,该沟道可以被延长,同时栅线端部形成为具有与栅线宽度相同的线宽。因此,相邻栅线之间的间隔可进一步缩短,由此改善器件的集成度。再者,由于毗邻器件隔离区的栅线端部形成为具有与栅线宽度相同的线宽,故可防止垂片间的接触并改善器件的特性。
接下来,虽然未示于图中,通过在栅线上沉积与图案化如氮化硅膜的绝缘膜,从而在与凹结构的沟槽及凸形结构的突出物啮合的栅线的两侧壁上形成间隔物膜。接着,通过执行n型或p型导电杂质的离子注入于基板的有源区中而在半导体基板中形成源极/漏极区,由此形成晶体管。
在本发明晶体管的制造方法中,栅线的端部啮合蚀刻至特定深度的凹结构的沟槽或形成于半导体基板的有源区中突出特定高度的凸形结构的突出物。由于与有源区接触的栅线的端部具有T形剖面或反U形剖面,该反U形剖面中具有面对基板的凹陷,由于该沟槽或突出物,沟道可长于一般栅线同时与有源区接触的栅线端部形成为具有与一般栅线宽度相同的线宽。
如上所述,依照本发明,凹结构的沟槽或突出特定高度的凸形结构的突出物形成于有源区中与栅线的端部接触,因而沟道可长于一般栅线,同时与有源区接触的栅线端部形成为具有与一般栅线宽度相同的线宽。
因此,依照本发明通过形成凹结构的沟槽或突出特定高度的凸形结构的突出物,其可降低当电压从晶体管的源极施加至漏极时由于HEIP效应在栅线端部的界面上产生的漏电流。再者,所有栅线均可设计成具有相同线宽,因而可防止半导体器件芯片尺寸的增大。此外,通过形成具有相等线宽的栅线,其可确保该栅线下阈值电压的稳定性。
虽然本发明的优选实施例已详细说明目的,但所属技术领域中的技术人员将可察知各种不同修改、附加与替换均为可行的,而仍不脱离由权利要求所界定的本发明范围与精神。
本申请主张2006年9月29日申请的韩国专利申请第10-2006-95705号的优先权,在此引入参考其全文。

Claims (20)

1.一种晶体管,包含:
包含由器件隔离层所界定的有源区的半导体基板;及
在所述半导体基板的有源区上隔开特定间隔的栅线;
其中,所述栅线包括与仅位于所述半导体基板的有源区域的端部的凹结构的沟槽相啮合的端部,所述沟槽在所述半导体基板的有源区的端部中被蚀刻至特定深度,并且所述栅线的端部的沟道长度由于所述沟槽而增加。
2.如权利要求1所述的晶体管,其中所述凹结构的沟槽形成为矩形形状。
3.如权利要求1所述的晶体管,其中所述栅线具有呈T形剖面的端部。
4.如权利要求1所述的晶体管,还包括:
形成于所述栅线两侧上的接触区。
5.如权利要求1所述的晶体管,其中至少一条所述栅线包含在外围电路区中NMOS晶体管或PMOS晶体管内。
6.一种晶体管,包含:
包含由器件隔离层所界定的有源区的半导体基板;及
在所述半导体基板的有源区上隔开特定间隔的栅线;
其中,所述栅线包括与仅位于所述半导体基板的有源区域的端部的凸形结构的突出物相啮合的端部,所述突出物在所述半导体基板的有源区的端部内从所述半导体基板的表面突出特定高度,并且所述栅线的端部的沟道长度由于所述突出物而增加。
7.如权利要求6所述的晶体管,其中所述凸形结构的突出物形成为矩形形状。
8.如权利要求6所述的晶体管,其中所述栅线具有反U形剖面的端部,所述剖面中的凹陷面对所述半导体基板。
9.如权利要求6所述的晶体管,还包括:
形成于所述栅线的两侧上的接触区。
10.如权利要求6所述的晶体管,其中至少一条所述栅线包含于外围电路区中的NMOS晶体管或PMOS晶体管内。
11.一种晶体管的制造方法,包含:
在包含单元区与外围电路区的半导体基板中形成器件隔离层;
在所述半导体基板的外围电路区中的有源区的端部中形成凹结构的沟槽;及
形成啮合该凹结构的沟槽的栅线,所述栅线的端部的沟道长度由于所述沟槽而增加。
12.如权利要求11所述的方法,其中形成凹结构的沟槽的步骤包括:
形成光敏抗蚀剂膜图案,以覆盖所述半导体基板的单元区,并露出所述外围电路区中毗邻所述器件隔离层的所述有源区;及
通过所述光敏抗蚀剂膜图案的掩模蚀刻所述外围电路区中的所述露出区域,以形成所述凹结构的沟槽。
13.如权利要求11所述的方法,其中形成凹结构的沟槽的步骤包括:
形成光敏抗蚀剂膜图案,以露出在所述半导体基板的单元区中用于形成凹陷沟道的区域,并露出所述外围电路区中毗邻所述器件隔离层的所述有源区;及
使用所述光敏抗蚀剂膜图案的掩模执行蚀刻工艺,以在所述单元区中形成凹陷沟道并在所述外围电路区中形成所述凹结构的沟槽。
14.如权利要求11所述的方法,其中所述凹结构的沟槽形成为矩形形状。
15.如权利要求11所述的方法,其中所述栅线具有T形剖面的端部。
16.一种晶体管的制造方法,包含:
在包含单元区与外围电路区的半导体基板中形成器件隔离层;
在所述半导体基板中的外围电路区中的有源区的端部中形成具有平坦顶面的凸形结构的突出物;及
形成啮合所述凸形结构的突出物的栅线,所述栅线的端部的沟道长度由于所述突出物而增加。
17.如权利要求16所述的方法,其中形成凸形结构的突出物的步骤包含:
形成光敏抗蚀剂膜图案,以覆盖所述半导体基板的单元区,并覆盖所述外围电路区中毗邻所述器件隔离层的所述有源区;及
通过光敏抗蚀剂膜图案的掩模蚀刻所述外围电路区中的露出区域,以形成凸形结构的突出物。
18.如权利要求16所述的方法,其中形成凸形结构的突出物的步骤包含:
形成光敏抗蚀剂膜图案,以覆盖半导体基板的单元区中用于形成鳍形突出物的区域,并覆盖所述外围电路区中毗邻所述器件隔离层的所述有源区;及
使用所述光敏抗蚀剂膜图案的掩模执行蚀刻工艺,以在所述单元区中形成鳍形突出物并在所述外围电路区中形成凸形结构的突出物。
19.如权利要求16所述的方法,其中所述凸形结构的突出物形成为矩形形状。
20.如权利要求16所述的方法,其中所述栅线具有反U形剖面的端部。
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KR101031484B1 (ko) * 2009-04-08 2011-04-26 주식회사 하이닉스반도체 반도체 소자 및 그 형성 방법
KR20110015803A (ko) * 2009-08-10 2011-02-17 삼성전자주식회사 반도체 메모리 소자
US8546854B2 (en) * 2010-04-30 2013-10-01 SK Hynix Inc. Semiconductor device and method for manufacturing the same
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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1231763A (zh) * 1996-09-30 1999-10-13 西门子公司 半导体只读存储器及其制造方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100195836B1 (ko) * 1994-03-19 1999-06-15 김영환 디램소자 및 그 제조방법
KR100245248B1 (ko) * 1996-12-28 2000-02-15 김영환 반도체장치의 제조방법
JP2002151688A (ja) * 2000-08-28 2002-05-24 Mitsubishi Electric Corp Mos型半導体装置およびその製造方法
JP4097417B2 (ja) * 2001-10-26 2008-06-11 株式会社ルネサステクノロジ 半導体装置
US7358121B2 (en) * 2002-08-23 2008-04-15 Intel Corporation Tri-gate devices and methods of fabrication
KR100558007B1 (ko) * 2003-11-24 2006-03-06 삼성전자주식회사 트랜지스터 및 그 제조방법
KR100518606B1 (ko) * 2003-12-19 2005-10-04 삼성전자주식회사 실리콘 기판과 식각 선택비가 큰 마스크층을 이용한리세스 채널 어레이 트랜지스터의 제조 방법
KR100574340B1 (ko) * 2004-02-02 2006-04-26 삼성전자주식회사 반도체 장치 및 이의 형성 방법
KR100610496B1 (ko) * 2004-02-13 2006-08-09 삼성전자주식회사 채널용 핀 구조를 가지는 전계효과 트랜지스터 소자 및 그제조방법
KR100605104B1 (ko) * 2004-05-04 2006-07-26 삼성전자주식회사 핀-펫 소자 및 그 제조 방법
KR100618861B1 (ko) * 2004-09-09 2006-08-31 삼성전자주식회사 로컬 리세스 채널 트랜지스터를 구비하는 반도체 소자 및그 제조 방법
JP2006114834A (ja) * 2004-10-18 2006-04-27 Toshiba Corp 半導体装置
DE102005014744B4 (de) * 2005-03-31 2009-06-18 Infineon Technologies Ag Trenchtransistor mit erhöhter Avalanchefestigkeit und Herstellungsverfahren
US7189617B2 (en) * 2005-04-14 2007-03-13 Infineon Technologies Ag Manufacturing method for a recessed channel array transistor and corresponding recessed channel array transistor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1231763A (zh) * 1996-09-30 1999-10-13 西门子公司 半导体只读存储器及其制造方法

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