CN102097394A - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
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- CN102097394A CN102097394A CN2010105929798A CN201010592979A CN102097394A CN 102097394 A CN102097394 A CN 102097394A CN 2010105929798 A CN2010105929798 A CN 2010105929798A CN 201010592979 A CN201010592979 A CN 201010592979A CN 102097394 A CN102097394 A CN 102097394A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 61
- 238000000034 method Methods 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 229920005989 resin Polymers 0.000 claims abstract description 353
- 239000011347 resin Substances 0.000 claims abstract description 353
- 239000000758 substrate Substances 0.000 claims description 37
- 238000010276 construction Methods 0.000 claims description 14
- 238000009434 installation Methods 0.000 claims description 12
- 229920006395 saturated elastomer Polymers 0.000 claims description 5
- 238000003825 pressing Methods 0.000 claims description 3
- 230000001681 protective effect Effects 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 38
- 238000005516 engineering process Methods 0.000 description 12
- 238000007789 sealing Methods 0.000 description 8
- 239000000463 material Substances 0.000 description 6
- 239000012535 impurity Substances 0.000 description 5
- 239000004020 conductor Substances 0.000 description 4
- 230000001105 regulatory effect Effects 0.000 description 4
- 239000000654 additive Substances 0.000 description 3
- 230000000996 additive effect Effects 0.000 description 3
- 230000001419 dependent effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000002156 mixing Methods 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000000116 mitigating effect Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 125000003903 2-propenyl group Chemical group [H]C([*])([H])C([H])=C([H])[H] 0.000 description 1
- 229920003180 amino resin Polymers 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000000839 emulsion Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229920001568 phenolic resin Polymers 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 229920006337 unsaturated polyester resin Polymers 0.000 description 1
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Abstract
一种半导体器件及其制造方法。该半导体器件包括电极焊盘和具有暴露电极焊盘的开口的保护绝缘膜。该半导体器件进一步包括凸块,即树脂芯凸块,其包括形成在保护绝缘膜上的凸块芯,即树脂芯,和形成在该凸块芯上的导电层。半导体器件进一步包括连接导电层和电极焊盘的互连。凸块芯为具有不同弹性模量的例如第一和第二树脂层的多个树脂层的层叠形式。
Description
本申请基于日本专利申请No.2009-284100,其内容通过引用合并于此。
技术领域
本发明涉及一种半导体器件及其制造方法。
背景技术
对于半导体器件的凸块,日本特开专利公布NO.02-272737公开了一种树脂芯凸块,其包括由树脂制成的凸块芯和涂覆到凸块芯的表面上的导电膜,从而展现出良好的弹性。
同时,日本特开专利公布NO.2003-037135公开了一种通过在绝缘衬底的表面上提供导体图案、在导体图案上提供导电突起(凸块芯)以及通过选择性蚀刻在导电突起上形成导体互连来形成凸块的技术。
根据日本特开专利公布No.2003-037135中公开的技术,导电突起是利用镀方法由具有不同硬度的两层金属导体(第一突起组件和第二突起组件)形成的。
树脂芯凸块利用其凸块芯的弹性能够稳定地连接到安装衬底的外部电极。因而,用于凸块芯的树脂的弹性特性对于获得树脂芯凸块和外部电极之间的良好连接性来说是非常重要的。
发明内容
本发明人已经认识到了如下内容。根据在日本特开专利公布NO.02-272737中公开的技术,由于凸块芯(树脂芯)由单层树脂形成,所以树脂芯凸块的弹性特性取决于单层树脂的固有硬度。
树脂芯和树脂芯凸块需要具有某种程度大小的排斥力。然而,如果由于强调该排斥力而增加树脂芯的硬度,那么消弱了树脂芯和树脂芯凸块的可变形性。
结果,不能获得凸块和外部电极之间的足够的连接性。具体而言,存在这种可能:如果由于在外部电极或凸块的顶表面上存在杂质等造成表面上的倾斜、翘曲、不平坦或突出,则使得凸块和外部电极之间的贴合不充分,这会导致凸块和外部电极之间的不充分的连接性。
根据在日本特开专利公布NO.2003-037135中公开的技术,凸块芯由金属导体制成。相信这对于凸块芯的优异的强度是有帮助的。然而,由于金属的可变形性显著低于树脂的可变形性,所以即使凸块芯具有层叠结构,由金属导体制成的凸块芯的变形量也非常小。为此,即使用在日本特开专利公布NO.2003-037135中公开的构造,有时也不能在凸块和外部电极之间获得良好的贴合性和连接性。
如上所述,凸块很难具有足够的贴合性和足够的排斥力以提高凸块和外部电极之间的连接性。
在一个实施例中,提供一种半导体器件,其包括:电极焊盘;保护绝缘膜,其具有被构造成暴露电极焊盘的开口;凸块,其包括形成在保护绝缘膜上的凸块芯和形成在凸块芯上的导电层;以及连接导电层和电极焊盘的互连。凸块芯具有弹性模量不同的多个树脂层的层叠结构。
根据本发明,凸块的凸块芯具有弹性模量不同的多个树脂层的层叠结构。为此,基于下面的(1)和(2)中任一个的原理,可以获得凸块和外部电极之间的良好的贴合性。
(1)当具有相对小弹性模量(软)的树脂层位于层叠结构的最上层时,表面层的树脂层变形以适应穿过导电层的外部电极的形状。由此,可以获得凸块和外部电极之间的良好的贴合性。为此,即使由于在外部电极或凸块的表面上存在杂质等造成表面上倾斜、翘曲、不平坦或突出,也可以获得凸块和外部电极之间的良好的贴合性。
(2)接下来,将描述具有相对小弹性模量(软)的一个树脂层位于层叠结构的下层或中间层以及具有比前面的树脂层的弹性模量大的弹性模量的另一个树脂层位于层叠结构的最上层的情况。在这种情况下,在前面的树脂层变形时,后面的树脂层和导电层倾斜以顺从于外部电极的形态。为此,可以获得凸块和外部电极之间的良好的贴合性。
通过存在具有相对大的弹性模量的树脂层,可以将凸块芯构造成具有足够的排斥力。
因此,凸块可以被构造成具有足够的贴合性和足够的排斥力,并且可以提高凸块和外部电极之间的连接性。
在另一实施例中,提供一种电子设备,其包括半导体器件和具有电极的安装衬底。凸块连接到安装衬底的电极。
在又一实施例中,提供一种半导体器件的制造方法,其包括:在形成电极焊盘的衬底上形成具有被构造成暴露电极焊盘的开口的保护绝缘膜;在保护绝缘膜上,层压多个固化后具有不同弹性模量的光敏树脂膜;曝光、显影和固化多个光敏树脂膜,以在保护绝缘膜上形成具有不同弹性模量的多个树脂层的层叠结构作为凸块芯;以及形成导电层,该导电层从凸块芯的上部延伸到电极焊盘的上部。
根据本发明,半导体器件的凸块可以被构造成具有足够的贴合性和足够的排斥力,并且可以提高凸块和外部电极之间的连接性。
附图说明
结合附图,根据下面的某些优选实施例的描述,本发明的上述和其它的目的、优点和特征将变得更明显,其中:
图1是示出根据实施例的半导体器件的平面图;
图2是示出根据实施例的半导体器件的截面图;
图3A至3E是示出根据实施例的半导体器件的制造方法的系列工艺的截面图;
图4是示出根据实施例的电子设备的截面图;
图5A至5C是示出安装时的树脂芯凸块的表现的截面图;
图6A和6B是示出在安装衬底的电极中发生翘曲的情况下的安装时的树脂芯凸块的表现的截面图;
图7A和7B是示出在安装衬底的电极倾斜的情况下的安装时的树脂芯凸块的表现的截面图;
图8是示出多个树脂层和树脂芯的变形特性的示例的图;
图9是示出多个树脂层和树脂芯的变形特性的另一示例的图;
图10A和10B是示出根据第一修改的半导体器件的树脂芯凸块的表现的截面图;
图11是根据第二修改的半导体器件的平面图;
图12是根据第二修改的半导体器件的截面图;
图13是根据第三修改的半导体器件的平面图;以及
图14是根据第三修改的半导体器件的截面图。
具体实施方式
现在在这里将参考示出实施例描述本发明。本领域的技术人员将认识到:利用本发明的教导可以实现许多替代实施例,并且本发明并不限于为说明目的而示出的实施例。
为了便于理解本发明的实施例,在平面图中附有阴影。参考附图,下面将说明本发明的实施例。注意,在所有图中,任何相同的组件将赋予相同的附图标记或符号,并因此将不重复说明。
首先,将描述根据该实施例的半导体器件100。
图1是根据实施例的半导体器件100的平面图,并且图2是沿着图1的线A-A截取的截面图。
根据该实施例的半导体器件100包括电极焊盘2和保护绝缘膜3,在保护绝缘膜3中形成暴露电极焊盘2的开口3a。半导体器件100进一步包括凸块(树脂芯凸块6),其包括形成在保护绝缘膜3上的凸块芯(树脂芯4)和形成在凸块芯上的导电层5a。半导体器件100进一步包括互连5b,其连接导电层5a和电极焊盘2。凸块芯具有弹性模量不同的多个树脂层(例如,第一和第二树脂层11和12)的层叠结构。
在下文中,将详细描述构造。
半导体器件100包括半导体衬底1。在该半导体衬底1中,与电极焊盘2一起形成诸如形成电路的晶体管的元件(在图中未示出)。
保护绝缘膜3形成在半导体衬底1上,并且树脂芯凸块6的树脂芯4形成在保护绝缘膜3上。
半导体器件100包括互连5,其从树脂芯4的上部延伸到电极焊盘2的上部。提供在树脂芯4上的互连5的部分形成导电层5a。导电层5a和树脂芯4形成树脂芯凸块6。同时,除了导电层5a之外的互连5的部分形成互连5b。
树脂芯凸块6连接到将在下文中描述的安装衬底151的电极152(图4)。在连接时,由于树脂芯凸块6和电极152彼此压靠,所以树脂芯凸块6的树脂芯4被压缩并变形。
树脂芯凸块6的树脂芯4具有弹性模量不同的多个树脂层11和12的层叠结构。
组成树脂芯4的树脂层11和12的数目是等于或大于2的任意数目。然而,在该实施例中,使用两层树脂层11和12构造树脂芯4。
位于下层的第一树脂层11的弹性模量或位于上层的第二树脂层12的弹性模量可以比另一个小(更软)。然而,在该实施例中,上层的第二树脂层12的弹性模量相对小(软),且下层的树脂层11的弹性模量相对大(硬)。
能够使用诸如酚醛树脂、环氧树脂、聚酰亚胺、氨基树脂、非饱和聚酯树脂、硅树脂或烯丙基树脂的热硬化树脂构造第一和第二树脂层11和12。第一和第二树脂层11和12中的每一个可以具有绝缘性质。
树脂芯4中的树脂层11和12中的每一个的弹性模量的大小主要由材料确定,并且通过适当选择树脂层11和12中的每一个的材料能够调节树脂层11和12中的每一个的弹性模量。
通过除了选择诸如聚酰亚胺和环氧树脂的基本材料之外还选择添加剂或溶剂的类型和量,能够调节树脂层11和12的弹性模量。而且,通过将基本材料与无机粉末混合能够调节树脂层11和12的弹性模量。
而且,当树脂层11和12由热硬化材料制成时,通过调节固化时的温度曲线能够调节树脂层11和12的弹性模量。
树脂芯4中的树脂层11和12中的每一个的变形量主要由树脂层11和12中的每一个的弹性模量和形状决定。与形状有关的变形量取决于安装时按压的面积,即树脂层11和12中的每一个的顶部的面积与由按压引起树脂变形的区域的面积,即由树脂层11和12中的每一个的侧面限定的面积的比。换言之,树脂层11和12中的每一个变形量随着其顶部面积的减小而增加。树脂层11和12中的每一个的变形量通常随着其侧面的倾斜角的增加而增加。树脂层11和12中的每一个的变形量随着其厚度的增加而增加。为此,通过调节树脂层11和12的厚度比能够调节树脂芯4的变形量。
例如,树脂芯4成形为向底部展开。即,树脂芯4的截面积从树脂芯4的顶部向底部逐渐增加。
例如,上侧的第二树脂层12的底部面积大约等于下侧的第一树脂层11的顶部面积。
例如,树脂芯凸块6直线排列。
各树脂芯凸块6彼此分离地布置。
接下来,将描述根据实施例的半导体器件的制造方法。
图3A至3E是示出根据实施例的半导体器件的制造方法的系列工艺的截面图。
根据该实施例的半导体器件的制造方法包括第一至第四工艺。在第一工艺中,在其中形成电极焊盘2的衬底(半导体衬底1)上形成具有暴露电极焊盘2的开口3a的保护绝缘膜3。在第二工艺中,在保护绝缘膜3上固化后变成具有不同弹性模量的多个光敏树脂膜(例如,第一和第二光敏树脂膜21和22)。在第三工艺中,在保护绝缘膜3上,曝光、显影并固化多个光敏树脂膜以形成具有不同弹性模量的多个树脂层(例如,第一和第二树脂层11和12)的层叠结构作为凸块芯(树脂芯4)。在第四工艺中,形成导电层(互连5),使其从凸块芯的上部延伸到电极焊盘2的上部。
在下文中,将更详细地描述工艺。
首先,在半导体衬底1上形成诸如形成电路的晶体管的元件(在图中未示出),并且在半导体衬底1上形成多层互连层(图中未示出)。多层互连层在其最上层上具有电极焊盘2。
接下来,在多层互连层上形成保护绝缘膜3。保护绝缘膜3能够由氧化硅膜、氧化硅膜和氮化硅膜的层压膜、或氮化硅膜构成。
接下来,通过选择性移除保护绝缘膜3形成开口3a。开口3a被提供在电极焊盘2上,并且在开口3a处通过保护绝缘膜3暴露电极焊盘2(参见图3A)。
接下来,如图3B所示,通过旋涂方法在保护绝缘膜3和电极焊盘2上形成第一光敏树脂膜21。接下来,通过旋涂方法,在第一光敏树脂膜21上形成第二光敏树脂膜22,第二光敏树脂膜22在固化后具有与第一光敏树脂膜21的弹性模量不同的弹性模量(在该实施例的情况下第二光敏树脂膜22具有比第一光敏树脂膜21的弹性模量更小的弹性模量)。
接下来,如图3C所示,通过在通过光掩模(图中未示出)部分地曝光第一和第二光敏树脂膜21和22之后显影第一和第二光敏树脂膜21和22,在保护绝缘膜3上选择性地保留第一和第二光敏树脂膜21和22。
接下来,如图3D所示,通过热处理固化第一和第二光敏树脂膜21和22。
以该方式,在保护绝缘膜3上能够形成树脂芯4,该树脂芯4具有由第一光敏树脂膜21构成的第一树脂层11和由第二光敏树脂膜22构成的第二树脂层12的层叠结构。
接下来,如图3E所示,形成互连5,使其从树脂芯4的上部延伸到电极焊盘2的上部。
即,在利用溅射方法在树脂芯4、保护绝缘膜3和电极焊盘2上形成导电膜(例如,Au膜(图中未示出))之后,在导电膜上形成抗蚀剂图案(图中未示出)。接下来,利用该抗蚀剂图案作为掩模,通过蚀刻导电膜选择性地移除导电膜,并且以互连5的形状处理导电膜。然后,移除抗蚀剂图案。
提供在树脂芯4上的互连5的部分是与树脂芯4一起组成树脂芯凸块6的导电层5a。除了导电层5a之外的互连5的部分组成连接导电层5a和电极焊盘2的互连5b。
以该方式,能够制造半导体器件100。
接下来,将描述根据实施例的电子设备150。
图4是根据实施例的电子设备150的截面图。
根据该实施例的电子设备150包括根据该实施例的半导体器件100和具有电极152的安装衬底151。凸块芯连接到安装衬底151的电极152。
通过如图4所示地在安装衬底151上安装半导体器件100,能够制造电子设备150。
即,通过将半导体器件100的树脂芯凸块6连接到安装衬底151的电极l 52,并在安装衬底l 51上安装半导体器件100,能够电连接半导体器件100和安装衬底151。电极152例如是焊接区(land)。然而,电极152并不限于焊接区。
在安装衬底151上安装半导体器件100之后,能够将安装密封树脂(图中未示出)填充到安装衬底151和半导体器件100之间的间隙中,然后能够进行固化。
在该情况下,当半导体器件100是用于液晶显示装置的驱动器时,半导体器件100以玻璃上芯片(COG)的形式安装在对应于玻璃衬底的安装衬底151上。
替代地,半导体器件100可以安装在用作安装衬底15l的布线板上,或者以膜上芯片(COF)的形式安装在膜衬底上。
通过安装,树脂芯凸块6压靠用作外部电极的电极152,使得树脂芯凸块6被压缩并变形。
接下来,将参考图5A至7B描述安装时的树脂芯凸块6的表现。
图5A至7B示出了安装时的树脂芯凸块6的表现,并且是沿着图1的线B-B截取的截面图。在图5A至7B中,图5A至5C示出了在安装衬底151的电极152和树脂芯凸块6彼此平行的情况下的表现,图6A和6B示出了在安装衬底151的电极152翘曲的情况下的表现,并且图7A和图7B示出了在安装衬底151的电极152倾斜的情况下的表现。
首先,如图5A所示,将描述电极152平行于树脂芯凸块6的顶表面的情况。在这种情况下,如图5B和5C所示,电极152的顶表面和树脂芯凸块6的顶表面彼此平行接触,并且彼此压靠。图5B和5C中的箭头C和D示出树脂芯凸块6相对于安装衬底151的电极152的按压方向。箭头C和D的长度表示该压力的大小(较长的箭头代表较大的压力大小)。
在该实施例中,具有相对小的弹性模量(软)的第二树脂层12布置在树脂芯4的最上层。为此,通过导电层5a,第二树脂层12变形以适应电极152的形状。由此,能够获得树脂芯凸块6和电极152之间的良好贴合性。
为此,即使由于电极152或树脂芯凸块6的顶表面上存在杂质等造成表面上的翘曲、不平坦或突起,也能够获得树脂芯凸块6和电极152之间的良好贴合性。例如,如图6A所示,当电极152以凹形状翘曲时,如图6B所示,导电层5a变得具有反映电极152翘曲的翘曲,并且第二树脂层12变形以通过导电层5a顺从于电极152的形态。由此,能够获得树脂芯凸块6和电极152之间的良好贴合性。
接下来,如图7A所示,将描述电极152相对树脂芯凸块6的顶表面倾斜的情况。在这种情况下,如图7B所示,由于树脂芯凸块6压靠倾斜的电极152,所以导电层5a倾斜以顺从于电极152的形态,并且第二树脂层12变形以吸收导电层5a的倾斜。由此,能够获得树脂芯凸块6和电极152之间的良好贴合性。
即使在这种情况下,与图6A和6B的情形类似,即使由于电极152或树脂芯凸块6的顶表面上存在杂质等造成表面上翘曲、不平坦或突起,也能够获得树脂芯凸块6和电极152之间的良好贴合性。
如上所述,即使在图5A至7B的任何一种情况下,由于能够获得树脂芯凸块6和电极152之间的良好贴合性,所以能够充分确保树脂芯凸块6和电极152的接触面积,使得能够获得良好的连接性。
即使在图5A至7B的任何一种情况下,树脂芯4也没有在所有方向的侧面上均匀膨胀。为此,即使与由一层树脂制成树脂芯4的情况相比,树脂芯4没有被构造成具有小的尺寸,也能够充分确保安装密封树脂(非导电膜(NCF)或非导电浆料(NCP))的流路。因而,由于填充安装密封树脂时的流动性变得优异,所以能够抑制在安装密封树脂中产生空隙。由此,能够提高半导体器件100和安装衬底151之间的贴合性。由于树脂芯4和树脂芯凸块6能够形成为具有尽可能大的尺寸,所以能够增加树脂芯凸块6和电极152之间的电气连接面积。
接下来,将参考图8和9描述多个树脂层11和12与树脂芯4的变形特性的示例。
在图8和9中,水平轴表示树脂芯凸块6相对于安装衬底151的电极152的压力(方向是树脂芯凸块6的高度方向),并且纵轴表示变形量。
在图8和9中,曲线L1表示第一树脂层11的变形特性,曲线L2表示第二树脂层12的变形特性,并且曲线L3表示树脂芯4的变形特性。
如图8和9所示,在第一和第二树脂层11和12中,变形量线性增加直到施加恒定压力(直到变形量达到变形量的饱和点P1和P2)。然而,在施加等于或大于恒定压力的压力的范围内,变形量饱和,使得即使压力增加变形量也几乎不变化。
在这种情况下,如图8所示,在第二树脂层12达到变形量的饱和点P2之后,第一树脂层11优选地达到变形量的饱和点P1。通过适当设定第一和第二树脂层11和12的厚度,能够相互移位变形量的饱和点P1和P2。
如上所述,如果将变形量达到饱和点P1的压力设定为比变形量达到饱和点P2的压力强,如图8所示,那么树脂芯4具有在变形量达到饱和点P3之前的拐点P4的变形特性。
由此,第二树脂层12能够变形为在树脂芯4达到拐点P4期间(曲线L3中的区域R1),树脂芯凸块6和电极152充分地彼此紧密贴合。如果在树脂芯4达到拐点P4之后达到饱和点P3期间(曲线L3中的区域R2),通过压力连接树脂芯凸块6和电极152,那么相对于压力的树脂芯4的变形量能够被限制在比树脂层为一层的情况更窄的范围内。因此,通过足够的且适当的排斥力,树脂芯凸块6能够被连接到电极152。
即,在图8所示的变形特性的情况下,压靠电极152时的树脂芯凸块6的排斥力主要由第二树脂层12的弹性特性和在安装的初始步骤中扩展到侧面的树脂量确定(参见图5B)。如果树脂芯凸块6被强力地按压,那么压靠电极152时的树脂芯凸块6的排斥力主要由第一树脂层11的弹性特性和扩展到侧面的树脂量确定(参见图5C、6B和7B)。为此,在初始步骤中,树脂芯凸块6软地紧密贴合到电极152。然后,在按压步骤中,树脂芯凸块6变成为硬凸块。因此,使得元件中的凸块的变形量均匀,并且凸块的高度变化被吸收。结果,在施加到导电层5a的应力减小时,也能够稳定地进行电气连接。
如图9所示,在第一树脂层11和第二树脂层12中,变形量达到饱和点P1和P2的压力可以彼此相等。然而,在该情况下,由于曲线L3不具有拐点P4(参见图8),曲线L3的变形特性变得与树脂层为一层的情形相同。为此,树脂芯4对于压力的变形量也变为与树脂层为一层的情况的变形量相同。
然而,即使在这种情形下,与图6B和7B相类似,第二树脂层12能够变形为树脂芯凸块6和电极152彼此充分紧密贴合。并且,通过足够的适当的排斥力,树脂芯凸块6能够连接到电极152。
在上述实施例中,树脂芯凸块6的树脂芯4具有多个具有不同弹性模量的树脂层11和12的层叠结构。上侧的第二树脂层12的弹性模量比下侧的第一树脂层11的弹性模量小。为此,第二树脂层12变形以通过导电层5a适合电极152的形状。由此,能够获得树脂芯凸块6和电极152之间的良好贴合性。为此,即使由于电极152的顶表面或树脂芯凸块6上存在杂质等造成表面上的翘曲、不平坦或突起,也能够获得树脂芯凸块6和电极152之间的良好贴合性。
通过具有相对大的弹性模量的第一树脂层11的存在,树脂芯4能够被构造成具有充分的排斥力。
因此,树脂芯凸块6能够被构造成具有充分的贴合性和排斥力,并且能够提高树脂芯凸块6和电极152之间的连接性。
如果适当设定多个树脂层11和12的厚度比和平面尺寸比,那么能够容易实现针对每个产品具有不同变形量的树脂芯凸块6。因此,与树脂层为一层的情况相比,即使减少了生产线中处理的树脂的种类,也能够实现具有不同变形量的树脂芯凸块6。
在多个树脂层11和12当中,具有相对小弹性模量的第二树脂层12的变形量达到饱和点P2的压力被设定为比具有相对大弹性模量的第一树脂层11的变形量达到饱和点P1的压力弱。换句话说,在具有相对小弹性模量的第二树脂层12的变形量饱和时施加在树脂芯凸块6的压力比具有相对大弹性模量的第一树脂层11的变形量饱和时施加到树脂芯凸块6的压力弱。由此,能够实现具有响应外部压力的拐点P4(参见图8)的树脂芯4。能够容易实现具有对于安装时需要的压力的变形特性的树脂芯4。
因此,能够实现具有良好连接性的树脂芯凸块6,并且能够容易实现具有适合安装时需要的压力接触条件的弹性特性的树脂芯凸块6。
由于仅通过将具有不同弹性模量的多个树脂层11和12构造成具有层压结构能够形成树脂芯4,所以通过通常的光刻技术能够容易地形成树脂芯4。例如,由于能够通过一次光刻处理形成树脂芯4,所以能够减少工艺数目。
在该实施例中,如果多个树脂芯凸块6彼此分离地形成,则能够获得下面的效果。
首先,即使在树脂芯凸块6通过安装而按压变形的状态下,也能够充分确保安装密封树脂(NCF或NCP)的流路。因此,由于填充安装密封树脂时的流动性变为优异,所以能够抑制在安装密封树脂中产生空隙。由此,能够提高半导体器件100和安装衬底151之间的贴合性。
由于树脂芯凸块6的裾部(hem)周围不存在树脂,所以能够充分确保树脂芯凸块6被按压变形时的变形量。因此,能够稳定地执行用作外部电极的电极152和树脂芯凸块6的电气连接。
<第一改进例>
图10A和10B是示出根据第一修改的半导体器件的树脂芯凸块6的表现的截面图。
在上述实施例中,示例了树脂芯4中的上侧的树脂层的弹性模量小于下侧的树脂层的弹性模量的情况。然而,在第一修改中,树脂芯4中的下侧的树脂层11的弹性模量可以比上侧的树脂层12的弹性模量小。
在这种情况下,如图10A所示,将描述在电极152相对于树脂芯凸块6的顶表面倾斜的情况下的表现。
例如,如图10B所示,由于树脂芯凸块6压靠倾斜的电极152,因此导电层5a倾斜,以顺从于电极152的形态。由于第二树脂层12比第一树脂层11硬,所以第二树脂层12也以与导电层5a相同的方式倾斜。第一树脂层11变形以吸收导电层5a和第二树脂层12的倾斜。由此,能够获得树脂芯凸块6和电极152之间的良好的贴合性。
在这种情况下,如果上侧的树脂层12的面积小于下侧的树脂层11的面积一定程度,那么在按压时的上侧的树脂层12被埋入下侧的树脂层11时,第一和第二树脂层11和12会变形。
在第一修改中,当下侧的树脂层11的弹性模量小于与树脂层11的上侧相邻的树脂层12的弹性模量时,优选的是,树脂芯4中的上侧的树脂层12的底部面积近似等于或大于下侧的树脂层11的顶部面积。由此,能够抑制上侧的树脂层12被掩埋在下侧的树脂层11中,使得与上述实施例一样,能够获得减小树脂芯凸块6的高度变化的效果和缓和施加到导电层5a的应力的效果。
<第二修改>
图11是根据第二修改的半导体器件200的平面图,而图12是沿着图11中的线A-A截取的截面图。
在上述实施例中,示例了组成树脂芯4的树脂层为两层的情况。然而,如图11和12所示,树脂芯4可以利用三层或更多层的树脂层(例如,三层树脂层11、12和13)来构造。
即使在这种情况下,上侧的树脂层的弹性模量优选小于下侧的树脂层的弹性模量。也就是,优选的是,位于第一树脂层11的上侧的第二树脂层12的弹性模量小于第一树脂层11的弹性模量,并且位于第二树脂层12的上侧的第三树脂层13的弹性模量小于第二树脂层12的弹性模量。
然而,组成树脂芯4的树脂层的弹性模量的大小并不限于上面的示例。树脂层的弹性模量可以依赖于温度。为此,弹性模量的温度依赖性相对大的树脂层优选地被布置在中央位置,以抑制由于温度变化造成的弹性模量变化。在这种情况下,构造了下述夹层结构,其中具有相对小弹性模量和相对大的弹性模量的温度依赖性的树脂层被布置在中央位置且通过具有相对大的弹性模量和相对小的弹性模量的温度依赖性的树脂层插入。由此,能够针对温度变化保护具有相对大的弹性模量的温度依赖性的树脂层,并且能够大大减小整个树脂芯4中的弹性模量的温度依赖性。
<第三修改>
图13是根据第三修改的半导体器件300的平面图,并且图14是沿着图13中的线A-A截取的截面图。
在上述实施例中,示例了上侧的树脂层12的底部面积大约等于下侧的树脂层11的顶部面积的情况。然而,在该第三修改中,如图13和14所示,至少上侧的第二树脂层12形成为向底部扩展,并且上侧的第二树脂层12的底部面积比下侧的第一树脂层11的顶部面积小。
如上所述,树脂层11和12的变形量随着其顶部的面积的减小而增加。为此,通过利用第三修改的构造,能够获得想要的树脂层12的变形量。
通过这种构造,由于能够减小在第二树脂层被按压、变形并横向膨胀时的第二树脂层12的占用面积,所以能够容易地确保填充安装密封树脂时的流动性。
作为通过一次曝光和显影仅减小第二树脂层12的顶部面积的方法,示例了利用提高光刻中的显影速率的添加剂的方法。即,添加剂与第二光敏树脂膜22的材料混合,并且没有与第一光敏树脂膜21的材料混合,或以相对第二光敏树脂膜22的混合浓度小的浓度进行混合。
作为减小第二树脂层12的顶部面积的另一个方法,示例了调节与第一和第二光敏树脂膜21和22的材料混合的感光剂并使第二树脂层12的侧面的倾斜比第一树脂层11的倾斜更缓和(moderated)的方法。第一和第二树脂层11和12形成为向底部扩展。这在图中没有示出。然而,与第一和第二树脂层11和12的倾斜彼此相等的情况相比,减少了第二树脂层12的顶部面积,并且该侧面的倾斜变得缓和。结果,增加了第二树脂层12的变形量。
在上述实施例和修改中,示例了彼此分离地形成多个树脂芯凸块6的情况。然而,多个树脂芯凸块6可以一体地形成。即,树脂芯4可以在其裾部彼此连接。
在这种情况下,制造方法能够通过暴露第一和第二光敏树脂膜21和22以使树脂芯4的布置变得密集来实现。例如,如果在图3C的步骤中剩余的第一和第二光敏树脂膜21和22的布置是密集的,那么显影时在第一和第二光敏树脂膜21和22的边缘部分产生显影的残留物。结果,能够实现多个树脂芯4和多个树脂芯凸块6在其裾部彼此连接的结构。
每个树脂层的变形特性不限于图8或9中示出的示例。例如,弹性模量相对小的树脂层可以比弹性模量相对大的树脂层更早达到变形量的饱和点。即使在这种情况下,与组成树脂芯4的树脂层为一层的情况相比,能够提高树脂芯凸块6和电极152之间的贴合性和连接性。
显然的是,本发明并不限于上述实施例,并且在没有偏离本发明的范围和精神的情况下,可以进行修改和变化。
Claims (9)
1.一种半导体器件,包括:
电极焊盘;
保护绝缘膜,其具有构造成暴露所述电极焊盘的开口;
凸块,其包括形成在所述保护绝缘膜上的凸块芯和形成在所述凸块芯上的导电层;以及
互连,其连接所述导电层和所述电极焊盘,
其中所述凸块芯具有弹性模量不同的多个树脂层的层叠结构。
2.根据权利要求1的半导体器件,
其中所述凸块芯包括第一树脂层和第二树脂层,所述第二树脂层具有比所述第一树脂层的弹性模量小的弹性模量并且位于所述第一树脂层上方。
3.根据权利要求2的半导体器件,
其中所述第二树脂层形成为向底部扩展,并且所述第二树脂层的底部面积小于所述第一树脂层的顶部面积。
4.根据权利要求2的半导体器件,
其中所述第一和第二树脂层中的每一个形成为向底部扩展,并且所述第二树脂层的侧面的倾斜比所述第一树脂层的侧面的倾斜缓和。
5.根据权利要求1的半导体器件,
其中所述凸块芯包括第一树脂层和第二树脂层,所述第二树脂层具有比所述第一树脂层的弹性模量大的弹性模量并且位于所述第一树脂层下方。
6.根据权利要求5的半导体器件,
其中所述第二树脂层与所述第一树脂层的上层相邻,以及
所述第二树脂层的底部面积近似等于或大于所述第一树脂层的顶部面积。
7.根据权利要求1的半导体器件,
其中所述多个树脂层中具有相对小的弹性模量的所述树脂层的变形量饱和时施加到所述凸块的压力,比所述多个树脂层中具有相对大的弹性模量的所述树脂层的变形量饱和时施加到所述凸块的压力弱。
8.一种电子设备,包括:
根据权利要求1所述的半导体器件;以及
具有电极的安装衬底,
其中所述凸块连接到所述安装衬底的所述电极。
9.一种半导体器件的制造方法,包括:
在形成有电极焊盘的衬底上形成具有被构造成暴露电极焊盘的开口的保护绝缘膜;
在所述保护绝缘膜上层压固化后具有不同弹性模量的多个光敏树脂膜;
曝光、显影和固化所述多个光敏树脂膜,以在所述保护绝缘膜上形成弹性模量不同的多个树脂层的层叠结构作为凸块芯;以及
形成导电层,所述导电层从所述凸块芯的上部延伸到所述电极焊盘的上部。
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Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001189337A (ja) * | 1999-12-28 | 2001-07-10 | Matsushita Electric Ind Co Ltd | 電極バンプおよびそれを用いた半導体素子並びに半導体装置 |
US20020100961A1 (en) * | 1995-10-31 | 2002-08-01 | Joseph Fjelstad | Microelectronic package having a compliant layer with bumped protrusions |
JP2006093383A (ja) * | 2004-09-24 | 2006-04-06 | Seiko Epson Corp | 半導体装置とその製造方法、回路基板、電気光学装置および電子機器 |
US20080067663A1 (en) * | 2006-09-18 | 2008-03-20 | Tessera, Inc. | Wafer level chip package and a method of fabricating thereof |
JP2008153367A (ja) * | 2006-12-15 | 2008-07-03 | Seiko Epson Corp | 半導体装置及びその製造方法 |
JP2008205078A (ja) * | 2007-02-19 | 2008-09-04 | Seiko Epson Corp | 半導体装置及びその製造方法 |
JP2008277646A (ja) * | 2007-05-02 | 2008-11-13 | Epson Imaging Devices Corp | 電気光学装置用基板、実装構造体及び電子機器 |
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Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020100961A1 (en) * | 1995-10-31 | 2002-08-01 | Joseph Fjelstad | Microelectronic package having a compliant layer with bumped protrusions |
JP2001189337A (ja) * | 1999-12-28 | 2001-07-10 | Matsushita Electric Ind Co Ltd | 電極バンプおよびそれを用いた半導体素子並びに半導体装置 |
JP2006093383A (ja) * | 2004-09-24 | 2006-04-06 | Seiko Epson Corp | 半導体装置とその製造方法、回路基板、電気光学装置および電子機器 |
US20080067663A1 (en) * | 2006-09-18 | 2008-03-20 | Tessera, Inc. | Wafer level chip package and a method of fabricating thereof |
JP2008153367A (ja) * | 2006-12-15 | 2008-07-03 | Seiko Epson Corp | 半導体装置及びその製造方法 |
JP2008205078A (ja) * | 2007-02-19 | 2008-09-04 | Seiko Epson Corp | 半導体装置及びその製造方法 |
JP2008277646A (ja) * | 2007-05-02 | 2008-11-13 | Epson Imaging Devices Corp | 電気光学装置用基板、実装構造体及び電子機器 |
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