CN102054789B - 半导体器件和制造半导体器件的方法 - Google Patents

半导体器件和制造半导体器件的方法 Download PDF

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Publication number
CN102054789B
CN102054789B CN201010516547.9A CN201010516547A CN102054789B CN 102054789 B CN102054789 B CN 102054789B CN 201010516547 A CN201010516547 A CN 201010516547A CN 102054789 B CN102054789 B CN 102054789B
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resin layer
projection
semiconductor device
insulating resin
core
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Expired - Fee Related
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CN201010516547.9A
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CN102054789A (zh
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别宫史浩
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Renesas Electronics Corp
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Renesas Electronics Corp
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Abstract

本发明涉及半导体器件和制造半导体器件的方法。半导体器件包括保护绝缘膜、被形成在保护绝缘膜中的开口、位于开口内的电极焊盘、被形成在保护绝缘膜上的凸块、以及互连。凸块包括凸块核和导电膜。凸块核包括绝缘树脂层和位于绝缘树脂层上的导电树脂层。导电膜至少被形成在凸块核的上表面上。互连连接凸块的导电膜和电极焊盘。

Description

半导体器件和制造半导体器件的方法
相关申请的交叉应用
本申请基于日本专利申请No.2009-246813，通过引用，将其内容合并于此。
技术领域
本发明涉及具有凸块的半导体器件和制造半导体器件的方法，在所述凸块中，导电膜被形成在树脂构成的凸块核上。
背景技术
凸块被形成在半导体器件中以将半导体器件安装在安装板上。被包括在半导体器件中的电路通过此凸块被连接至诸如安装板的焊接区(land)的电极上。近年来，已经开发如下的技术，在其中凸块的核由树脂形成，并且通过将导电膜形成在此核上来形成凸块。
例如，日本未经审查的专利公开No.2007-201106公布一种技术，该技术用于分散形成凸块核的树脂中的导电金属颗粒。根据此技术，已知即使当在导电膜中产生裂痕或者细缝时，也能够抑制凸块和电极之间的电气连接的可靠性的降低。
通过在日本未经审查的专利公开No.2007-201106中公开的技术，导电金属颗粒被分散在整个凸块核中。另一方面，可能存在下述情况，其中当凸块相互接触时，则凸块核的下部将相互连接。在这样的情况下，当导电金属颗粒被分散到整个凸块核中时，彼此相邻的凸块通过凸块核被短路。
发明内容
在一个实施例中，提供了一种半导体器件，包括：保护绝缘膜；开口，该开口被形成在保护绝缘膜中；电极焊盘，该电极焊盘位于开口中；凸块，该凸块被形成在保护绝缘膜上方，包括凸块核和被形成在凸块核上方的导电膜；以及互连，该互连连接凸块的导电膜和电极焊盘，其中，凸块核包括绝缘树脂层，和位于绝缘树脂层上方的导电树脂层。
在其中在形成凸块的导电膜中产生裂痕的位置是位于凸块核的上部的部分，例如，该位置可以是位于凸块核的侧面和上表面之间的边界的区域处的部分。根据本发明，凸块核具有在其中导电树脂层被层压在绝缘树脂层上的构造。即，通过导电树脂层来形成凸块核的上部。为此，即使当在导电膜中存在裂痕时，通过由凸块核中的导电树脂层形成的部分来确保凸块的电气可靠性。另外，即使当相邻的凸块的凸块核的下部被形成而相互连接，通过绝缘树脂层形成凸块核的下部，其导致抑制相邻的凸块的电气短路。因此，根据本发明，在相邻的凸块之间没有短路的情况下能够使凸块节距变得更窄，同时抑制凸块的电气可靠性的降低。
在另一实施例中，提供一种制造半导体器件的方法，包括在衬底中形成凸块，该衬底包括绝缘膜、被形成在保护绝缘膜中的开口、以及从开口暴露的电极焊盘，该方法包括：在保护绝缘膜上方形成绝缘树脂层；在绝缘树脂层上方形成导电树脂层；通过选择性地移除绝缘树脂层和导电树脂层的层压膜形成凸块核；以及通过在凸块核、保护绝缘膜以及电极焊盘的上方选择性地形成导电膜，来形成凸块和将凸块连接到电极焊盘的互连。
根据本发明，在具有带有凸块核的凸块的半导体器件中，在相邻的凸块之间没有短路的情况下能够使凸块节距变得更窄，同时抑制凸块的电气可靠性的降低。
附图说明
结合附图，根据某些优选实施例的以下描述，本发明的以上和其它方面、优点和特征将更加明显，在附图中：
图1A和图1B是示出根据第一实施例的制造半导体器件的方法的横截面图；
图2A和图2B是示出根据第一实施例的制造半导体器件的方法的横截面图；
图3A和图3B是示出根据第一实施例的制造半导体器件的方法的横截面图；
图4是图3A中所示的半导体器件的平面图；
图5是沿着图4的线B-B’截取的横截面图；
图6是用于解释第一实施例的操作和效果的图；
图7是示出根据第二实施例的半导体器件的构造的平面图；以及
图8是沿着图7的线B-B’截取的横截面图。
具体实施方式
现在在此将参考示例性实施例来描述本发明。本领域的技术人员将会理解能够使用本发明的教导完成许多可替选的实施例，并且本发明不限于为解释性目的而示出的实施例。
在下文中，将会参考附图来描述本发明的实施例。在所有的附图中，通过相同的附图标记来表示相同的元件，并且将不会重复其描述。
图1A至图3B是根据第一实施例的制造半导体器件的方法的横截面图。制造半导体器件的方法包括在衬底100中形成凸块的工艺，所述半导体器件具有保护绝缘膜120；被形成在保护绝缘膜120中的开口122；以及从开口122暴露的电极焊盘130。具体地，首先，绝缘树脂层212被形成在保护绝缘膜120上。接下来，导电树脂层214被形成在绝缘树脂层212上。接下来，通过选择性地移除绝缘树脂层212和导电树脂层214的层压膜来形成凸块核210。接下来，通过在凸块核210、保护绝缘膜120、以及电极焊盘130上选择性地形成导电膜来形成凸块200和互连230。互连230将凸块200连接至电极焊盘130。在下文中，将会给出详细的描述。
首先，如图1A中所示，诸如晶体管的元件(未示出)被形成在的衬底100上，并且多层的互连层110被进一步形成在衬底100上。电极焊盘130被形成在位于多层的互连层110的最上边的层的互连层中。接下来，保护绝缘层120被形成在多层的互连层110上。接下来，通过选择性地移除保护绝缘膜120来形成开口122。开口122位于电极焊盘130上，并且从保护绝缘膜120暴露电极焊盘130。
接下来，如图1B中所示，绝缘树脂层212被形成在保护绝缘膜120和电极焊盘130上。例如，绝缘树脂层212是由诸如酚醛树脂、环氧树脂、聚酰亚胺树脂、氨基树脂、不饱合聚脂树脂、硅树脂、或者烯丙基树脂的热固性树脂、或者诸如有机硅基树脂或者酰亚胺基树脂的光固性树脂形成。
接下来，导电树脂层214被形成在绝缘树脂层212上。导电树脂层214具有在其中例如颗粒的导电粉末被混合在绝缘基材中的构造。例如，导电树脂层212的基材是由诸如酚醛树脂、环氧树脂、聚酰亚胺树脂、氨基树脂、不饱合聚脂树脂、硅树脂、或者烯丙基树脂的热固性树脂、或者诸如有机硅基树脂或者酰亚胺基树脂的光固性树脂形成。优选的是，导电树脂层214的基材与形成绝缘树脂层212的树脂是相同的树脂。
接下来，如图2A中所示，绝缘树脂层212和导电树脂层214被曝光并且显影。因此，绝缘树脂层212和导电树脂层214被选择性地移除，并且以岛状保留在保护绝缘膜120上。
同时，导电树脂层214具有在其中例如金属粉的导电粉末被混合在感光树脂中的构造。如图2A中所示，在进行选择性移除之后的状态下，在平面图中看到的导电树脂层214的面积小于绝缘树脂层212的面积。为了获得此构造，例如，存在调节光敏剂、溶液、以及各层的树脂的添加剂的类型和数量的方法。当导电树脂层214的面积小于绝缘树脂层212的面积时，能够在形成稍后描述的导电膜220的时提高相对于凸块核210的导电膜的涂覆性能(coatability)。然而，导电树脂层214的面积可能与绝缘树脂层212的面积相同。
接下来，如图2B中所示，绝缘树脂层212和导电树脂层214被固化。此工艺是当树脂层212和导电树脂层214是热固性树脂时，对绝缘树脂层212和导电树脂层214进行热处理的工艺；和当绝缘树脂层212和导电树脂层214是光固性树脂时，通过光照射绝缘树脂层212和导电树脂层214的工艺。因此，凸块核210被形成在保护绝缘膜120上。通过绝缘树脂层212和导电树脂层214形成凸块核210。
同时，能够通过调整制造条件来使绝缘树脂层212的侧面比凸块核210中的导电树脂层214的侧面更加陡峭。
接下来，如图3A中所示，例如，通过溅射方法，将例如Au膜的导电膜形成在凸块核210、保护绝缘膜120、以及电极焊盘130上。接下来，抗蚀图案(未示出)被形成在导电膜上，并且使用抗蚀图案作为掩模来蚀刻导电膜。因此，选择性地移除导电膜，并且形成用于形成凸块200的导电膜220和互连230。凸块200具有在其中导电膜220被形成在凸块核210上的构造。互连230被从凸块200的导电膜220伸展到保护绝缘膜120，并且将凸块200的导电膜220连接到电极焊盘130。然后，抗蚀图案被移除。
由此形成的半导体器件包括保护绝缘膜120、被形成在保护绝缘膜120中的开口122、位于开口122内的电极焊盘130、被形成在保护绝缘膜120上的凸块200、以及互连230。凸块200包括凸块核210和导电膜220。凸块核210包括绝缘树脂层212，和位于绝缘树脂层212上的导电树脂层214。导电膜220至少被形成在凸块核210的上表面上。互连230连接凸块200的导电膜220和电极焊盘130。
在此状态下，优选的是，导电树脂层214的厚度等于或者大于导电膜220的厚度。另外，优选的是，导电树脂层214的厚度等于或者小于凸块核210的高度h1(参见图5)的90％。将会描述这些理由。
存在如下的高可能性，即，因为安装时的按压和由此造成的树脂变形的应力，所以在凸块200的顶部下面的导电膜20中可能产生裂痕。为了有效地补偿在安装时产生的裂痕，优选的是，导电树脂层214的厚度至少是凸块200的顶部的附近中的导电膜220的厚度。
另外，考虑避免在安装时由于凸块核210的膨胀而导致彼此相邻的凸块200的短路，优选的是，导电树脂层214的厚度等于或者小于凸块核210的高度h1的90％。同时，可能存在下述情况，例如，由于安装压力或者树脂的膨胀特性，有必要使导电树脂层214的厚度变小，以将其厚度设置为等于或者少于凸块核210的高度h1的50％。
然后，如图3B中所示，执行半导体器件的覆晶薄膜(COF)安装或者玻璃上芯片(COG)安装。当半导体器件是液晶驱动器时，安装板300是玻璃衬底。在此状态下，半导体器件的凸块200被连接至安装板300的电极310。例如，电极310是焊接区，但是不限于焊接区。
图4是图3A中所示的半导体器件的平面图，并且图5是沿着图4的线B-B’截取的横截面图。同时，图3A是沿着图4中的线A-A’截取的横截面图。如图4和图5中所示，沿着第一方向(附图中的垂直方向)布置多个凸块200。在不同于第一方向的第二方向中，例如，与第一方向垂直的方向(附图中的水平方向)伸展互连230。相互分离多个凸块200，但是将其相互靠近地布置。另外，在凸块核210的各侧面当中，凸块200的导电膜220没有被形成在沿着上述第一方向的部分中。然而，在这些侧面当中，导电膜220可以被形成在通过导电树脂层214形成的区域中。
接下来，将会参考图6描述实施例的操作和效果。当图3A和图3B中所示的半导体器件被安装时，在形成凸块200的导电膜220中，在位于凸块核210的上部上，例如，位于凸块核210的侧面和上表面之间的边界的区域中的部分容易地产生裂痕232。另一方面，在实施例中，通过导电树脂层214形成凸块核210的上部。为此，即使当在导电膜220中产生裂痕232时，位于导电膜220中的凸块核210的上表面上的部分和互连230通过导电树脂层214被相互电气的连接。因此，凸块200的电气可靠性没有被降低。
另外，通过绝缘树脂层212形成凸块核210的下部。为此，即使当多个凸块200被相互靠近地布置，并且在形成凸块核210时相邻的凸块核210在下部相互连接时，彼此相邻的凸块200之间通过凸块核210的电气连接被得以抑制。
另外，当用作导电树脂层214的基材的树脂与绝缘树脂层212的相同时，使用一个掩模能够执行同时曝光，从而允许抑制半导体器件的制造成本的增加。
图7是示出根据第二实施例的半导体器件的构造的平面图，并且图8是沿着图7的B-B’截取的横截面图。图7中的线A-A’的横截面与第一实施例的图3A和图3B中所示的相同。
根据实施例的半导体器件与根据第一实施例的半导体器件相同，不同之处在于多个凸块200彼此靠近，并且至少凸块210的绝缘树脂层212的下部被相互连接。另外，制造此半导体器件的方法与第一实施例的相同。
在实施例中，导电树脂层214的厚度等于或者大于导电膜220的厚度。另外，优选的是，基于相邻的凸块核210的分离点，导电树脂层214的厚度等于或者小于凸块核210的顶部的高度h2的90％。
在所述实施例中，还能够获得与第一实施例相同的效果。另外，由于能够彼此靠近布置多个凸块200，所以半导体器件能够变小。
如上所述，尽管参考附图已经提出本发明的实施例，但是它们仅用于示出本发明，并且能够采用除了上述之外的各种构造。
显然的是，本发明不限于上面的实施例，但是在不脱离本发明的范围和精神的情况下可以进行修改和变化。

Claims (7)

1.一种半导体器件，包括：
保护绝缘膜；
开口，所述开口被形成在所述保护绝缘膜中；
电极焊盘，所述电极焊盘位于所述开口中；
凸块，所述凸块被形成在所述保护绝缘膜上方，包括凸块核和被形成在所述凸块核上方的导电膜；以及
互连，所述互连连接所述凸块的所述导电膜和所述电极焊盘，
其中，所述凸块核包括绝缘树脂层，和位于所述导电膜和所述绝缘树脂层之间的导电树脂层，以及
其中，从平面图来看，所述导电树脂层的面积窄于所述绝缘树脂层的面积。
2.如权利要求1所述的半导体器件，
其中，沿着第一方向布置多个所述凸块，
所述互连从所述凸块伸展到不同于所述第一方向的第二方向，并且
所述多个凸块核被构成为使得形成所述凸块核的所述绝缘树脂层的至少下部相互连接。
3.如权利要求1所述的半导体器件，
其中，通过在绝缘树脂中混合导电粉末，使得所述导电树脂层具有导电性。
4.如权利要求3所述的半导体器件，
其中，形成所述导电树脂层的所述绝缘树脂与形成所述绝缘树脂层的树脂相同。
5.一种制造半导体器件的方法，包括在衬底中形成凸块，所述衬底包括保护绝缘膜、被形成在所述保护绝缘膜中的开口、以及从所述开口暴露的电极焊盘，所述方法包括：
在所述保护绝缘膜上方形成绝缘树脂层；
在所述绝缘树脂层上方形成导电树脂层；
通过选择性地移除所述绝缘树脂层和所述导电树脂层的层压膜，形成凸块核；以及
通过在所述凸块核、所述保护绝缘膜以及所述电极焊盘的上方选择性地形成导电膜，来形成所述凸块和将所述凸块连接到所述电极焊盘的互连。
6.如权利要求5所述的制造半导体器件的方法，
其中，所述绝缘树脂层和所述导电树脂层具有感光性，并且
所述形成凸块核的步骤包括曝光并且显影所述层压膜。
7.如权利要求6所述的制造半导体器件的方法，
其中，通过在形成所述绝缘树脂层的绝缘且感光的树脂中混合导电粉末，使得所述导电树脂层具有导电性。
CN201010516547.9A 2009-10-27 2010-10-20 半导体器件和制造半导体器件的方法 Expired - Fee Related CN102054789B (zh)

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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5683942A (en) * 1994-05-25 1997-11-04 Nec Corporation Method for manufacturing bump leaded film carrier type semiconductor device

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4813129A (en) * 1987-06-19 1989-03-21 Hewlett-Packard Company Interconnect structure for PC boards and integrated circuits
US6284563B1 (en) * 1995-10-31 2001-09-04 Tessera, Inc. Method of making compliant microelectronic assemblies
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JP4221606B2 (ja) * 2005-06-28 2009-02-12 セイコーエプソン株式会社 半導体装置の製造方法
JP4714593B2 (ja) 2006-01-25 2011-06-29 富士通株式会社 半導体素子接続バンプ及び半導体装置

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5683942A (en) * 1994-05-25 1997-11-04 Nec Corporation Method for manufacturing bump leaded film carrier type semiconductor device

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* Cited by examiner, † Cited by third party
Title
JP特开2006-93383A 2006.04.06 *

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