CN102097364B - 硬掩模材料 - Google Patents

硬掩模材料 Download PDF

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Publication number
CN102097364B
CN102097364B CN201010569747.0A CN201010569747A CN102097364B CN 102097364 B CN102097364 B CN 102097364B CN 201010569747 A CN201010569747 A CN 201010569747A CN 102097364 B CN102097364 B CN 102097364B
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CN
China
Prior art keywords
hard mask
film
plasma
deposition
sublayer
Prior art date
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Active
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CN201010569747.0A
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English (en)
Chinese (zh)
Other versions
CN102097364A (zh
Inventor
维什瓦纳坦·兰加拉扬
乔治·安德鲁·安东内利
阿南达·班纳吉
巴尔特·范施拉文迪杰克
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ASM Nutool Inc
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ASM Nutool Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US12/631,709 external-priority patent/US8178443B2/en
Priority claimed from US12/631,691 external-priority patent/US8247332B2/en
Application filed by ASM Nutool Inc filed Critical ASM Nutool Inc
Priority to CN201510566292.XA priority Critical patent/CN105185707B/zh
Publication of CN102097364A publication Critical patent/CN102097364A/zh
Application granted granted Critical
Publication of CN102097364B publication Critical patent/CN102097364B/zh
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Formation Of Insulating Films (AREA)
  • Chemical Vapour Deposition (AREA)
  • Drying Of Semiconductors (AREA)
  • Electrodes Of Semiconductors (AREA)
CN201010569747.0A 2009-12-04 2010-11-30 硬掩模材料 Active CN102097364B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201510566292.XA CN105185707B (zh) 2009-12-04 2010-11-30 硬掩模材料、其形成方法和设备及其用途

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US12/631,709 US8178443B2 (en) 2009-12-04 2009-12-04 Hardmask materials
US12/631,709 2009-12-04
US12/631,691 2009-12-04
US12/631,691 US8247332B2 (en) 2009-12-04 2009-12-04 Hardmask materials

Related Child Applications (1)

Application Number Title Priority Date Filing Date
CN201510566292.XA Division CN105185707B (zh) 2009-12-04 2010-11-30 硬掩模材料、其形成方法和设备及其用途

Publications (2)

Publication Number Publication Date
CN102097364A CN102097364A (zh) 2011-06-15
CN102097364B true CN102097364B (zh) 2015-10-14

Family

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Family Applications (2)

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CN201010569747.0A Active CN102097364B (zh) 2009-12-04 2010-11-30 硬掩模材料
CN201510566292.XA Active CN105185707B (zh) 2009-12-04 2010-11-30 硬掩模材料、其形成方法和设备及其用途

Family Applications After (1)

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CN201510566292.XA Active CN105185707B (zh) 2009-12-04 2010-11-30 硬掩模材料、其形成方法和设备及其用途

Country Status (4)

Country Link
JP (1) JP5656010B2 (ja)
KR (2) KR101798235B1 (ja)
CN (2) CN102097364B (ja)
TW (2) TWI547997B (ja)

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JP5860734B2 (ja) * 2012-03-13 2016-02-16 株式会社ライテック研究所 硬質皮膜被覆部材およびその製造方法
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JP2014078579A (ja) * 2012-10-10 2014-05-01 Renesas Electronics Corp 半導体装置の製造方法
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JP6111097B2 (ja) * 2013-03-12 2017-04-05 株式会社日立国際電気 半導体装置の製造方法、基板処理装置およびプログラム
JP6111106B2 (ja) * 2013-03-19 2017-04-05 株式会社日立国際電気 半導体装置の製造方法、基板処理装置およびプログラム
US10767259B2 (en) 2013-07-19 2020-09-08 Agilent Technologies, Inc. Components with an atomic layer deposition coating and methods of producing the same
US20150024152A1 (en) * 2013-07-19 2015-01-22 Agilent Technologies, Inc. Metal components with inert vapor phase coating on internal surfaces
CN104947085B (zh) * 2014-03-31 2017-12-19 中芯国际集成电路制造(上海)有限公司 掩膜的沉积方法、掩膜及半导体器件的刻蚀方法
US20160314964A1 (en) 2015-04-21 2016-10-27 Lam Research Corporation Gap fill using carbon-based films
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KR102130459B1 (ko) * 2016-02-29 2020-07-07 가부시키가이샤 코쿠사이 엘렉트릭 반도체 장치의 제조 방법, 기판 처리 장치 및 프로그램
US9870915B1 (en) * 2016-10-01 2018-01-16 Applied Materials, Inc. Chemical modification of hardmask films for enhanced etching and selective removal
KR102084296B1 (ko) 2016-12-15 2020-03-03 도쿄엘렉트론가부시키가이샤 성막 방법, 붕소 막 및 성막 장치
US9837270B1 (en) * 2016-12-16 2017-12-05 Lam Research Corporation Densification of silicon carbide film using remote plasma treatment
JP6914143B2 (ja) * 2016-12-26 2021-08-04 東京エレクトロン株式会社 基板処理方法、基板処理装置、基板処理システム、基板処理システムの制御装置および半導体基板の製造方法
KR102020211B1 (ko) * 2017-01-09 2019-11-04 주식회사 테스 탄소 및/또는 보론를 포함하는 비정질 실리콘막의 형성 방법
CN110249410B (zh) * 2017-02-01 2023-07-04 应用材料公司 用于硬掩模应用的硼掺杂碳化钨
JP6914107B2 (ja) * 2017-06-05 2021-08-04 東京エレクトロン株式会社 ボロン膜の除去方法
CN107742607B (zh) * 2017-08-31 2021-05-11 重庆中科渝芯电子有限公司 一种用icp干法刻蚀制作薄膜电阻的方法
US10474027B2 (en) * 2017-11-13 2019-11-12 Macronix International Co., Ltd. Method for forming an aligned mask
JP7049883B2 (ja) * 2018-03-28 2022-04-07 東京エレクトロン株式会社 ボロン系膜の成膜方法および成膜装置
GB201813467D0 (en) * 2018-08-17 2018-10-03 Spts Technologies Ltd Method of depositing silicon nitride
CN113195786A (zh) 2018-10-19 2021-07-30 朗姆研究公司 用于间隙填充的远程氢等离子体暴露以及掺杂或未掺杂硅碳化物沉积
TW202111147A (zh) * 2019-08-12 2021-03-16 美商應用材料股份有限公司 低k介電膜
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Also Published As

Publication number Publication date
TW201543574A (zh) 2015-11-16
JP2011139033A (ja) 2011-07-14
TWI547997B (zh) 2016-09-01
KR101907802B1 (ko) 2018-12-05
TW201130050A (en) 2011-09-01
CN102097364A (zh) 2011-06-15
KR101798235B1 (ko) 2017-11-15
KR20110063386A (ko) 2011-06-10
CN105185707A (zh) 2015-12-23
JP5656010B2 (ja) 2015-01-21
TWI505364B (zh) 2015-10-21
KR20170126827A (ko) 2017-11-20
CN105185707B (zh) 2018-06-01

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