CN102077340A - 减少半导体器件中在通孔图案化期间的金属盖层的侵蚀的方法 - Google Patents

减少半导体器件中在通孔图案化期间的金属盖层的侵蚀的方法 Download PDF

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Publication number
CN102077340A
CN102077340A CN200980125491XA CN200980125491A CN102077340A CN 102077340 A CN102077340 A CN 102077340A CN 200980125491X A CN200980125491X A CN 200980125491XA CN 200980125491 A CN200980125491 A CN 200980125491A CN 102077340 A CN102077340 A CN 102077340A
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CN
China
Prior art keywords
layer
conductive cap
etch
cap layer
semiconductor device
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Pending
Application number
CN200980125491XA
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English (en)
Chinese (zh)
Inventor
C·巴尔奇
D·费希尔
M·沙勒
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Priority claimed from PCT/US2009/002631 external-priority patent/WO2009134386A1/en
Publication of CN102077340A publication Critical patent/CN102077340A/zh
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/034—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics bottomless barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/077—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers on sidewalls or on top surfaces of conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/083—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts the openings being via holes penetrating underlying conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
CN200980125491XA 2008-04-30 2009-04-30 减少半导体器件中在通孔图案化期间的金属盖层的侵蚀的方法 Pending CN102077340A (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
DE102008021568.6 2008-04-30
DE102008021568A DE102008021568B3 (de) 2008-04-30 2008-04-30 Verfahren zum Reduzieren der Erosion einer Metalldeckschicht während einer Kontaktlochstrukturierung in Halbleiterbauelementen und Halbleiterbauelement mit einem schützenden Material zum Reduzieren der Erosion der Metalldeckschicht
US12/397,661 2009-03-04
US12/397,661 US7986040B2 (en) 2008-04-30 2009-03-04 Method of reducing erosion of a metal cap layer during via patterning in semiconductor devices
PCT/US2009/002631 WO2009134386A1 (en) 2008-04-30 2009-04-30 Method of reducing erosion of a metal cap layer during via patterning in semiconductor devices

Publications (1)

Publication Number Publication Date
CN102077340A true CN102077340A (zh) 2011-05-25

Family

ID=41256569

Family Applications (1)

Application Number Title Priority Date Filing Date
CN200980125491XA Pending CN102077340A (zh) 2008-04-30 2009-04-30 减少半导体器件中在通孔图案化期间的金属盖层的侵蚀的方法

Country Status (6)

Country Link
US (2) US7986040B2 (https=)
JP (1) JP2011519487A (https=)
KR (1) KR101557906B1 (https=)
CN (1) CN102077340A (https=)
DE (1) DE102008021568B3 (https=)
TW (1) TW201001552A (https=)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106067417A (zh) * 2015-04-20 2016-11-02 东京毅力科创株式会社 蚀刻有机膜的方法
CN107492506A (zh) * 2016-06-12 2017-12-19 中芯国际集成电路制造(上海)有限公司 半导体结构及形成方法
CN113517395A (zh) * 2021-04-15 2021-10-19 长江先进存储产业创新中心有限责任公司 相变存储器的制备方法、制备的控制方法以及相变存储器

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102005004409B4 (de) * 2005-01-31 2011-01-20 Advanced Micro Devices, Inc., Sunnyvale Technik zur Erhöhung der Prozessflexibilität während der Herstellung von Kontaktdurchführungen und Gräben in Zwischenschichtdielektrika mit kleinem ε
DE102008049775B4 (de) 2008-09-30 2018-08-09 Globalfoundries Inc. Herstellungsverfahren einer Metalldeckschicht mit besserer Ätzwiderstandsfähigkeit für kupferbasierte Metallgebiete in Halbleiterbauelementen
US8164190B2 (en) * 2009-06-25 2012-04-24 International Business Machines Corporation Structure of power grid for semiconductor devices and method of making the same
US8637395B2 (en) * 2009-11-16 2014-01-28 International Business Machines Corporation Methods for photo-patternable low-k (PPLK) integration with curing after pattern transfer
US8691687B2 (en) * 2010-01-07 2014-04-08 International Business Machines Corporation Superfilled metal contact vias for semiconductor devices
US8586472B2 (en) 2010-07-14 2013-11-19 Infineon Technologies Ag Conductive lines and pads and method of manufacturing thereof
DE102012210480B4 (de) * 2012-06-21 2024-05-08 Robert Bosch Gmbh Verfahren zum Herstellen eines Bauelements mit einer elektrischen Durchkontaktierung
US9627256B2 (en) * 2013-02-27 2017-04-18 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit interconnects and methods of making same
DE102013104464B4 (de) * 2013-03-15 2019-08-29 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleiterstruktur
US10032712B2 (en) 2013-03-15 2018-07-24 Taiwan Semiconductor Manufacturing Company Limited Semiconductor structure
JP5873145B2 (ja) * 2014-07-08 2016-03-01 株式会社フジクラ 貫通配線基板の製造方法
US10211052B1 (en) * 2017-09-22 2019-02-19 Lam Research Corporation Systems and methods for fabrication of a redistribution layer to avoid etching of the layer
US10276794B1 (en) 2017-10-31 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Memory device and fabrication method thereof
US11069526B2 (en) * 2018-06-27 2021-07-20 Taiwan Semiconductor Manufacturing Co., Ltd. Using a self-assembly layer to facilitate selective formation of an etching stop layer
US11854870B2 (en) * 2021-08-30 2023-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Etch method for interconnect structure
KR20230118409A (ko) 2022-02-04 2023-08-11 삼성전자주식회사 반도체 장치 및 이를 포함하는 데이터 저장 시스템

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6380075B1 (en) * 2000-09-29 2002-04-30 International Business Machines Corporation Method for forming an open-bottom liner for a conductor in an electronic structure and device formed
JP2002176099A (ja) * 2000-12-08 2002-06-21 Nec Corp 半導体装置及びその製造方法
US6756672B1 (en) * 2001-02-06 2004-06-29 Advanced Micro Devices, Inc. Use of sic for preventing copper contamination of low-k dielectric layers
US6831018B2 (en) * 2001-08-21 2004-12-14 Matsushita Electric Industrial Co., Ltd. Method for fabricating semiconductor device
JP4198906B2 (ja) * 2001-11-15 2008-12-17 株式会社ルネサステクノロジ 半導体装置および半導体装置の製造方法
JP2003160877A (ja) * 2001-11-28 2003-06-06 Hitachi Ltd 半導体装置の製造方法および製造装置
US6528409B1 (en) * 2002-04-29 2003-03-04 Advanced Micro Devices, Inc. Interconnect structure formed in porous dielectric material with minimized degradation and electromigration
US7026714B2 (en) * 2003-03-18 2006-04-11 Cunningham James A Copper interconnect systems which use conductive, metal-based cap layers
JP2007042662A (ja) * 2003-10-20 2007-02-15 Renesas Technology Corp 半導体装置
US7365001B2 (en) * 2003-12-16 2008-04-29 International Business Machines Corporation Interconnect structures and methods of making thereof
US6949457B1 (en) * 2004-01-21 2005-09-27 Kla-Tencor Technologies Corporation Barrier enhancement
US7259463B2 (en) * 2004-12-03 2007-08-21 Taiwan Semiconductor Manufacturing Company, Ltd. Damascene interconnect structure with cap layer
JP2006210508A (ja) * 2005-01-26 2006-08-10 Sony Corp 半導体装置およびその製造方法
JP2006324584A (ja) * 2005-05-20 2006-11-30 Sharp Corp 半導体装置およびその製造方法
KR100640662B1 (ko) * 2005-08-06 2006-11-01 삼성전자주식회사 장벽금속 스페이서를 구비하는 반도체 소자 및 그 제조방법
DE102005046975A1 (de) * 2005-09-30 2007-04-05 Advanced Micro Devices, Inc., Sunnyvale Technik zur Herstellung einer kupferbasierten Metallisierungsschicht mit einer leitenden Deckschicht
KR100660915B1 (ko) * 2006-02-03 2006-12-26 삼성전자주식회사 반도체 소자의 배선 형성 방법

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106067417A (zh) * 2015-04-20 2016-11-02 东京毅力科创株式会社 蚀刻有机膜的方法
CN106067417B (zh) * 2015-04-20 2019-09-03 东京毅力科创株式会社 蚀刻有机膜的方法
CN107492506A (zh) * 2016-06-12 2017-12-19 中芯国际集成电路制造(上海)有限公司 半导体结构及形成方法
CN107492506B (zh) * 2016-06-12 2020-01-03 中芯国际集成电路制造(上海)有限公司 半导体结构及形成方法
CN113517395A (zh) * 2021-04-15 2021-10-19 长江先进存储产业创新中心有限责任公司 相变存储器的制备方法、制备的控制方法以及相变存储器

Also Published As

Publication number Publication date
KR20110003562A (ko) 2011-01-12
JP2011519487A (ja) 2011-07-07
US8338293B2 (en) 2012-12-25
TW201001552A (en) 2010-01-01
US20120003832A1 (en) 2012-01-05
DE102008021568B3 (de) 2010-02-04
KR101557906B1 (ko) 2015-10-06
US20090273086A1 (en) 2009-11-05
US7986040B2 (en) 2011-07-26

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Application publication date: 20110525