CN102074559A - SiP系统集成级IC芯片封装件及其制作方法 - Google Patents

SiP系统集成级IC芯片封装件及其制作方法 Download PDF

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Publication number
CN102074559A
CN102074559A CN2010105613047A CN201010561304A CN102074559A CN 102074559 A CN102074559 A CN 102074559A CN 2010105613047 A CN2010105613047 A CN 2010105613047A CN 201010561304 A CN201010561304 A CN 201010561304A CN 102074559 A CN102074559 A CN 102074559A
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Prior art keywords
chip
attenuate
substrate
adopt
sip
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CN2010105613047A
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CN102074559B (zh
Inventor
谢建友
李习周
慕蔚
王永忠
魏海东
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Tianshui Huatian Technology Co Ltd
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Tianshui Huatian Technology Co Ltd
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Priority to CN2010105613047A priority Critical patent/CN102074559B/zh
Priority to PCT/CN2010/080520 priority patent/WO2012068762A1/zh
Priority to US13/883,143 priority patent/US9349615B2/en
Publication of CN102074559A publication Critical patent/CN102074559A/zh
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Abstract

SiP系统集成级IC芯片封装件及制作方法，包括基板，基板上设置有无源器件和两个IC芯片，该两个IC芯片与基板之间分别设置有胶片膜，IC芯片通过键合线与基板上面的第一焊盘连接，基板上覆盖有塑封体。其中一个IC芯片的上面还可以设置第三IC芯片，该第三IC芯片通过键合线分别与第一焊盘和三IC芯片下面的IC芯片相连。采用SMTPAD开窗方式的基板，在基板上进行贴片，经回流焊、清洗、上芯、等离子清洗、压焊、打印、切割和包装，制得SiP系统集成级IC芯片封装件。本发明封装件集成了不同类型的器件，具有完整的系统功能，可作为进一步开发SoC的中间环节。

Description

SiP系统集成级IC芯片封装件及其制作方法
技术领域
本发明属于集成电路封装技术领域，涉及一种SiP系统集成级IC芯片封装件，使电路封装从单芯片级进入系统集成级。本发明还涉及一种该SiP系统集成级IC芯片封装件的制作方法。
背景技术
电子产品的小型化和多功能化，特别是计算机、通讯等便携式产品持续不断的需求，对集成电路提出了新的要求，并要求在芯片上实现系统的功能。由于集成电路设计水平和工艺技术的提高，集成电路规模越来越大，已可以将整个系统集成为一个芯片。一段时间以来，从设计的角度出发，能将整个系统集成为一个芯片的主要是芯片系统（SoC），但一项SoC设计需要高达18个月的时间和巨大的一次性工程费用（NRE费用），影响到SoC的广泛应用。而一项在基板上组装一块或多块裸片、再加上若干分离式和被动组件的系统级封装（SiP）设计，可能只需要6到9个月的时间。通过垂直集成，SiP也可以缩短互连距离，缩短信号延迟时间、降低噪音并减少电容效应，使信号速度更快，功率消耗也较低。有时，SiP作为进一步开发SoC的中间环节，最终将全部内容合并到一个硅芯片上。这一点特别是在蓝牙设备、手机、汽车电子、成像和显示产品、数码相机和电源中确定无疑。SiP切合这些应用的封装需要，与传统的IC封装相比，通常最多可节约80%的资产，并将重量降低90%。其中的一个关键原因是采用了表面贴装技术（SMT）。SiP技术将电子制造服务（EMS）的SMT和半导体装配服务（SAS）融合为一体。SiP通过将存储器和逻辑芯片堆叠在一起满足众多应用的需求。但现有SiP封装件中封装的器件的功能单一，而且只能封装同一类型的器件，造成封装的系统功能不完整。
发明内容
本发明的目的是提供一种SiP系统集成级封装件，集成了存储芯片、CPU、加密芯片和解码芯片，具有完整的系统功能，可作为进一步开发SoC的中间环节。
本发明的另一目的是提供一种上述集成级封装件的制作方法。
为实现上述目的，本发明所采用的技术方案是，SiP系统集成级IC芯片封装件，包括基板1，基板1上设置有无源器件和两个IC芯片，该两个IC芯片与基板1之间分别设置有胶片膜，IC芯片通过键合线与基板1上面的第一焊盘6相连接，基板1上覆盖有塑封体13。
本发明所采用的另一技术方案是，一种上述SiP系统集成级IC芯片封装件的制作方法，按以下步骤进行：
步骤1：晶圆减薄
当晶圆减薄要求厚度小于等于160μm时，采用PG300RM减薄机和现有减薄工艺对晶圆进行减薄，然后，取规格为230mm×100m、厚度为200μm的 CP9021B-200专用减薄胶膜，采用现有粗磨、细磨和抛光工艺对该专用减薄胶膜的表面进行磨制，使专用减薄胶膜的表面粗糙度为0.05μm～0.12μm，将磨制后的专用减薄胶膜粘贴到减薄的晶圆表面；   
当晶圆减薄要求厚度大于160μm时，采用PG300RM减薄机和现有减薄工艺对晶圆进行减薄，然后，取规格为230mm×100m、厚度为150μm 的BT-150E-KL减薄胶膜，采用现有工艺对该减薄胶膜的表面进行磨制，使减薄胶膜的表面粗糙度为0.05μm～0.12μm，将磨制后的减薄胶膜粘贴到晶圆减薄的芯片的表面；
步骤2：当晶圆的减薄厚度小于等于160μm时，用DFD3350双刀划片机划片，划片后烘烤；
当晶圆的减薄厚度大于160μm时，采用DAD6340普通划片机划片，划片后烘烤；
步骤3：取采用SMT PAD开窗方式的基板，该基板规格为0201：非焊窗定义型垫结构，0402: 焊窗定义型垫结构，使用XPf-s贴片机，在基板上的相关焊盘上印刷锡膏，然后按器件外形从小到大的顺序，将无源器件粘贴在已印锡膏的焊盘上，然后，将贴片后的基板送入Pyramax 回流焊炉进行回流焊，回流温度为230℃～250℃，回流焊时间为30s～50s；
采用 BL-370清洗剂对回流焊后的基板进行清洗，去除助焊剂残渣，清洗时，传送速度0.45m/min，清洗温度35～45℃，清洗后在40～50℃温度下烘干；
步骤4：将步骤2中划片后的晶圆放入上芯机工作室；将步骤3清洗后的基板送到上料台，夹上粘片胶管，在显微镜下观察，并旋转调整芯片位置，使用配备写胶系统在芯片粘贴位置划胶，采用现有多顶针系统多步顶起系统，在芯片顶起的同时，将芯片放置在基板的粘片位置上；
步骤5：采用现有方法步骤4上芯后的基板进行等离子清洗；
步骤6：取键合线，采用芯片打到芯片技术和跨芯片打线技术进行压焊，同时对键合线弧度进行DOE优化，线弧高度控制在100μm～150μm；
采用ESEC3100焊线机进行压焊；
步骤7：取线膨胀系a1≤1、粘度≥8000cp、流动性80cm～120cm的塑封料，采用带真空吸附的全自动塑封系统对步骤6压焊后的基板进行塑封，塑封时应用现有的多段注射防翘曲软件控制技术控制冲丝、翘曲和离层；在后固化过程中，采用防翘曲专用固化夹具夹紧塑封后的胶体，在175℃±10℃温度下，后固化4小时～7小时，制成SiP系统级集成封装整条半成品。塑封料采用市售的CEL9250塑封料和市售的EME EF0324906塑封料；
步骤8：用LMK-54打印设备在步骤7制成的SiP系统级集成封装整条半成品上印字；
步骤9：用AE公司的MWM-850贴膜设备在步骤9印字后的SiP系统级集成封装整条半成品表面贴膜；然后，采用DISCO公司的 AD3350切割设备对表面贴膜后的SiP系统级集成封装整条半成品进行切割；之后，用DISCO公司的DCS1440清洗设备进行清洗；用AE公司的UV-956照射设备进行UV照射；捡拾分选；最后，用离子风机进行风干；
步骤10：采用普通封装件的防静电真空包装工艺进行包装，制得SiP系统级集成级IC芯片封装件。
本发明集成级封装件的制作方法是基于SoC的一种新型封装技术，将一个或多个裸芯片及无源元件构成的高性能模块装载在一个封装外壳内，具备一个系统的功能。缩短了设计时间，只需要6到9个月的时间。通过垂直集成，缩短互连距离，缩短信号延迟时间、降低噪音并减少电容效应，使信号速度更快，降低了功率消耗。
附图说明
图1是本发明多芯片封装件实施例的结构示意图。
图2是本发明堆叠封装件实施例的结构示意图。
图中，1.基板，2.第一胶膜片，3.第一IC芯片，4.第二胶膜片，5.第二ＩＣ芯片，6.第一焊盘，7.第一键合线，8.第一无源器件，9.第二无源器件，10.第三无源器件，11.第四无源器件，12.第二焊盘，13.塑封体，14.第三IC芯片，15.第三胶膜片，16.第二键合线，17.焊球，18.第三键合线，19.第四键合线。
具体实施方式
下面结合附图和具体实施方式对本发明进行详细说明。
SiP是IC产业链发展中的知识、技术、方法相互渗透交融，综合应用的结果，能最大限度地灵活利用各种不同芯片资源和封装互连优势，尽可能地提高性能，降低成本，在做深做透的研发过程中涉及到多种技术问题，相关技术包括热设计，I/O口的重分布，减薄大规模IC芯片的背面厚度，若干芯片的层叠组装和高密集互连技术等。
SiP将多个IC和无源元件封装在高性能基板上，可方便地兼容不同制造技术的芯片，从而使封装由单芯片级进人系统集成级。SiP实际上就是一系统级的多芯片封装（MCP），封装效率极大提高。SiP将微处理器或数字信号处理器与各种存储器堆叠封装，可作为微系统独立运行。.
如图1所示，本发明多芯片封装件实施例的结构，包括基板1，基板1的下面并排设置有两第二焊盘12，基板1上并排设置有第一IC芯片3和第二IC芯片5，基板1上还设置有第一无源器件8、第二无源器件9、第三无源器件10和第四无源器件11；第一IC芯片3与基板1之间设置有第一胶片膜2，第二IC芯片5与基板1之间设置有第二胶片膜4；第一IC芯片3的两侧的基板1上分别设置有第一焊盘6，第二IC芯片5两侧的基板1上也分别设置有第一焊盘6；第一IC芯片3上焊接有多根第一键合线7，该多根第一键合线7的一端与第一IC芯片3固接，该多根第一键合线7的另一端分别与位于第一IC芯片3两侧的第一焊盘6焊接。第二IC芯片5上也焊接有多根第一键合线7，该多根键合线7的一端与第二IC芯片5固接，该多根第一键合线7的另一端分别与位于第二IC芯片5两侧的第一焊盘6焊接；基板1上覆盖有塑封体13，塑封体13包围了基板1的上表面及该表面上设置的所有器件。
如图2所示，本发明堆叠封装件实施例的结构，包括基板1，基板1的下面并排设置有两第二焊盘12；基板1上并排设置有第一IC芯片3和第二IC芯片5；基板1上还分别设置有第一无源器件8、第二无源器件9、第三无源器件10和第四无源器件11；第一IC芯片3与基板1之间设置有第一胶片膜2，第二IC芯片5与基板1之间设置有第二胶片膜4；第二IC芯片5的上面设置有第三IC芯片14，第三IC芯片14与第二IC芯片5之间设置有第三胶片膜15。第一IC芯片3的两侧的基板1上分别设置有第一焊盘6，第二IC芯片5两侧的基板1上也分别设置有第一焊盘6；第一IC芯片3上焊接有多根第一键合线7，该多根第一键合线7的一端与第一IC芯片3固接，该多根第一键合线7的另一端分别与位于第一IC芯片3两侧的第一焊盘6焊接。第二IC芯片5上也焊接有多根第一键合线7，该多根键合线7的一端与第二IC芯片5固接，该多根第一键合线7的另一端分别与位于第二IC芯片5两侧的第一焊盘6焊接；第二IC芯片5上设置有焊球17；第三IC芯片14上分别设置有多根第三键合线16和多根第四键合线19，第三键合线16的一端与第三IC芯片14固接，第三键合线16的另一端与第二IC芯片5一侧的第一焊盘6焊接，第四键合线19的一端与第三IC芯片14固接，第四键合线19的另一端与焊球17焊接。基板1上覆盖有塑封体13，塑封体13包围了基板1的上表面及该表面上所有的器件。
第一键合线3、第二键合线5、第三键合线16和第四键合线19均采用金线或铜线。
第一胶片膜2、第二胶片膜4和第三胶片膜15均采用DAF膜。
塑封体13对IC芯片、键合线和基板1起到保护和支撑作用。
IC芯片、键合线、基板1、第二焊盘12和无源器件构成电源和信号通道。
胶片膜、键合线、第一焊盘6，第二焊盘12以及焊球17形成电路整体。
本发明还提供了一种上述封装件的制作方法，具体按以下步骤进行：
步骤1：晶圆减薄
当晶圆减薄要求厚度小于等于160μm时，采用PG300RM减薄机和现有减薄工艺对晶圆进行减薄，然后，取规格为230mm×100m、厚度为200μm的 CP9021B-200专用减薄胶膜，采用现有粗磨、细磨和抛光工艺对该专用减薄胶膜的表面进行磨制，使专用减薄胶膜的表面粗糙度为0.05μm～0.12μm，将磨制后的专用减薄胶膜粘贴到减薄的晶圆表面；   
当晶圆减薄要求厚度大于160μm时，采用PG300RM减薄机和现有减薄工艺对晶圆进行减薄，然后，取规格为230mm×100m、厚度为150μm 的BT-150E-KL减薄胶膜，采用现有工艺对该减薄胶膜的表面进行磨制，使减薄胶膜的表面粗糙度为0.05μm～0.12μm，将磨制后的减薄胶膜粘贴到减薄的晶圆表面。
步骤2：划片
根据步骤1中晶圆减薄要求的的厚度，对步骤1中粘贴减薄胶膜的晶圆进行划片：
当该晶圆的减薄厚度小于等于160μm时，用DFD3350双刀划片机划片，防止碎片，划片后烘烤，烘箱型号为ESPEC；
当该晶圆的减薄厚度大于160μm时，采用DAD6340普通划片机划片，划片后烘烤，烘箱型号为ESPEC。
步骤3：表面贴装及回流焊
其流程为：印刷焊料→贴片→回流→收料→清洗
先在基板上贴元件的相关焊盘上印刷上锡膏，然后按器件外形从小到大的顺序，将无源器件粘贴在已印锡膏的焊盘上，贴完全部无源器件后，将贴片后的基板送入Pyramax 回流焊炉进行回流焊，回流温度为230～250℃，回流焊时间为30～50s；基板采用SMT PAD开窗方式，其规格为0201：非焊窗定义型（non-Solder mask define）垫结构，0402: 焊窗定义型（ Solder mask define）垫结构；
锡膏采用SENJU生产的规格为96.5SN 3AG 0.5CU的锡膏。
电阻规格为R0201 4.7K,5%,0.05W；R0201  10K,5%,0.05W； R0402  10K,1%,0.05W；
电容规格为C0201 100nf±10%/10Ⅴ；
使用XPf-s贴片机，
将回流焊后的基板进行清洗，去除多余的助焊剂残渣，清洗时采用 BL-370清洗剂，传送速度0.45m/min，清洗温度35～45℃，清洗后在40～50℃温度下烘干。
步骤4：将步骤2中划片后的晶圆放入上芯机工作室，关好门；将步骤3中清洗后的基板送到上料台，夹上粘片胶（导电胶或绝缘胶）管，选用合适的点胶头，将划片后的晶圆放置于晶圆工作台上，在显微镜下观察，并旋转调整该晶圆位置，使用配备写胶系统（根据芯片尺寸和粘片胶粘度不同选择写胶头的大小，写胶图案也和芯片形状尺寸有关）在晶圆粘贴位置划胶，采用现有多顶针系统多步顶起系统，在晶圆顶起的同时，将晶圆准确对位放置在基板的粘片位置上；
将步骤2中划片后的晶圆放入上芯机工作室，关好门；将步骤3中清洗后的基板送到上料台，夹上粘片胶（导电胶或绝缘胶）管，选用合适的点胶头，将划片后的晶圆放置于晶圆工作台上，在显微镜下观察，并旋转调整该晶圆位置，使用配备写胶系统（根据芯片尺寸和粘片胶粘度不同选择写胶头的大小，写胶图案也和芯片形状尺寸有关）在晶圆粘贴位置划胶，采用现有多顶针系统多步顶起系统，在晶圆顶起的同时，将晶圆准确对位放置在基板的粘片位置上；使用DB-700FL或ESEC 2008hs3 plus上芯机，将已贴下层芯片的基板进行预热，预热温度150℃，设备机械手吸取1只带胶膜片的IC芯片，自动对准放置到下层芯片上的粘片位置，粘完一片自动传送到收料的引线传递盒，采用同样方法粘完本批全部上层芯片；将粘完上层芯片的引线传递盒送烘烤，使用ESPEC烘箱在150℃下，采用防离层烘烤工艺烘烤3小时；
当芯片尺寸大于6mm×6mm时，上芯过程中会出现芯片错位、芯片压伤、溢胶量不良等问题，通过控制出胶量，保证粘片胶溢出量；调整检测头位置解决芯片错位；控制机械手升降高度防止芯片压伤；
上芯时，选用DB-700FL或ESEC 2008hs3 plus上芯机；选用线性膨胀系数a1≤1、粘度≥8000cp的低应力环保导电胶；
另外，SiP封装设计DOE试验优化工艺条件，在芯片与载体尺寸比例相近时，对银浆溢出量及粘片精度有了更高的要求。
步骤5：采用现有方法及VSP-88D Prol等离子清洗机对步骤4上芯后的基板进行清洗。
步骤6：根据具体封装件焊盘和焊线尺寸选择适合的劈刀，键合线直径可以在Φ18μm、Φ20μm、Φ23μm、Φ25μm、Φ30μm、Φ33μm、Φ38μm、Φ50μm中任意选择进行压焊；
多芯片叠层结构中，首先，在上层芯片与下层芯片间采用高低弧焊线，其次在下层芯片与第一焊盘6间采用平弧或M弧焊线，最后在上层芯片与第一焊盘6间采用BGA弧焊线；
大跨度、远距离的弧线在芯片上方布线是非常必要的技术，采用跨芯片技术，有效提高布线和封装密度；
在此工序为了得到更好的电性能参数，采用芯片打到芯片的技术、跨芯片打线技术，芯片与芯片之间通过金线连接，有效减少线长，缩小封装区域；同时通过线弧优化，避免die to die的特殊线弧发生塌陷、短路等现象。由于键合线间距小，封装过程中很容易造成金线偏移引起短路问题，对金线弧度参数进行DOE优化，把线弧高度控制在100μm～150μm以内，弧形选用最优的弧形增强线弧强度，提高金线抗弯强度，
使用ESEC3100焊线机。
步骤7：取线膨胀系a1≤1、粘度≥8000cp、流动性80cm～120cm的塑封料，对步骤6压焊后的基板进行塑封，塑封时采用带真空吸附的全自动塑封系统，真空吸附框架，同时应用现有的多段注射防翘曲软件控制技术，解决塑封过程中的冲丝、翘曲和离层；在后固化过程中，采用防翘曲专用固化夹具夹紧塑封后的胶体，在175℃±10℃温度下，后固化4～7小时，制成SiP系统级集成封装整条半成品；
塑封料采用市售的CEL9250塑封料和市售的EME EF0324906塑封料；
SiP封装是单面封装，一面为塑封料，另一面是基板，由于不是对等封装，封装体内材料的不一致，在塑封时由于热的膨胀系数的不同和收缩率不同，在受到温度变化后胶体发生翘曲。塑封时采用多段注射防翘曲软件控制的防翘曲工艺，可以将翘曲度控制在工艺范围内，同时在后固化过程中用专用的固化夹具矫正，并且用严格的升温、降温程序，避免温度变化剧烈造成翘曲。经过严格的控制程序控制翘曲度0.15mm（smile）、0.10mm（cry），满足切割工艺要求；
塑封空洞是高密度封装中的缺陷问题之一，本发明在12×18mm的封装体中，放置22颗器件，三个芯片，所有器件与模流方向垂直，器件间距超小，并通过封装设计优化，采用多段注塑模型软件控制工艺使塑封参数优化，上模抽真空等技术，消除了空洞。
步骤8：采用专用打印夹具固定步骤7制成SiP系统级集成封装整条半成品，用LMK-54打印设备在该半成品上印字，然后，使用专用检测夹具进行检验；
用LMK-54打印设备进行印字时，先做打印模版，再调试印章位置，可以单只移动印章，解决了现有技术中因材质较差存在变形及断裂现象，检测夹具制作精度不够的打印难问题。原来的检测夹具四个印章开了一个窗口，这样的设计弊端为：其一，制作一个印章大小很难控制；其次，印章位置及印章之间步距调试难度很大；其三，夹具方格变形非常严重断裂部分很多，夹具精度很差，调试一条产品位置所花费的时间在一个半小时左右。
步骤9：切割
用AE公司的MWM-850贴膜设备在步骤9印字后的SiP系统级集成封装整条半成品表面贴膜；然后，采用DISCO公司的 AD3350切割设备对表面贴膜后的SiP系统级集成封装整条半成品进行切割；之后，用DISCO公司的DCS1440清洗设备进行清洗；用AE公司的UV-956照射设备进行UV照射；捡拾分选；最后，用离子风机进行风干；
贴膜选用FC-217M-170UV胶膜；
切割后产品表面有少许铜粉粘附在管脚或散热片表面，会造成产品表面有异物，生产时会造成引脚间的短路。因此，加大切割过程中的进刀速度，尽可能减少切割后污水在产品上的停留时间，切割完成后及时清洗；选用二流体清洗机并优化清洗程序参数设置，提高清洗质量；切割过程中必须选择正确的切割顺序，避免2条料条在切割过程中相互受切割污水污染；
外形尺寸小的封装件工艺加工后容易出现飞芯现象，解决的措施之一是通过选择粘性强的胶膜增强产品在胶膜上的粘结强度；其二是通过控制料条的翘曲度，改善贴片工艺使产品能和UV膜粘结紧密，不能出现气泡、砂眼等；
另外，外形尺寸小的封装件在切割过程容易发生切现象，解决的措施：其一，选择CSP校准模式并选用多点校准功能；其二，通过编程改变切割顺序命令，从而改变不同位置的径向受力减小产品位移。
步骤10：包装
采用普通封装件的防静电真空包装工艺。
本发明制作方法的创新点在以下几方面可以得到很好的体现。
关键信号的差分阻抗控制技术；大片敷铜时采取了void设计，有效释放塑封、高温流程的应力。并且在基板设计中采用很小的器件，可以优化压焊第二焊点；集成了存储芯片、CPU、加密和解码芯片，具有完整的系统功能；高密度封装中的3D结构及布局，防止SMT污染第二焊点；以及多芯片技术和叠加技术的混合应用。在工艺上，采用高密度、低节距下的锡膏印刷技术，高密度、低节距组装元器件贴装技术，以及高温回流焊技术。超薄芯片的上芯，高密度封装中上芯污染问题，采用等离子清洗技术的解决。在压焊中，采用芯片打芯片技术，通过掌握跨芯片技术，跨芯片打线，解决高密度、交叉弧线碰线问题，有效提高布线和封装密度。芯片叠加结构中，采用了芯片打到芯片的技术、跨芯片打线技术；超短弧线、超低弧线技术的研发，解决了上下层芯片间的焊线问题，并且在基板设计中，已考虑了芯片叠加结构中，打线可采取备份和复用技术，即上层芯片既可以通过芯片打芯片技术直接通过金线连接，也可以通过金手指在基板上连接，保证了生产的可靠性和工艺的灵活性。在高密度封装中，采用多段注塑模型软件控制工艺及大片敷铜是采用void设计，有效释放塑封、高温流程的应力，解决了高密度塑封中的紊流、空洞和翘曲问题。无源器件集成的方式：其放置与金线保持近似平行关系，有效降低了塑封冲线率。芯片和芯片之间信号交流通过三种方式同时进行：金线直接连接，金线到基板走线到金线连接，金线到基板走线后再到无源器件再到金线连接。基板的芯片粘接区大面积敷铜，上芯过程中通过使用含有金属成分的粘结剂，加强芯片散热。
实施例1
晶圆减薄要求厚度小于等于160μm，采用PG300RM减薄机和现有减薄工艺对芯片进行晶圆减薄，并取规格为230mm×100m、厚度为200μm的 CP9021B-200专用减薄胶膜，采用粗磨、细磨和抛光工艺对该专用减薄胶膜的表面进行磨制，使其表面粗糙度为0.05μm～0.12μm，将磨制后的专用减薄胶膜粘贴到晶圆减薄芯片的表面；采用DFD3350双刀划片机进行划片，并防止碎片，划片后用ESPEC烘箱烘烤；取采用SMT PAD开窗方式的基板，其规格为0201：non-Solder mask define，0402: Solder mask define；用SENJU生产的96.5SN 3AG 0.5CU锡膏，分别去规格为R0201 4.7K,5%,0.05W的电阻、R0201 10K,5%,0.05W的电阻；R0402 10K,1%,0.05W的电阻和规格为C0201 100nf±10%/10Ⅴ的电容，使用XPf-s贴片机在基板上贴器件的相关焊盘上印刷锡膏，然后按器件外形从小到大的顺序自动吸取无源器件放置在已印锡膏的焊盘上，贴完全部无源器件后，将贴片后的基板送入Pyramax 回流焊炉，在230℃回流温度下回流焊30s；采用 BL-370清洗剂对回流焊后的芯片进行清洗，去除多余的助焊剂残渣，清洗时的传送速度0.45m/min，清洗温度35℃，并在40℃温度下烘干。将划片后的晶圆框架放入DB-700FL上芯机工作室，关好门；将已贴无源器件的基板送到上料台，夹上导电胶管，上芯机将晶圆片抓取放置于晶圆工作台上，在显微镜下观察，旋转调整芯片位置，使用加注线性膨胀系数a1≤1、粘度≥8000cp的低应力环保导电胶的写胶系统，在芯片粘贴位置划胶，采用现有多顶针系统多步顶起系统，在芯片顶起的同时，机械手抓取芯片准确对位放置在基板的粘片位置上，进行贴片，等离子清洗上芯后的基板；根据具体封装件焊盘和焊线尺寸选择劈刀，选用直径为Φ18μm的金线，采用ESEC3100焊线机进行压焊，控制金线弧度为100μm ~150μm；取CEL9250塑封料，对压焊后的基板进行塑封，塑封时采用超薄型封装防翘曲工艺、现有的多段注射防翘曲软件控制技术和上模抽真空技术，防止冲丝、翘曲离层和塑封空洞；采用现有防翘曲专用固化夹具夹紧塑封后的胶体，在175℃温度下，后固化7小时。采用LMK-54打印设备进行打印。贴膜用AE公司的MWM-850设备；切割用DISCO公司的 AD3350；清洗用DISCO公司的DCS1440；UV照射用AE公司的UV-956；捡拾分选用SIMCO公司；AEROTAT  XC（离子风机）设备。UV胶膜：FC-217M-170；切割过程中加大切割过程进刀速度，减少切割后污水在的停留时间，切割完成后及时清洗；选用二流体清洗机并优化清洗程序参数设置，提高清洗质量；切割过程中必须选择正确的切割顺序，避免2条料条在切割过程中相互受切割污水污染；采用普通封装件的防静电真空包装工艺进行包装；制成SiP系统级集成封装件。
实施例2
晶圆减薄要求厚度大于160μm，采用PG300RM减薄机和现有减薄工艺对芯片进行晶圆减薄，并取规格为230mm×100m、厚度为200μm的BT-150E-KL专用减薄胶膜，采用现有工艺对该专用减薄胶膜的表面进行磨制，使其表面粗糙度为0.05μm～0.12μm，将磨制后的专用减薄胶膜粘贴到晶圆减薄芯片的表面；采用DAD6340划片机进行划片，防止碎片，划片后用ESPEC烘箱烘烤；取采用SMT PAD开窗方式的基板，其规格为0201：non-Solder mask define，0402: Solder mask define；用SENJU生产的96.5SN 3AG 0.5CU锡膏，分别去规格为R0201 4.7K,5%,0.05W的电阻、R0201 10K,5%,0.05W的电阻；R0402 10K,1%,0.05W的电阻和规格为C0201 100nf±10%/10Ⅴ的电容，使用XPf-s贴片机在基板上贴器件的相关焊盘上印刷锡膏，然后按器件外形从小到大的顺序自动吸取无源器件放置在已印锡膏的焊盘上，贴完全部无源器件后，将贴片后的基板送入Pyramax 回流焊炉，在250℃回流温度下回流焊50s；采用 BL-370清洗剂对回流焊后的芯片进行清洗，去除多余的助焊剂残渣，清洗时的传送速度0.45m/min，清洗温度45℃，并在50℃温度下烘干。将划片后的晶圆框架放入ESEC 2008hs3 plus上芯机工作室，关好门；将已贴无源器件的基板送到上料台，夹上绝缘胶管，上芯机将晶圆片抓取放置于晶圆工作台上，在显微镜下观察，旋转调整芯片位置，使用加注线性膨胀系数a1≤1、粘度≥8000cp的低应力环保导电胶的写胶系统，在芯片粘贴位置划胶，采用现有多顶针系统多步顶起系统，在芯片顶起的同时，机械手抓取芯片准确对位放置在基板的粘片位置上，进行贴片，等离子清洗贴片后的基板；根据具体封装件焊盘和焊线尺寸选择劈刀，选用直径为Φ50μm的金线，采用ESEC3100焊线机进行压焊，控制金线弧度为100μm～150μm；取EME EF0324906塑封料，对压焊后的基板进行塑封，塑封时采用超薄型封装防翘曲工艺、现有的多段注射防翘曲软件控制技术和上模抽真空技术，防止冲丝、翘曲离层和塑封空洞；采用现有防翘曲专用固化夹具夹紧塑封后的胶体，在185℃温度下，后固化4小时。采用LMK-54打印设备进行打印。贴膜用AE公司的MWM-850设备；切割用DISCO公司的 AD3350；清洗用DISCO公司的DCS1440；UV照射用AE公司的UV-956；捡拾分选用SIMCO公司；AEROTAT  XC（离子风机）设备。UV胶膜：FC-217M-170；切割过程中加大切割过程进刀速度，减少切割后污水在的停留时间，切割完成后及时清洗；选用二流体清洗机并优化清洗程序参数设置，提高清洗质量；切割过程中必须选择正确的切割顺序，避免2条料条在切割过程中相互受切割污水污染；采用普通封装件的防静电真空包装工艺进行包装；制成SiP系统级集成封装件。
实施例3
多层堆叠封装中，下层芯片晶圆减薄到厚度为100μm～150μm，上层芯片晶圆减薄到厚度为75μm～120μm，减薄机具备8″～12″超薄减薄抛光功能，采用防翘曲薄减薄抛光工艺；采用同实施例1的方法进行贴膜、划片、贴片和回流焊，回流焊后的清洗温度为40℃，并在45℃的温度下烘干，按实施例1的方法进行一次上芯，使用DB-700FL上芯机，将已贴下层芯片的基板预热到150℃，设备机械手吸取1只带胶膜片的IC芯片，自动对准放置到下层芯片上的粘片位置，粘完一片自动传送到收料的引线传递盒，采用同样方法粘完本批全部上层芯片；将粘完上层芯片的引线传递盒送烘烤，使用ESPEC烘箱在150℃下，采用防离层烘烤工艺烘烤3小时；然后采用与实施例1相同的方法进行等离子清洗；先在上层芯片与下层芯片间采用高低弧焊线，其次在下层芯片与第一焊盘6间采用平弧焊线，最后在上层芯片与第一焊盘6间采用BGA弧焊线；对完成键合线焊接的基板进行塑封，塑封时应用多段注射防翘曲软件控制技术和DOE试验优选工艺控制冲丝、翘曲和离层，然后，在165℃的温度下，后固化5.5小时，制成SiP系统级集成封装整条半成品；采用实施例1的方法进行后续工序，制成SiP系统级集成封装件。

Claims (6)

1.SiP系统集成级IC芯片封装件，其特征在于，包括基板（1），基板（1）上设置有无源器件和两个IC芯片，该两个IC芯片与基板（1）之间分别设置有胶片膜，IC芯片通过键合线与基板（1）上面的第一焊盘（6）相连接，基板（1）上覆盖有塑封体（13）。
2.按照权利要求1所述的SiP系统集成级IC芯片封装件，其特征在于，所述的胶片膜采用DAF膜。
3.一种权利要求1所述SiP系统集成级IC芯片封装件的制作方法，其特征在于，该方法按以下步骤进行：
步骤1：晶圆减薄
当晶圆减薄要求厚度小于等于160μm时，采用PG300RM减薄机和现有减薄工艺对晶圆进行减薄，然后，取规格为230mm×100m、厚度为200μm的 CP9021B-200专用减薄胶膜，采用现有粗磨、细磨和抛光工艺对该专用减薄胶膜的表面进行磨制，使专用减薄胶膜的表面粗糙度为0.05μm～0.12μm，将磨制后的专用减薄胶膜粘贴到减薄的晶圆表面；   
当晶圆减薄要求厚度大于160μm时，采用PG300RM减薄机和现有减薄工艺对晶圆进行减薄，然后，取规格为230mm×100m、厚度为150μm 的BT-150E-KL减薄胶膜，采用现有工艺对该减薄胶膜的表面进行磨制，使减薄胶膜的表面粗糙度为0.05μm～0.12μm，将磨制后的减薄胶膜粘贴到晶圆减薄的芯片的表面；
步骤2：当晶圆的减薄厚度小于等于160μm时，用DFD3350双刀划片机划片，划片后烘烤；
当晶圆的减薄厚度大于160μm时，采用DAD6340普通划片机划片，划片后烘烤；
步骤3：取采用SMT PAD开窗方式的基板，该基板规格为0201：非焊窗定义型垫结构，0402: 焊窗定义型垫结构，使用XPf-s贴片机，在基板上的相关焊盘上印刷锡膏，然后按器件外形从小到大的顺序，将无源器件粘贴在已印锡膏的焊盘上，然后，将贴片后的基板送入Pyramax 回流焊炉进行回流焊，回流温度为230℃～250℃，回流焊时间为30s～50s；
采用 BL-370清洗剂对回流焊后的基板进行清洗，去除助焊剂残渣，清洗时，传送速度0.45m/min，清洗温度35～45℃，清洗后在40～50℃温度下烘干；
步骤4：将步骤2中划片后的晶圆放入上芯机工作室；将步骤3清洗后的基板送到上料台，夹上粘片胶管，在显微镜下观察，并旋转调整芯片位置，使用配备写胶系统在芯片粘贴位置划胶，采用现有多顶针系统多步顶起系统，在芯片顶起的同时，将芯片放置在基板的粘片位置上；
步骤5：采用现有方法步骤4上芯后的基板进行等离子清洗；
步骤6：取键合线，采用芯片打到芯片技术和跨芯片打线技术进行压焊，同时对键合线弧度进行DOE优化，线弧高度控制在100μm～150μm；
采用ESEC3100焊线机进行压焊；
步骤7：取线膨胀系a1≤1、粘度≥8000cp、流动性80cm～120cm的塑封料，采用带真空吸附的全自动塑封系统对步骤6压焊后的基板进行塑封，塑封时应用现有的多段注射防翘曲软件控制技术控制冲丝、翘曲和离层；在后固化过程中，采用防翘曲专用固化夹具夹紧塑封后的胶体，在175℃±10℃温度下，后固化4小时～7小时，制成SiP系统级集成封装整条半成品；
塑封料采用市售的CEL9250塑封料和市售的EME EF0324906塑封料；
步骤8：用LMK-54打印设备在步骤7制成的SiP系统级集成封装整条半成品上印字；
步骤9：用AE公司的MWM-850贴膜设备在步骤9印字后的SiP系统级集成封装整条半成品表面贴膜；然后，采用DISCO公司的 AD3350切割设备对表面贴膜后的SiP系统级集成封装整条半成品进行切割；之后，用DISCO公司的DCS1440清洗设备进行清洗；用AE公司的UV-956照射设备进行UV照射；捡拾分选；最后，用离子风机进行风干；
步骤10：采用普通封装件的防静电真空包装工艺进行包装，制得SiP系统级集成级IC芯片封装件。
4.SiP系统集成级IC芯片封装件，其特征在于，包括基板（1），基板（1）上设置有无源器件和两个IC芯片，该两个IC芯片与基板（1）之间分别设置有胶片膜，该两个IC芯片通过键合线与基板（1）上面的第一焊盘（6）相连接，该两个IC芯片中的一个IC芯片上面还设置有第三个IC芯片，该第三个IC芯片与其下面的IC芯片之间设置有胶片膜，该第三个IC芯片通分别通过键合线与第一焊盘（6）和第三个IC芯片下面的IC芯片相连接，基板（1）上覆盖有塑封体（13）。
5.按照权利要求4所述的SiP系统集成级IC芯片封装件，其特征在于，所述胶片膜采用DAF膜。
6.一种权利要求4所述SiP系统集成级IC芯片封装件的制作方法，其特征在于，该方法按以下步骤进行：
步骤1：当晶圆减薄要求厚度小于等于160μm时，采用PG300RM减薄机和现有减薄工艺对芯片晶圆进行减薄，然后，取规格为230mm×100m、厚度为200μm的 CP9021B-200专用减薄胶膜，采用现有粗磨、细磨和抛光工艺对该专用减薄胶膜的表面进行磨制，使专用减薄胶膜的表面粗糙度为0.05μm～0.12μm，将磨制后的专用减薄胶膜粘贴到晶圆减薄芯片的表面；   
当晶圆减薄要求厚度大于160μm时，采用PG300RM减薄机和现有减薄工艺对芯片晶圆进行减薄，然后，取规格为230mm×100m、厚度为150μm 的BT-150E-KL减薄胶膜，采用现有工艺对该减薄胶膜的表面进行磨制，使减薄胶膜的表面粗糙度为0.05μm～0.12μm，将磨制后的减薄胶膜粘贴到晶圆减薄的芯片的表面；
步骤2：当晶圆的减薄厚度小于等于160μm时，用DFD3350双刀划片机划片，划片后烘烤；
当晶圆的减薄厚度大于160μm时，采用DAD6340普通划片机划片，划片后烘烤；
步骤3：取采用SMT PAD开窗方式的基板，该基板的规格为0201：非焊窗定义型垫结构，0402: 焊窗定义型垫结构；使用XPf-s贴片机，在基板上的相关焊盘上印刷上锡膏，然后按器件外形从小到大的顺序，将无源器件粘贴在已印锡膏的焊盘上，将贴片后的基板送入Pyramax 回流焊炉进行回流焊，回流温度为230～250℃，回流焊时间为30～50s；基板采用；
采用 BL-370清洗剂对回流焊后的基板进行清洗，去除多余的助焊剂残渣，清洗时的传送速度0.45m/min，清洗温度35～45℃，清洗后在40～50℃温度下烘干；
步骤4：将步骤2中划片后的晶圆放入上芯机工作室，将步骤3中清洗后的基板夹上粘片胶管，在显微镜下观察，并旋转调整芯片位置，使用配备写胶系统在芯片粘贴位置划胶，采用现有多顶针系统多步顶起系统，在芯片顶起的同时，将芯片放置在基板的粘片位置上；将已贴下层芯片的基板预热至150℃，上芯机将1只带胶膜片的IC芯片，自动对准放置到下层芯片上的粘片位置，粘完一片自动传送到收料的引线传递盒，采用同样方法粘完本批全部上层芯片；将粘完上层芯片的引线传递盒在150℃温度下采用防离层烘烤工艺烘烤3小时；
步骤5：采用现有方法及VSP-88D Prol等离子清洗机对步骤4上芯后的基板进行清洗；
步骤6：使用ESEC3100焊线机，采用芯片打到芯片的技术和跨芯片打线技术机压焊键合线，首先在上层芯片与下层芯片间采用高低弧焊线，其次在下层芯片与基板上的焊盘间采用平弧或M弧焊线，最后在上层芯片与基板上的焊盘间采用BGA弧焊线，压焊过程中对键合线弧度参数进行DOE优化，将键合线线弧高度控制在100μm～150μm；
步骤7：取线膨胀系a1≤1、粘度≥8000cp、流动性80cm～120cm的塑封料，采用带真空吸附的全自动塑封系统对步骤6压焊后的基板进行塑封，同时应用现有的多段注射防翘曲软件控制技术防止冲丝、翘曲和离层；在后固化过程中，采用防翘曲专用固化夹具夹紧塑封后的胶体，在175℃±10℃温度下，后固化4～7小时，制成SiP系统级集成封装整条半成品；
步骤8：采用LMK-54打印设备在SiP系统级集成封装整条半成品上印字；
步骤9：用AE公司的MWM-850贴膜设备在步骤9印字后的SiP系统级集成封装整条半成品表面贴膜；然后，采用DISCO公司的 AD3350切割设备对表面贴膜后的SiP系统级集成封装整条半成品进行切割；之后，用DISCO公司的DCS1440清洗设备进行清洗；用AE公司的UV-956照射设备进行UV照射；捡拾分选；最后，用离子风机进行风干；
贴膜选用FC-217M-170UV胶膜；
步骤10：采用普通封装件的防静电真空包装工艺进行包装，制成SiP系统集成级IC芯片封装件。
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