CN102054807B - 膜上芯片型半导体封装 - Google Patents

膜上芯片型半导体封装 Download PDF

Info

Publication number
CN102054807B
CN102054807B CN201010219206.5A CN201010219206A CN102054807B CN 102054807 B CN102054807 B CN 102054807B CN 201010219206 A CN201010219206 A CN 201010219206A CN 102054807 B CN102054807 B CN 102054807B
Authority
CN
China
Prior art keywords
chip
film
type semiconductor
backing
insulation backing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201010219206.5A
Other languages
English (en)
Other versions
CN102054807A (zh
Inventor
金都永
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Megna Zhixin Hybrid Signal Co.,Ltd.
Original Assignee
MagnaChip Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by MagnaChip Semiconductor Ltd filed Critical MagnaChip Semiconductor Ltd
Publication of CN102054807A publication Critical patent/CN102054807A/zh
Application granted granted Critical
Publication of CN102054807B publication Critical patent/CN102054807B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本发明涉及一种膜上芯片型半导体封装，其包括膜、在膜上形成的多个导线、在所述多个导线上形成的芯片、填充芯片与多个导线间的空间的底填层和在膜的与多个导线接触的相反侧上形成的绝缘热片，其中所述绝缘热片是由基于玻璃纤维的复合物形成。

Description

膜上芯片型半导体封装
相关申请的交叉引用
本发明要求2009年10月30日提交的韩国专利申请第10-2009-0104653号的优先权，其全文通过引用并入本文。
技术领域
本发明的示例性实施方案涉及半导体封装，且更具体地涉及膜上芯片型半导体封装。
背景技术
由于需要低制造成本和高性能的显示装置，如液晶显示(LCD)面板，所以显示装置像素的集成度升高。
因此，随着用于对显示装置中每一像素进行控制的驱动器IC芯片的节距已尽可能减小，已经发展了各种半导体封装。
半导体型封装，如带载式封装(tape carrier package)(TCP)、玻璃上芯片(chip on glass)(COG)和膜上芯片(chip on film)(COF)通常用于显示装置。
自1990年代起，COF型半导体封装作为常用半导体型封装已主要用于改善产率及降低生产成本。
COF型半导体封装是用于使显示装置的驱动器IC芯片最小化的新型半导体封装。
由于TV和监视器的驱动频率已由60Hz上升到120Hz，所以驱动器IC芯片的驱动负载也上升，因此增加驱动器IC芯片的热量。增加的热量被认为是个问题。
韩国专利第10-0771890号公开了一种用于解决与驱动器IC芯片热量增加有关的问题的方法。
图1是常规COF型半导体封装100的横截面视图。
参照图1，常规COF型半导体封装100包括驱动器IC芯片103、凸块(bump)106、多个导线102、底填层(under-fill layer)107、膜101、热垫(heat pad)104及绝缘带105。
膜101是柔性的且通过所述多个导线102和凸块106与驱动器IC芯片103连接。
所述多个导线102在膜101上彼此分离地形成，且所述导线102的一端设置为集中于中心区域。
在驱动器IC芯片103与膜101之间的空间中，填充底填层107以稳固地固定驱动器IC芯片103及柔性膜101。
热垫104通过粘合部件(未显示)在膜101的与导线102接触的相反侧上形成。
热垫104可使由驱动器IC芯片103运行所产生的热通过底填层107及导线102辐射。热垫104可包括金属材料如铝(Al)。
如上所述，由于常规COF型半导体封装100包括含有金属材料的热垫104，因此常规COF型半导体封装100不具柔性。
此外，由于常规COF型半导体封装100包括含有金属材料的热垫104，因此附加绝缘带105对于热垫104的绝缘处理是必需的。其使得COF型半导体封装100的制造方法不便利。
此外，由于热垫104变得柔性较差，当热垫104变厚时导线102容易损坏。
发明内容
本发明的实施方案涉及提供用于制造半导体存储器件的方法，其可降低半导体存储器件的制造成本。
本发明的其它目的及优势可通过以下描述来理解，且参考本发明的实施方案将变得显而易见。此外，本发明所属领域中的技术人员显然可通过本发明要求保护的方案及其组合来实现本发明的目的和优势。
根据本发明的实施方案，膜上芯片型半导体封装包括：膜、在膜上形成的多个导线、在多个导线上形成的芯片、填充芯片与多个导线之间空间的底填层、及在膜的接触多个导线的相反侧上形成的绝缘热片(insulating heating sheet)，其中绝缘热片是由基于玻璃纤维的复合物形成。
绝缘热片可具有栅格结构形式。
绝缘热片可具有硅面和玻璃纤维的堆叠结构。
绝缘热片可包括包含硅橡胶、氮化硼及玻璃纤维的复合物。
硅橡胶的体积含量可为约19％至约24％，氮化硼的体积含量可为约65％至约71％和玻璃纤维的体积含量可为小于约10％。
绝缘热片厚度可为约100μm至约200μm。
绝缘热片可通过粘合部件与膜相附着。
芯片可包括驱动器IC芯片。
底填层可包括液体树脂。
绝缘热片可具有小于约0.2℃/W的热阻。
附图说明
图1是说明常规膜上芯片(COF)型半导体封装的横截面视图。
图2是说明根据本发明的一个实施方案的膜上芯片(COF)型半导体封装的横截面视图。
图3A是说明图2所示热片的横截面视图。
图3B是说明图3A中热片的详细视图。
具体实施方案
本发明的示例性实施方案将参考附图更详细描述。然而，本发明可以不同形式实施且不应将其理解为限制于本文所述的实施方案。相反地，提供这些实施方案以使本发明公开详尽及完整，并且相本领域技术人员完整传达本发明的范围。在整个公开内容中，相同参考数字指代本发明实施方案和各图中的相同部件。
各图不一定按照比例绘制，在某些实例中，可放大其比例以清晰说明实施方案的特征。当第一层称为在第二层“上”时，不仅指第一层是直接在第二层或衬底上形成的情况，也指在第一层与第二层之间存有第三层的情况。
图2是说明根据本发明的一个实施方案的膜上芯片(COF)型半导体封装200的横截面视图。图3A是说明热片的横截面视图。图3B是说明图3A中热片的详细视图。
参照图2，COF型半导体封装200包括驱动器IC芯片203、凸块205、多个导线202、底填层206、膜201、粘合部件207和绝缘热片204。膜201是柔性的并且通过所述多个导线202及凸块205与驱动器IC芯片203连接。
多个导线202彼此分离地在膜201下方形成，并且导线202的一端设置为集中于中心区域。
在驱动器IC芯片203与膜201之间的空间中，填充底填层206以稳固地固定驱动器IC芯片203和膜201。
绝缘热片204是通过粘合部件207在膜201上形成。
膜201可包括绝缘层，如聚酰亚胺。导线202可包括铜(Cu)。导线202和驱动器IC芯片203通过凸块205连接。凸块205可包括金(Au)。底填层206可包括液体树脂。
粘合部件207可包括导电材料。导电材料可包括基于丙烯酸的材料。
热片204可将驱动器IC芯片203运行所产生的热通过底填层206和导线202辐射到外部。
绝缘热片204包括基于玻璃纤维而非基于金属的复合物。例如，绝缘热片204可包括玻璃纤维层、基于硅面的层及玻璃纤维层的堆叠层。
绝缘热片204可包括包含硅橡胶、氮化硼和玻璃纤维的复合物。硅橡胶的体积含量为约19％至约24％。氮化硼的体积含量为约65％至约71％。玻璃纤维的体积含量为小于约10％。
如图3A所示，绝缘热片204可具有玻璃纤维204C插入两个硅面层204A和204B之间的结构，以提高导热性及降低热阻。
如图3B所示，玻璃纤维204C可具有栅格结构的形式。
此外，由于包括硅橡胶、氮化硼及玻璃纤维的绝缘热片204具有绝缘特性，所以无需外加绝缘带105来绝缘处理包含绝缘热片204的COF型半导体封装200。因此，可降低制造成本。
绝缘热片204的厚度为约100μm至约200μm的范围内。包含热片204的COF型半导体封装200的散热效果随绝缘热片204厚度变大而变大。
绝缘热片204是柔性的，是因为绝缘热片204包含基于具有柔性的玻璃纤维204C的复合物。可将绝缘热片204提供至辊型层压设备。即，层压设备可容易地将绝缘热片204层压至膜201而不受设计的限制。与此相反的是，由于常规热垫104包含金属基材料(如铝(Al))，故常规热垫104不是柔性的。
例如，包含热片204的COF型半导体封装200可用于车辆部件、发光二极管(LED)及荧光灯辐射热的目的。包含热片204的COF型半导体封装200可应用于各种不包括膜型散热器的产品，如其上无法安装散热器的驱动器IC、热控制器、中央处理单元(CPU)、存储器。
绝缘热片204可用作柔性型印刷电路板(PCB)中需要绝缘的热片或用作驱动器IC芯片、半导体器件及热块中的散热器。
此外，由于基于玻璃纤维的绝缘热片204具有大的张力，因此包含热片204的COF型半导体封装200可应用于需要张力和柔性的产品。
常规热垫104与本发明实施方案的热片204之间的热导性及热阻比较结果描述于以下表1中。
表1
  常规热垫104   绝缘热片1   绝缘热片2   绝缘热片3
  厚度   110μm   200μm   200μm   200μm
  热导性   4.5W/mk   5.0W/mk   4.1W/mk   3.9W/mk
  热阻   0.25℃/W   0.12℃/W   0.18℃/W   0.19℃/W
参照表1，绝缘热片1是BFG20A，绝缘热片2是BFG20及绝缘热片3是BS20。BFG20A、BFG20及BS20是名为NISSO SHOJI Corporation的生产商的商品名称。
如表1所示，绝缘热片1、2及3具有与常规热垫104的热导性类似的热导性(即，约4.5W/mk)。绝缘热片1、2及3具有比常规热垫104小的热阻(即，约0.2℃/W)。
此外，由于与常规热垫104相比，热片204的柔性较大且热片204的价格较低，所以包含热片204的COF型半导体封装200可广泛地应用于各种产品。
如上所述，根据本发明的实施方案，由于无需绝缘处理包含热片的COF型半导体封装，因此可降低制造成本。包含柔性热片的COF型半导体封装可应用于各种产品。
此外，由于基于玻璃纤维的绝缘热片具有大的张力，所以包含热片的COF型半导体封装可应用于需要张力和柔性的产品。
此外，由于绝缘热片提供缓冲膜与所基于的驱动器IC芯片之间的温度差的扩散效应(spread effect)，因此抑制收缩和膨胀，从而防止导线损坏。
尽管已针对具体实施方案描述本发明，但本领域技术人员将了解在不脱离权利要求中所限定的本发明的精神及范围下，可进行各种改变及修改。

Claims (8)

1.一种膜上芯片型半导体封装，其包括：
膜；
在所述膜下方形成的多个导线；
与所述导线的一端连接的芯片；
填充于所述芯片与所述多个导线间的底填层；和
在所述膜上形成且包含插入硅面层之间的玻璃纤维的绝缘热片，其中所述绝缘热片具有小于0.2℃/W的热阻。
2.权利要求1的膜上芯片型半导体封装，其中所述绝缘热片具有栅格结构的形式。
3.权利要求1的膜上芯片型半导体封装，其中所述绝缘热片包含含有硅橡胶、氮化硼及玻璃纤维的复合物。
4.权利要求3的膜上芯片型半导体封装，其中所述硅橡胶的体积含量为19％至24％，所述氮化硼的体积含量为65％至71％和所述玻璃纤维的体积含量为小于10％。
5.权利要求1的膜上芯片型半导体封装，其中所述绝缘热片具有100μm至200μm的厚度。
6.权利要求1的膜上芯片型半导体封装，其中所述绝缘热片通过粘合部件附着于所述膜。
7.权利要求1的膜上芯片型半导体封装，其中所述芯片包括驱动器IC芯片。
8.权利要求1的膜上芯片型半导体封装，其中所述底填层包括液体树脂。
CN201010219206.5A 2009-10-30 2010-06-30 膜上芯片型半导体封装 Active CN102054807B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020090104653A KR101189255B1 (ko) 2009-10-30 2009-10-30 칩온필름형 반도체 패키지
KR10-2009-0104653 2009-10-30

Publications (2)

Publication Number Publication Date
CN102054807A CN102054807A (zh) 2011-05-11
CN102054807B true CN102054807B (zh) 2015-07-08

Family

ID=43924495

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201010219206.5A Active CN102054807B (zh) 2009-10-30 2010-06-30 膜上芯片型半导体封装

Country Status (5)

Country Link
US (1) US8283774B2 (zh)
JP (1) JP2011097006A (zh)
KR (1) KR101189255B1 (zh)
CN (1) CN102054807B (zh)
TW (1) TWI438874B (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20120122266A (ko) * 2011-04-28 2012-11-07 매그나칩 반도체 유한회사 칩온필름형 반도체 패키지
TWI441293B (zh) * 2011-06-29 2014-06-11 Au Optronics Corp 緩衝元件及應用此緩衝元件之覆晶軟膜接合方法
CN209845575U (zh) * 2018-08-29 2019-12-24 惠科股份有限公司 一种显示面板和显示装置
CN109300879B (zh) * 2018-09-18 2020-12-29 惠科股份有限公司 驱动芯片封装结构及其分离方法、分离设备

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5221575A (en) * 1990-10-30 1993-06-22 Shin-Etsu Chemical Co. Ltd. Thermally conductive sheet
US6225701B1 (en) * 1999-03-05 2001-05-01 Kabushiki Kaisha Toshiba Semiconductor device provided with heat-sink and method of manufacturing the same

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56161140A (en) * 1980-05-16 1981-12-11 Denki Kagaku Kogyo Kk Manufacture of insulating heat radiating sheet
JP2906953B2 (ja) 1993-11-05 1999-06-21 信越化学工業株式会社 絶縁性放熱シート及びその製造方法
US6855578B2 (en) * 2002-08-16 2005-02-15 Texas Instruments Incorporated Vibration-assisted method for underfilling flip-chip electronic devices
JP3908671B2 (ja) * 2003-01-29 2007-04-25 松下電器産業株式会社 半導体装置およびそれを用いたディスプレイ装置
JP2005116668A (ja) 2003-10-06 2005-04-28 Oki Electric Ind Co Ltd 放熱シール
KR100771890B1 (ko) 2006-07-20 2007-11-01 삼성전자주식회사 씨오에프(ｃｏｆ)형 반도체 패키지
KR101493869B1 (ko) 2008-04-17 2015-02-23 삼성전자주식회사 방열 부재 테이프, 방열부재를 구비한 씨오에프(ｃｏｆ)형 반도체 패키지 및 이를 적용한 전자장치

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5221575A (en) * 1990-10-30 1993-06-22 Shin-Etsu Chemical Co. Ltd. Thermally conductive sheet
US6225701B1 (en) * 1999-03-05 2001-05-01 Kabushiki Kaisha Toshiba Semiconductor device provided with heat-sink and method of manufacturing the same

Also Published As

Publication number Publication date
TWI438874B (zh) 2014-05-21
US20110101513A1 (en) 2011-05-05
CN102054807A (zh) 2011-05-11
TW201115690A (en) 2011-05-01
KR101189255B1 (ko) 2012-10-09
KR20110047863A (ko) 2011-05-09
US8283774B2 (en) 2012-10-09
JP2011097006A (ja) 2011-05-12

Similar Documents

Publication Publication Date Title
US20090008771A1 (en) Semiconductor module device, method of manufacturing the same, flat panel display, and plasma display panel
US20100163090A1 (en) Thermoelectric device and fabrication method thereof, chip stack structure, and chip package structure
JP6862896B2 (ja) 半導体装置及び半導体装置の製造方法
CN101692443B (zh) 薄膜覆晶型半导体封装及显示装置
US20110143625A1 (en) Tape for heat dissipating member, chip on film type semiconductor package including heat dissipating member, and electronic apparatus including the same
US20060151206A1 (en) Semiconductor device and manufacturing method therefor
CN102054807B (zh) 膜上芯片型半导体封装
KR20090062612A (ko) 멀티 칩 패키지
TWI781215B (zh) 改善散熱及電磁波屏蔽功能的層壓石墨的膜上晶片型半導體封裝
CN1747105B (zh) 平面显示器及等离子体显示器
US9365768B2 (en) White light emitting diode, manufacturing method and packaging material thereof
JP2017005165A (ja) 半導体装置
JP2009536458A (ja) 半導体モジュール及びその製造方法
US20130328200A1 (en) Direct bonded copper substrate and power semiconductor module
KR102172689B1 (ko) 반도체 패키지 및 그 제조방법
KR20090085256A (ko) 반도체 패키지 및 그 제조방법들
TW201541576A (zh) 半導體器件之封裝方法與實施該方法之設備
CN102931148B (zh) 半导体封装基板
CN210805740U (zh) 封装结构和电子设备
US7601561B2 (en) Heat-radiating tape carrier package and method for manufacturing the same
US11842945B2 (en) Chip on film package and display apparatus including the same
CN101908528A (zh) 电子封装结构及其载板
US9439326B1 (en) Electronic components
US20090183364A1 (en) Method of connecting a series of integrated devices utilizing flexible circuits in a semi-stacking configuration
CN218827079U (zh) 功率模组

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20240425

Address after: Han Guozhongqingbeidao

Patentee after: Megna Zhixin Hybrid Signal Co.,Ltd.

Country or region after: Republic of Korea

Address before: Cheongju Chungbuk Korea

Patentee before: MagnaChip Semiconductor, Ltd.

Country or region before: Republic of Korea