CN101796620A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN101796620A
CN101796620A CN200880106197A CN200880106197A CN101796620A CN 101796620 A CN101796620 A CN 101796620A CN 200880106197 A CN200880106197 A CN 200880106197A CN 200880106197 A CN200880106197 A CN 200880106197A CN 101796620 A CN101796620 A CN 101796620A
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gate electrode
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理崎智光
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Ablic Inc
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Abstract

在通过相对栅极长度方向呈水平地形成多个沟槽来增大每单位面积的栅极宽度的高驱动能力横型MOS中，为了在不增加元件面积的情况下进一步改善驱动能力，而作出一种半导体装置，其中包括：高电阻第一导电型半导体的阱区，在离半导体衬底表面一定的深度设置；多个沟槽，从所述阱区的表面达到中途的深度；栅极绝缘膜，设于所述沟槽所形成的凹凸部的表面；栅电极膜，设置在衬底表面并在埋入所述沟槽内部的栅电极和所述沟槽两端附近除外的所述凹凸部区域中与埋入所述沟槽内部的栅电极接触；栅电极膜，与所述栅电极膜接触并埋入为使其表面在所述沟槽两端附近的沟槽内部位于比半导体衬底表面更深的位置；以及2个低电阻第二导电型半导体层即源极区和漏极区，在从不与所述栅电极膜接触的半导体面设成比所述阱区的深度浅。

Description

半导体装置及其制造方法
技术领域
本发明涉及具有沟槽结构的半导体装置。
背景技术
随着时代的发展，半导体装置通过运用精细加工技术，能够在不降低能力的情况下作成更小。在具有高驱动能力的半导体元件中其流程也不例外，通过运用精细加工技术，实现了降低每单位面积的导通电阻。但是，随着元件的精细化而产生的耐压的降低，事实上也阻碍精细加工的驱动能力的进一步改善。为了打破该精细化和耐压的权衡(trade-off)，迄今提出了各式各样结构的元件，作为现在主流的结构，若举出具有高耐压且高驱动能力的功率MOS FET的例子，则有沟槽栅MOS。沟槽栅MOS在具有高耐压且高驱动能力的DMOS之中集成度也是最高的。但是，沟槽栅MOS是使电流在衬底的深度方向流动的纵型MOS结构，虽然对元件单体而言具有非常优越的性能，但不利于与IC的芯片级(on chip)化。考虑到与IC的芯片级化，依然不得不选择传统横型MOS结构。作为在不降低耐压的情况下进一步降低每单位面积的导通电阻的方法，设计了将栅极部作成具有凸部和凹部的沟槽结构来获得栅极宽度的横型沟槽栅型晶体管(例如，参照专利文献1)。
图3及图4中示出传统横型沟槽栅型晶体管的概念图。在此，图3(a)为鸟瞰图，图3(b)为平面图，图4(a)、(b)、(c)分别是沿着图3(b)的线段4A-4A’、4B-4B’、4C-4C’的剖视图。横型沟槽栅型晶体管包括：多个沟槽，配置成与晶体管的沟道方向平行，该晶体管配置在设于n型或p型的高电阻半导体衬底006表面的p型阱区005；凸部007，位于由沟槽规定的凹部008及凹部的两侧；栅极绝缘膜004，设于凹部及凸部表面；栅电极003，填充凹部并配置在凸部的栅极绝缘膜之上；源极区001及漏极区002，配置成在夹住栅电极的两侧的阱区表面与沟槽组合。在此图3(b)中为了方便图示而使沟槽外部的栅电极003和栅极绝缘膜004透明，并且用粗线示出栅电极003的边缘。该发明是通过将栅极部作成沟槽结构来扩大横型MOS的每单位平面积的栅极宽度并降低导通电阻的发明。图中的虚线019示出流过晶体管的电流路径。
专利文献1：日本特开2006-294645号公报
发明内容
但是，上述的发明中存在一个问题。在上述的发明中，沟槽越深，并且图3及图4所示的栅电极的顶部长度LP越短，则沟槽底部附近的沟道长度就会比全体沟槽顶部附近长，会发生如图3及图4所示，不使沿着沟槽底部附近的电流路径019的电流充分流过，并得不到充分的驱动能力的问题。
(1)一种半导体装置及其制造方法，其中该半导体装置包括：高电阻第一导电型半导体的阱区，在离半导体衬底表面一定的深度设置；多个沟槽，从所述阱区的表面达到中途的深度；栅极绝缘膜，设于所述沟槽所形成的凹凸部的表面；栅电极膜，设置在衬底表面并在埋入所述沟槽内部的栅电极和所述沟槽两端附近除外的所述凹凸部区域中与埋入所述沟槽内部的栅电极接触；栅电极膜，与所述栅电极膜接触并埋入为使其表面在所述沟槽两端附近的沟槽内部位于比半导体衬底表面更深的位置；以及2个低电阻第二导电型半导体层即源极区和漏极区，在从不与所述栅电极膜接触的半导体面设成比所述阱区的深度浅。
(2)在上述(1)所述的半导体装置中，在所述源极区和漏极区的半导体表面比所述沟槽两端附近除外的沟槽区域的凸部的高度深的结构中，具有从不与所述栅电极膜接触的半导体面设置成比所述阱区的深度浅的2个低电阻第二导电型半导体层即源极区和漏极区。
(3)在上述(1)或(2)所述的半导体装置中，在所述沟槽两端附近的沟槽内部不存在栅电极膜的结构中，具有从不与所述栅电极膜接触的半导体面设置成比所述阱区的深度浅的2个低电阻第二导电型半导体层即源极区和漏极区。
发明效果
通过加深源极及漏极区的深度，使电流在底部附近的沟道中也充分流过，从而改善驱动能力。
附图说明
图1是本发明的基本结构示图。(a)鸟瞰图。(b)平面图。
图2是图1(b)的剖视图(a)线段2A-2A’的剖视图。(b)线段2B-2B’的剖视图。(c)线段2C-2C’的剖视图。
图3是传统技术的实施例示图。(a)鸟瞰图。(b)平面图。
图4是图3(b)的剖视图(a)线段4A-4A’的剖视图。(b)线段4B-4B’的剖视图。(c)线段4C-4C’的剖视图。
图5是表示本发明的制造工序的鸟瞰图。
图6是表示本发明的基本结构及其制造工序的图。(a)鸟瞰图。(b)线段6A-6B’的剖视图。
图7是表示本发明的基本结构及其制造工序的图。(a)鸟瞰图。(b)线段7A-7A’的剖视图。
符号说明
001源极区
002漏极区
003栅电极
004栅极绝缘膜
005阱区
006高电阻半导体衬底
007凸部
008凹部
019电流路径
具体实施方式
利用图1及图2，说明本发明的第一实施例。
在此，图1(a)为鸟瞰图，图1(b)为平面图，图2(a)、(b)、(c)分别为沿着图1(b)的线段2A-2A’、2B-2B’、2C-2C’的剖视图。在这些图中对于与图3及图4所示的传统技术对应的构成要素采用相同的符号。在此图1(b)中为了方便图示而使沟槽外部的栅电极003和栅极绝缘膜004透明并且用粗线来示出栅电极003的边缘。与传统技术的不同点是加大了从半导体衬底的表面到埋入沟槽内部的栅电极的表面为止的距离dP，以使源极区001及漏极区002尽量能够形成至沟槽凹部的下方。如图2(b)、(c)所示，在dP大的结构中如果用多方向倾斜离子注入法作成源极/漏极区，则离子进入dP的沟槽侧壁部并可将源极/漏极区作成到比传统技术深的部位，且源极/漏极的深度可以深达与dP大致相同深度的dSD。从而，如图1(a)所示比传统技术更能使电流沿着沟槽底部区域的电流路径019流过，改善了驱动能力。
在图5中示出具有这样的结构的横型沟槽栅型晶体管的制造方法。首先如(a)所示在n型或p型半导体衬底006作成p型阱005，然后通常作成多个具有凸部007和凹部008的沟槽。如(b)所示，接着通过热氧化来使任意膜厚的氧化膜生长并成为栅极绝缘膜004。接着为了形成栅电极003而沉积例如多晶硅(Poly-Si)等之后，通过抗蚀剂来遮掩任意部位的多晶硅，蚀刻其它的多晶硅。在进行该蚀刻时，将多晶硅蚀刻至按照蚀刻减缩率消除源极/漏极区上的氧化膜的程度，尽量除去埋入沟槽内部的多晶硅，扩大dP。更具体地说，栅电极包括配置在半导体衬底表面上的第二栅电极、在该第二栅电极的下方埋入于沟槽内部的第一栅电极和在沟槽内部配置于第一栅电极两侧的其表面被蚀刻的第三栅电极。然后，如(c)所示，离子注入n型离子种并通过自对准(self aligned)来作成源极/漏极区(001及002)。这时使用多方向倾斜离子注入法进行离子注入，从而使离子注入至没有栅电极的沟槽侧壁，可将源极/漏极区作成比传统技术更深。
在此通过使源极/漏极区的深度与沟槽底部的高度相等来显著改善了驱动能力，但这要如图6(a)及图6(b)所示，能够通过上述的栅电极蚀刻中全部除去没有被遮掩的部位的沟槽内部的栅电极来实现。但是认为还有这样的情形，即，通过沟槽深度、栅极氧化膜的厚度、还有蚀刻的栅电极/氧化膜的选择比，直至沟槽内部的栅电极全部被除去，源极/漏极区上的氧化膜按照蚀刻减缩率来消除，就连源极/漏极区的硅也蚀刻，成为如图7所示的形状。但是，该形状中也与上述同样地能够通过多方向倾斜离子注入法注入n型离子种来作成更深的源极/漏极区，作为高驱动能力MOS起作用。
在上述例中，显然也可以通过反转导电型来同样地作成p沟道型MOS结构，如果使用双阱方法，不仅可以容易用1芯片作成具有高驱动能力的CMOS结构，而且也可以容易混合并承放IC。以上为本发明的基本结构及基本制造法。
下面，对上述的基本结构的应用进行描述。
在普通的平面型MOS中，为了改善耐压而以基本结构基础存在各式各样的结构。关于本发明也同样，以基本结构(图5～图7)为基础，可以结合LDD(轻掺杂漏极：Light Doped Drain)结构、DDD(双扩散漏极：Double Diffused Drain)结构、LDMOS(横向双扩散MOS：Lateral Double diffused MOS)结构等的传统技术，因此容易改善耐压。
此外，通过将图1所示的凸部007的宽度做成1000埃程度，在MOS成为导通状态时使凸部内部全部耗尽化，改善次临界(sub-threshold)特性。因而源极-漏极间的泄漏减少，可以降低阈值，其结果可以进一步改善驱动能力。
此外，通过结合本发明和传统双阱技术，可将两极性沟道的本发明的半导体装置和普通的IC混合承载于同一芯片上，并可以简单作成混合承载CMOS驱动器的IC。
以上，说明了本发明的实施方式，但本发明并不局限于上述的实施方式，本发明在不超出其要旨的范围内可做变形。

Claims (11)

1.一种半导体装置，其中包括：
高电阻第一导电型半导体的阱区，在离半导体衬底表面一定的深度设置；
多个沟槽，从所述阱区的表面达到中途的深度；
栅极绝缘膜，设于所述沟槽所形成的凹部及凸部的表面；
第一栅电极，埋入于所述沟槽的内部；
第二栅电极，设置在所述半导体衬底表面并在所述沟槽的两端附近除外的所述凹部及凸部的区域中接触于所述第一栅电极；
第三栅电极，接触于所述第一栅电极及所述第二栅电极并埋入成使其表面在所述沟槽的两端附近的沟槽内部位于比所述半导体衬底表面深的位置；以及
低电阻第二导电型半导体层的源极区及漏极区，在从不与所述第三栅电极接触的半导体面到所述沟槽的所述凹部的侧面，设置为比所述沟槽的所述凸部的表面深，而且比所述阱区的深度浅。
2.如权利要求1所述的半导体装置，其特征在于：不具有所述第三栅电极。
3.如权利要求2所述的半导体装置，其中，所述源极区及漏极区的顶面在低于所述栅极绝缘膜的最顶面的位置。
4.如权利要求1至3中的任一项所述的半导体装置，其中，所述源极区及漏极区具有轻掺杂漏极结构。
5.如权利要求1至3中的任一项所述的半导体装置，其中，所述源极区及漏极区具有双扩散漏极结构。
6.如权利要求1至3中的任一项所述的半导体装置，其中，所述源极区及漏极区具有横向双扩散MOS结构。
7.如权利要求1至3中的任一项所述的半导体装置，其中，所述沟槽部的凸部宽度大致为1000埃。
8.如权利要求1至3中的任一项所述的半导体装置，其中，还结合了双阱技术。
9.如权利要求1至3中的任一项所述的半导体装置，在所述半导体装置中，反转了所有的导电型。
10.一种半导体装置的制造方法，其中包括：
从半导体衬底表面以一定的深度形成高电阻第一导电型半导体的阱区的工序；
从所述阱区的表面形成达到中途的深度的多个沟槽的工序；
在形成所述沟槽的凹部及凸部的表面设置栅极绝缘膜的工序；
在所述沟槽内部及所述半导体衬底表面沉积栅电极材料的工序；
通过蚀刻法用所述栅电极材料形成埋入于所述沟槽的内部的第一栅电极、设于所述半导体衬底表面并在所述沟槽的两端附近除外的所述凹部及凸部的区域中接触于所述第一栅电极的第二栅电极、以及与所述第一栅电极及所述第二栅电极接触并埋入成使其表面在所述沟槽的两端附近的沟槽内部比所述半导体衬底表面深的位置的第三栅电极的工序；以及
通过从多方向开始的倾斜离子注入法在从不与所述第三栅电极接触的半导体面到所述沟槽的所述凹部的侧面形成设置为比所述沟槽的所述凸部的表面更深，而且设置为比所述阱区的深度浅的低电阻第二导电型半导体层的源极区及漏极区的工序。
11.如权利要求10所述的半导体装置的制造方法，其中，包括在蚀刻所述栅电极材料时同时蚀刻所述源极及漏极区的半导体表面的工序。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105097916A (zh) * 2014-05-05 2015-11-25 中芯国际集成电路制造(上海)有限公司 Mos晶体管器件及其制作方法
CN107452800A (zh) * 2016-05-24 2017-12-08 马克西姆综合产品公司 Ldmos晶体管及相关系统和方法

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2995139A1 (fr) 2012-09-04 2014-03-07 St Microelectronics Sa Transistor mos
EP3123413A4 (en) * 2014-03-25 2017-10-04 Interactive Intelligence Group, Inc. System and method for predicting contact center behavior
CN109065635B (zh) * 2018-08-22 2021-05-14 电子科技大学 一种横向二极管器件

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US223253A (en) * 1880-01-06 Half op his eight to geoege joseph o doheett
US101110A (en) * 1870-03-22 Improvement in drop-wire supporting-bars or plates of warfing-machines
KR940005451B1 (ko) 1984-11-27 1994-06-18 아메리칸 텔리폰 앤드 텔레그라프 캄파니 Mos 트렌치 트랜지스터 장치 및 그 제조 방법
JPH0575121A (ja) * 1991-09-18 1993-03-26 Fujitsu Ltd 半導体装置
US5467305A (en) * 1992-03-12 1995-11-14 International Business Machines Corporation Three-dimensional direct-write EEPROM arrays and fabrication methods
US5399516A (en) * 1992-03-12 1995-03-21 International Business Machines Corporation Method of making shadow RAM cell having a shallow trench EEPROM
US5932911A (en) * 1996-12-13 1999-08-03 Advanced Micro Devices, Inc. Bar field effect transistor
JP2001102574A (ja) * 1999-09-29 2001-04-13 Toshiba Corp トレンチゲート付き半導体装置
JP2006019518A (ja) * 2004-07-01 2006-01-19 Seiko Instruments Inc 横型トレンチｍｏｓｆｅｔ
JP4976658B2 (ja) * 2005-04-05 2012-07-18 セイコーインスツル株式会社 半導体装置の製造方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105097916A (zh) * 2014-05-05 2015-11-25 中芯国际集成电路制造(上海)有限公司 Mos晶体管器件及其制作方法
CN107452800A (zh) * 2016-05-24 2017-12-08 马克西姆综合产品公司 Ldmos晶体管及相关系统和方法
US10833164B2 (en) 2016-05-24 2020-11-10 Maxim Integrated Products, Inc. LDMOS transistors and associated systems and methods
CN107452800B (zh) * 2016-05-24 2021-02-26 马克西姆综合产品公司 Ldmos晶体管及相关系统和方法

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