US7485921B2 - Trench gate type MOS transistor semiconductor device - Google Patents

Trench gate type MOS transistor semiconductor device Download PDF

Info

Publication number
US7485921B2
US7485921B2 US11/674,337 US67433707A US7485921B2 US 7485921 B2 US7485921 B2 US 7485921B2 US 67433707 A US67433707 A US 67433707A US 7485921 B2 US7485921 B2 US 7485921B2
Authority
US
United States
Prior art keywords
layer
semiconductor
conductivity type
base layer
epitaxial
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
US11/674,337
Other versions
US20070194375A1 (en
Inventor
Yusuke Kawaguchi
Yoshihiro Yamaguchi
Syotaro Ono
Miwako Akiyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP2006041954A priority Critical patent/JP2007221024A/en
Priority to JP2006-41954 priority
Application filed by Toshiba Corp filed Critical Toshiba Corp
Assigned to KABUSHIKI KAISHA TOSHIBA reassignment KABUSHIKI KAISHA TOSHIBA ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ONO, SYOTARO, AKIYAMA, MIWAKO, KAWAGUCHI, YUSUKE, YAMAGUCHI, YOSHIHIRO
Publication of US20070194375A1 publication Critical patent/US20070194375A1/en
Application granted granted Critical
Publication of US7485921B2 publication Critical patent/US7485921B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095Body region, i.e. base region, of DMOS transistors or IGBTs
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402Field plates
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725Source or drain electrodes for field effect devices
    • H01L29/41741Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725Source or drain electrodes for field effect devices
    • H01L29/41766Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor

Abstract

This semiconductor device comprises a first semiconductor layer of a first conductivity type, an epitaxial layer of a first conductivity type formed in the surface on the first semiconductor layer, and a base layer of a second conductivity type formed on the surface of the epitaxial layer. Column layers of a second conductivity type are repeatedly formed in the epitaxial layer under the base layer at a certain interval. Trenches are formed so as to penetrate the base layer to reach the epitaxial layer; and gate electrodes are formed in the trenches via a gate insulation film. A termination layer of a second conductivity type is formed on the epitaxial layer at an end region at the perimeter of the base layer. The termination layer is formed to have a junction depth larger than that of the base layer.

Description

CROSS REFERENCE TO RELATED APPLICATIONS

This application is based on and claims the benefit of priority from prior Japanese Patent Application No. 2006-41954, filed on Feb. 20, 2006, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device, more particularly to a semiconductor device including a so-called trench gate type MOS transistor.

2. Description of the Related Art

In recent years, demands of power MOS transistors are increasing rapidly, not only in a market of switching power supplies with large current and high breakdown voltage (for example, a breakdown voltage of 600V), but also in a market of energy-saving switching devices used in a mobile communication device including a notebook PC (for example, a breakdown voltage of 30V).

A power MOS transistor used in such an energy-saving switching device market is required to reduce its driving voltage so that it can be driven directly by a voltage from a battery. It is also required to reduce its ON-resistance, and its gate-drain capacitance for reduction of switching loss, and so forth.

On the other hand, an ON-resistance of a MOS transistor mainly consists of a channel resistance and drift resistance. A structure called super-junction structure is known as a structure of a MOS transistor for reducing a drift resistance.

A super-junction structure forms a drift layer as a structure in which longwise strip-shaped p-type pillar layers and n-type pillar layers are embedded in turn in the transverse direction (for example, see JP 2003-273355 A). When a charge quantity (an impurity quantity) in a p-type pillar layer is equal to that in an n-type pillar layer in a super-junction structure, a pseudo non-doped layer can be formed therein. Thereby, a low ON-resistance beyond a material limit is realized by flowing a current in a high-doped n-type pillar layer, while keeping a required breakdown voltage.

Even in a power MOS transistor having a breakdown voltage of about 30V suitable for an energy-saving switching element, it is possible to form a MOS transistor with a low ON resistance by forming a drift layer of super-junction structure.

However, in a power MOS transistor having a low breakdown voltage of about 30V used for an energy-saving switching element, a pitch of a super-junction structure needs to be shortened to about 1 micrometer, which is shorter than a power MOS transistor of a large current and a high breakdown voltage. Such a narrow-pitched super-junction structure must be formed in the last step in a process including a MOSFET-forming process, in order to prevent thermal diffusion. Thus, it is difficult to form such a narrow-pitched super-junction structure not only in an element region but also in an end region surrounding the element region.

For this reason, in a power MOS transistor with a breakdown voltage of about 30V used for an energy-saving switching element, concentration of electric field in an end region could not be eased enough. Therefore, a breakdown voltage in an end region cannot be high enough compared to that in an element region. This is recognized as a problem.

SUMMARY OF THE INVENTION

A semiconductor device according to one aspect of the present invention comprises: a first semiconductor layer of a first conductivity type; an epitaxial layer of a first conductivity type formed in the surface on the first semiconductor layer; a base layer of a second conductivity type formed on the surface of the epitaxial layer; column layers of a second conductivity type repeatedly formed in the epitaxial layer under the base layer at a certain interval; a diffusion layer of a first conductivity type formed selectively in the base layer; trenches formed so as to penetrate the base layer to reach the epitaxial layer; gate electrodes formed in the trenches via a gate insulation film formed on an inner wall of the trench; a first main electrode connected to the back side of the first semiconductor layer; a second main electrode connected to the diffusion layer and the base layer; and a termination layer of a second conductivity type formed on the epitaxial layer at an end region at the perimeter of the base layer, the termination layer being formed to have a junction depth larger than that of the base layer.

A semiconductor device according to another aspect of the present invention comprises: a first semiconductor layer of a first conductivity type; an epitaxial layer of a first conductivity type formed in the surface on the first semiconductor layer; a base layer of a second conductivity type formed on the surface of the epitaxial layer; column layers of a second conductivity type repeatedly formed in the epitaxial layer under the base layer at a certain interval; a diffusion layer of a first conductivity type formed selectively in the base layer; trenches formed so as to penetrate the base layer to reach the epitaxial layer; gate electrodes formed in the trenches via a gate insulation film formed on an inner wall of the trench; a first main electrode connected to the back side of the first semiconductor layer; a second main electrode connected to the diffusion layer and the base layer; and a semiconductor layer of a first conductivity type formed under the base layer at the perimeter of the column layer at an outermost portion and having an impurity concentration lower than the epitaxial layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a cross-sectional structure of the semiconductor device according to the first embodiment of the present invention.

FIG. 2 shows a modified example of the first embodiment.

FIG. 3 shows a cross-sectional structure of the semiconductor device according to the second embodiment of the present invention.

FIG. 4 shows a cross-sectional structure of the semiconductor device according to the third embodiment of the present invention.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Next, a semiconductor device according to embodiments of the present invention will be explained in detail with reference to drawings.

First Embodiment

FIG. 1 illustrates a cross-sectional structure of a semiconductor device according to a first embodiment of the present invention.

This semiconductor device is composed of an element region in which a semiconductor device, for example, a so-called trench-gate type n-channel MOS transistor is formed, and an end region formed to surround this element region. AMOS transistor in this embodiment is supposed to be a MOS transistor with a breakdown voltage of about 30V for the energy-saving switching device market used on a mobile communication device. Furthermore, although a trench gate type n-channel MOS transistor is explained as an example here, the present invention may not be limited to this. It may include a p-channel MOS transistor. The present invention may be applied to an IGBT, a Schottky-barrier diode, and so forth. Moreover, the present invention is applicable also to the planer type semiconductor device instead of a trench gate type.

As shown in FIG. 1, an n-channel MOS transistor formed in the element region is equipped with an n+ type silicon substrate 11. This n+ type silicon substrate 11 functions as a drain layer connected to a drain electrode 10 in the rear surface.

On this silicon substrate 11, an n-type epitaxial layer 12 with a lower impurity concentration and higher resistance than those of the silicon substrate 11, is formed to have a thickness of 3-4 micrometers for example.

P-type column layers 13 are formed at an interval of a predetermined pitch, for example, 1 micrometer, on the n-type epitaxial layer 12. The width X1 of the p-type column layer 13 itself is about 0.5 micrometer, for example.

Although the column layer 13 is formed to have a stripe shape in the direction perpendicular to the paper plane, the column layer 13 may not be limited to this. For example, it may be formed to have a lattice shape, or a hound tooth check shape in a plan view.

A super-junction structure is formed by these column layers 13 and the n-type epitaxial layer 12 sandwiched therebetween. That is, the p-type pillar layers are constituted by the column layers 13, and n-type pillar layers are constituted by the n-type epitaxial layer 12 inserted between the column layers 13. And a pseudo non-doped layer can be formed, if the charge quantity (impurity quantity) contained in pn pillars are the same.

A p-type base layer 14 is formed on the upper part of the super-junction structure portion, i.e., on the upper part of the column layer 13. Plural trenches T1 are formed in the p-type base layer 14 at positions between the column layers 13. That is, the trenches T1 are formed on the n-type pillar layers so that they penetrates the p-type base layer 14 to reach the epitaxial layer 12.

The trench T1 is formed to have a stripe shape in a direction perpendicular to the paper plane. Instead of a stripe shape, the trench T1 may be formed to form mesh shape.

The gate electrode 16 is formed in the trench T1 by burying polysilicon therein via a gate insulator film 15, in order to form a gate electrode of a trench-gate type MOS transistor.

Moreover, an n+ type source layer 17 and a p+ type contact layer 18 are formed on the surface of the p-type base layer 13 by diffusion at positions adjacent to the gate electrode 16. The source electrode 19 is formed so that it connects to the n+-type source layer 17 and the p+-type contact layer 18. The source electrode 19 is extended to the end region via a field plate insulation film 20, and the extended portion serves as a field-plate electrode for extending a depletion layer in a transverse direction to alleviate the concentration of the electric field when the MOS transistor is in a non-conductive state. A p-type termination layer 21 is formed in the surface of the epitaxial layer 12 at the end region under the field plate insulation film 20. The p-type termination layer 21 has a junction depth Y2 deeper than a junction depth Y1 of the p-type base layer 14.

The significance of this p-type termination layer 21 will be explained hereinbelow. As mentioned above, in a MOS transistor for a market of an energy-saving switching device with a breakdown voltage of about 30V used in mobile communication devices, the pn-pillar pitch of a super-junction structure is set at 1 micrometer for example, which is very small. For this reason, the column layer 13 needs to be formed by ion implantation using a mask in the process after the heating process for forming a MOS transistor which is described later. Therefore, the column layers 13 may be formed only in the element region, and it is difficult to form them in the end region.

However, if an end region is formed of the epitaxial layer 12 given high impurity concentration because of formation of a super-junction structure, a breakdown voltage of the end region becomes low compared to the element region.

Therefore, in this embodiment, the p-type termination layer 21 whose junction depth Y2 is deeper than the junction depth Y1 of the p-type base layer 14 is formed in the end region. The p-type termination layer 21 preferably has a larger width X2 than the width X1 of the column layer 13.

As described above, the termination layer 21 with the large junction depth is formed. Thereby, a depletion layer spreads between the n-type epitaxial layer 12 and the termination layer 21 at the end region up to the bottom of the epitaxial layer 12, when a reverse bias voltage is applied at the time of turnoff of a MOS transistor. This alleviates concentration of electric field in the end region. Therefore, the breakdown voltage of the end region may be kept higher enough compared to that in the element region. In addition, the junction depth Y2 of the termination layer 21 is desirably 40% or more of thickness Y3 of the epitaxial layer 12.

As shown in FIG. 2, this embodiment may be modified so that trenches are formed in the surface of the p-type base layer 14 over the upper part of the column layer 13, and the contact layer 18 is formed in the bottom of these trenches. The source electrode 19 may be embedded in these trenches. In this case, when forming the column layers 13 by ion implantation, it is possible to perform the implantation with lower energy.

Second Embodiment

Next, the second embodiment of the present invention will be explained with reference to FIG. 3. In FIG. 3, the same numerals are given to the same components as FIG. 1, and these components have the same structures and functions. Therefore, the detailed explanation thereof is omitted hereinbelow.

This embodiment comprises an n-type embedded layer 22 under the p-type termination layer 21. This layer has an effective impurity concentration and a career concentration lower than those in the n-type epitaxial layer 12 and a high resistance. This n-type embedded layer 22 may be formed by carrying out ion implantation of boron (B) with high energy, when forming the termination layer 21. As described above, by forming the n-type embedded layer 22 with lower career concentration under the termination layer 21, a depletion layer spreads in the end region easily at the time of the non-conductive state of a MOS transistor, and it is possible to raise the breakdown voltage of the end region more.

Third Embodiment

Next, the third embodiment of the present invention will be explained with reference to FIG. 4. In FIG. 4, the same numerals are given to the same components as FIG. 3, and these components have the same structures and functions. Therefore, the detailed explanation thereof is omitted hereinbelow.

This embodiment is different from the second embodiment in that the termination layer 21 is not formed in the end region, and only the n-type embedded layer 22 is formed in the bottom of the epitaxial layer 12. The p-type base layer 14 is extended to the end region. Also in this embodiment, if the career concentration of the n-type embedded layer 22 is set low, it is possible to extend a depletion layer close to the silicon substrate 11 at the time of the non-conductive state of a MOS transistor. This may maintain the breakdown voltage of the end region high enough compared to that in the element region.

Although the embodiments of the present invention has been explained, various changes, additions or the like are possible for the present invention without departing from the scope thereof.

Claims (8)

1. A semiconductor device comprising:
a first semiconductor layer of a first conductivity type;
an epitaxial layer of a first conductivity type formed in the surface on the first semiconductor layer;
a base layer of a second conductivity type formed on the surface of the epitaxial layer;
column layers of a second conductivity type repeatedly formed in the epitaxial layer under the base layer at a certain interval;
a diffusion layer of a first conductivity type formed selectively in the base layer; trenches formed so as to penetrate the base layer to reach the epitaxial layer;
gate electrodes formed in the trenches via a gate insulation film formed on an inner wall of the trench;
a first main electrode connected to the back side of the first semiconductor layer;
a second main electrode connected to the diffusion layer and the base layer; and
a termination layer of a second conductivity type formed on the epitaxial layer at an end region at the perimeter of the base layer, the termination layer being formed to have a junction depth larger than that of the base layer, impurity concentration of the termination layer being set lower than the impurity concentration of the column layer,
wherein the column layers are formed exclusively under the base layer.
2. The semiconductor device according to claim 1, wherein the width of the termination layer is larger than the width of the column layer.
3. The semiconductor device according to claim 1, wherein a junction depth of the termination layer is set as 40% or more of the thickness of the epitaxial layer.
4. The semiconductor device according to claim 1, further comprising second trenches formed in a surface of the base layer over the column layers.
5. The semiconductor device according to claim 4, further comprising a contact layer of a second conductivity type formed in the bottom of the second trenches.
6. The semiconductor device according to claim 1, further comprising a field plate insulation film formed over the termination layer, the second main electrode extending over the field plate insulation film.
7. The semiconductor device according to claim 1, further comprising an embedded layer of a first conductivity type with impurities concentration lower than the impurity concentration of the epitaxial layer under termination layer.
8. A semiconductor device comprising:
a first semiconductor layer of a first conductivity type;
an epitaxial layer of a first conductivity type formed in the surface on the first semiconductor layer;
a base layer of a second conductivity type formed on the surface of the epitaxial layer;
column layers of a second conductivity type repeatedly formed in the epitaxial layer under the base layer at a certain interval;
a diffusion layer of a first conductivity type formed selectively in the base layer;
trenches formed so as to penetrate the base layer to reach the epitaxial layer;
gate electrodes formed in the trenches via a gate insulation film formed on an inner wall of the trench;
a first main electrode connected to the back side of the first semiconductor layer;
a second main electrode connected to the diffusion layer and the base layer; and
a semiconductor layer of a first conductivity type formed under the base layer at the perimeter of the column layer at an outermost portion and having an impurity concentration lower than the epitaxial layer.
US11/674,337 2006-02-20 2007-02-13 Trench gate type MOS transistor semiconductor device Expired - Fee Related US7485921B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2006041954A JP2007221024A (en) 2006-02-20 2006-02-20 Semiconductor device
JP2006-41954 2006-02-20

Publications (2)

Publication Number Publication Date
US20070194375A1 US20070194375A1 (en) 2007-08-23
US7485921B2 true US7485921B2 (en) 2009-02-03

Family

ID=38427319

Family Applications (1)

Application Number Title Priority Date Filing Date
US11/674,337 Expired - Fee Related US7485921B2 (en) 2006-02-20 2007-02-13 Trench gate type MOS transistor semiconductor device

Country Status (2)

Country Link
US (1) US7485921B2 (en)
JP (1) JP2007221024A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090032875A1 (en) * 2007-08-03 2009-02-05 Kabushiki Kaisha Toshiba Semiconductor device
US20120061753A1 (en) * 2010-09-09 2012-03-15 Kabushiki Kaisha Toshiba Semiconductor device
US9310425B2 (en) 2011-07-01 2016-04-12 Taiwan Semiconductor Manufacturing Company, Ltd. Reliability assessment of capacitor device
US20160181372A1 (en) * 2013-07-26 2016-06-23 Sumitomo Electric Industries, Ltd. Silicon carbide semiconductor device and method for manufacturing same
US9923091B2 (en) 2016-03-14 2018-03-20 Renesas Electronics Corporation Semiconductor device including power MOS transistor

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007221024A (en) 2006-02-20 2007-08-30 Toshiba Corp Semiconductor device
JP5196766B2 (en) 2006-11-20 2013-05-15 株式会社東芝 Semiconductor device
US20080116512A1 (en) * 2006-11-21 2008-05-22 Kabushiki Kaisha Toshiba Semiconductor device and method of making the same
JP5165995B2 (en) * 2007-11-07 2013-03-21 株式会社東芝 Semiconductor device and manufacturing method thereof
JP4788749B2 (en) * 2007-11-09 2011-10-05 株式会社デンソー Semiconductor device
JP5721308B2 (en) * 2008-03-26 2015-05-20 ローム株式会社 Semiconductor device
JP4640439B2 (en) 2008-04-17 2011-03-02 株式会社デンソー Silicon carbide semiconductor device
KR101039564B1 (en) * 2009-08-10 2011-06-09 (주) 트리노테크놀로지 Trench gate semiconductor device
KR101353903B1 (en) * 2009-08-28 2014-01-22 산켄덴키 가부시키가이샤 Semiconductor device
JP2012043955A (en) * 2010-08-18 2012-03-01 Toshiba Corp Semiconductor device and method of manufacturing the same
JP2012069824A (en) * 2010-09-24 2012-04-05 Seiko Instruments Inc Semiconductor device and manufacturing method therefor
JP2012074441A (en) * 2010-09-28 2012-04-12 Toshiba Corp Semiconductor device for power
TWI470802B (en) * 2011-12-21 2015-01-21 Ind Tech Res Inst Trench metal oxide semiconductor transistor device and manufacturing method thereof
TWI521719B (en) 2012-06-27 2016-02-11 財團法人工業技術研究院 Double-recessed trench schottky barrier device
KR20140022518A (en) * 2012-08-13 2014-02-25 삼성전자주식회사 Semiconductor device and fabricating method thereof
KR101397784B1 (en) * 2012-11-21 2014-05-20 삼성전기주식회사 Insulated gate bipolar transistor
WO2014207793A1 (en) * 2013-06-24 2014-12-31 株式会社日立製作所 Semiconductor device, and method for manufacturing same
JP6300638B2 (en) * 2014-05-26 2018-03-28 ルネサスエレクトロニクス株式会社 Semiconductor device
DE102015110484A1 (en) 2015-06-30 2017-01-05 Infineon Technologies Austria Ag Semiconductor devices and methods of forming a semiconductor device
CN105633127B (en) * 2015-12-31 2019-03-29 电子科技大学 A kind of super node MOSFET
JP2018019045A (en) * 2016-07-29 2018-02-01 富士電機株式会社 Silicon carbide semiconductor device and silicon carbide semiconductor device manufacturing method

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5034341A (en) * 1988-03-08 1991-07-23 Oki Electric Industry Co., Ltd. Method of making a memory cell array structure
US5894149A (en) * 1996-04-11 1999-04-13 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having high breakdown voltage and method of manufacturing the same
US6300171B1 (en) 1998-12-09 2001-10-09 Stmicroelectronics S.R.L. Method of manufacturing an integrated edge structure for high voltage semiconductor devices, and related integrated edge structure
JP2003273355A (en) 2002-03-18 2003-09-26 Toshiba Corp Semiconductor element and method for manufacturing the same
US6639260B2 (en) * 2000-12-18 2003-10-28 Denso Corporation Semiconductor device having a vertical semiconductor element
US20060043478A1 (en) 2004-08-31 2006-03-02 Denso Corporation Semiconductor device having super junction structure and method for manufacturing the same
US20070194375A1 (en) 2006-02-20 2007-08-23 Kabushiki Kaisha Toshiba Semiconductor device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3951522B2 (en) * 1998-11-11 2007-08-01 富士電機デバイステクノロジー株式会社 Super junction semiconductor device
US6197095B1 (en) * 1999-02-16 2001-03-06 John C. Ditria Subsea multiphase fluid separating system and method
JP3940518B2 (en) * 1999-03-10 2007-07-04 株式会社東芝 High voltage semiconductor element
JP2005101334A (en) * 2003-09-25 2005-04-14 Sanyo Electric Co Ltd Semiconductor device and its manufacturing method
JP4940546B2 (en) * 2004-12-13 2012-05-30 株式会社デンソー Semiconductor device

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5034341A (en) * 1988-03-08 1991-07-23 Oki Electric Industry Co., Ltd. Method of making a memory cell array structure
US5894149A (en) * 1996-04-11 1999-04-13 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having high breakdown voltage and method of manufacturing the same
US6300171B1 (en) 1998-12-09 2001-10-09 Stmicroelectronics S.R.L. Method of manufacturing an integrated edge structure for high voltage semiconductor devices, and related integrated edge structure
US6639260B2 (en) * 2000-12-18 2003-10-28 Denso Corporation Semiconductor device having a vertical semiconductor element
JP2003273355A (en) 2002-03-18 2003-09-26 Toshiba Corp Semiconductor element and method for manufacturing the same
US6844592B2 (en) 2002-03-18 2005-01-18 Kabushiki Kaisha Toshiba Semiconductor device with super junction region
US20060043478A1 (en) 2004-08-31 2006-03-02 Denso Corporation Semiconductor device having super junction structure and method for manufacturing the same
US20070194375A1 (en) 2006-02-20 2007-08-23 Kabushiki Kaisha Toshiba Semiconductor device

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
U.S. Appl. No. 11/936,412, filed Nov. 7, 2007, Ono, et al.
U.S. Appl. No. 11/943,181, filed Nov. 20, 2007, Kawaguchi, et al.

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090032875A1 (en) * 2007-08-03 2009-02-05 Kabushiki Kaisha Toshiba Semiconductor device
US8008715B2 (en) * 2007-08-03 2011-08-30 Kabushiki Kaisha Toshiba Semiconductor device
US20120061753A1 (en) * 2010-09-09 2012-03-15 Kabushiki Kaisha Toshiba Semiconductor device
US8629505B2 (en) * 2010-09-09 2014-01-14 Kabushiki Kaisha Toshiba Semiconductor device
US8884364B2 (en) 2010-09-09 2014-11-11 Kabushiki Kaisha Toshiba Semiconductor device with field-plate electrode
US9310425B2 (en) 2011-07-01 2016-04-12 Taiwan Semiconductor Manufacturing Company, Ltd. Reliability assessment of capacitor device
US20160181372A1 (en) * 2013-07-26 2016-06-23 Sumitomo Electric Industries, Ltd. Silicon carbide semiconductor device and method for manufacturing same
US10192960B2 (en) * 2013-07-26 2019-01-29 Sumitomo Electric Industries, Ltd. Silicon carbide semiconductor device and method for manufacturing same
US9923091B2 (en) 2016-03-14 2018-03-20 Renesas Electronics Corporation Semiconductor device including power MOS transistor

Also Published As

Publication number Publication date
JP2007221024A (en) 2007-08-30
US20070194375A1 (en) 2007-08-23

Similar Documents

Publication Publication Date Title
US9899474B2 (en) Nanotube semiconductor devices
US9601334B2 (en) Semiconductor device and the method of manufacturing the same
US9515067B2 (en) Semiconductor device having switching element and free wheel diode and method for controlling the same
US9842917B2 (en) Methods of operating power semiconductor devices and structures
US9076861B2 (en) Schottky and MOSFET+Schottky structures, devices, and methods
US8294235B2 (en) Edge termination with improved breakdown voltage
US8742401B2 (en) Field effect transistor with gated and non-gated trenches
US8441046B2 (en) Topside structures for an insulated gate bipolar transistor (IGBT) device to achieve improved device performances
US7723783B2 (en) Semiconductor device
US7713822B2 (en) Method of forming high density trench FET with integrated Schottky diode
EP1113501B1 (en) Power MOSFET having a trench gate electrode
US7642597B2 (en) Power semiconductor device
US8466025B2 (en) Semiconductor device structures and related processes
CN101971304B (en) Structure and method for forming shielded gate trench fet with multiple channels
DE19848828C2 (en) Semiconductor device with low forward voltage and high blocking capability
KR100305978B1 (en) Field-effect trench transistors with lightly doped epitaxial regions on the surface of transistors
US9627520B2 (en) MOS transistor having a cell array edge zone arranged partially below and having an interface with a trench in an edge region of the cell array
JP4599379B2 (en) Trench gate type semiconductor device
JP4198469B2 (en) Power device and manufacturing method thereof
US10720510B2 (en) Lateral transistors and methods with low-voltage-drop shunt to body diode
US9105716B2 (en) Semiconductor device
US8247329B2 (en) Nanotube semiconductor devices
JP4764987B2 (en) Super junction semiconductor device
US7755138B2 (en) Semiconductor device
US7368777B2 (en) Accumulation device with charge balance structure and method of forming the same

Legal Events

Date Code Title Description
AS Assignment

Owner name: KABUSHIKI KAISHA TOSHIBA, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KAWAGUCHI, YUSUKE;YAMAGUCHI, YOSHIHIRO;ONO, SYOTARO;AND OTHERS;REEL/FRAME:019086/0265;SIGNING DATES FROM 20070223 TO 20070226

FPAY Fee payment

Year of fee payment: 4

REMI Maintenance fee reminder mailed
LAPS Lapse for failure to pay maintenance fees
STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Expired due to failure to pay maintenance fee

Effective date: 20170203