CN1848455B - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN1848455B
CN1848455B CN2006100820326A CN200610082032A CN1848455B CN 1848455 B CN1848455 B CN 1848455B CN 2006100820326 A CN2006100820326 A CN 2006100820326A CN 200610082032 A CN200610082032 A CN 200610082032A CN 1848455 B CN1848455 B CN 1848455B
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理崎智光
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Ablic Inc
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Abstract

半导体器件及其制造方法提供了一种具有如下结构的半导体器件：在距n型或p型的半导体衬底表面的一定深度设置高阻抗p型半导体阱区；多个沟槽从阱区表面延伸到某一深度；栅绝缘膜形成在其上形成了沟槽的凹/凸部分表面上；栅电极嵌入在沟槽内。该半导体器件包括：栅电极膜，其设置在与嵌入凹凸部分区域中的沟槽中的栅电极相接触的衬底表面上，除了沟槽两端附近的部分之外；以及为两个低阻抗n型半导体层的源区和漏区，它们位于除了栅电极膜下部的阱区中，位置比阱区深度浅。

Description

半导体器件及其制造方法
技术领域
本发明涉及一种需要具有高驱动性能的半导体器件。
背景技术
精细加工技术逐年来充分的应用使得能够在不降低性能的情况下制造小半导体器件。这一趋势也适用于具有高驱动性能的半导体元件。在精细加工技术的最佳应用下，已经实现了每单位面积元件的开态电阻的降低。然而，还有一个事实，由元件的小型化导致的耐压降低，阻碍了驱动性能的进一步提高。为了解决小型化和耐压之间的平衡已提出了具有不同结构的元件。沟槽栅MOS晶体管是具有高耐压和高驱动性能的功率MOSFET的例子，其成为了现在的主流。在具有高耐压和高驱动性能的DMOS晶体管中，沟槽栅MOS晶体管具有最高的集成封装密度。然而，沟槽栅MOS晶体管具有纵向的MOS结构，其中电流在衬底的深度方向流动。晶体管作为元件自身具有极好的性能，但是当与其它IC元件一起集成在芯片上的时候，存在缺点。当考虑到与其它IC一起装配在芯片上的时候，不能忽略传统的横向MOS结构。
已提议了横向沟槽栅晶体管作为能够在不降低耐压的情况下降低每单位面积的开态电阻的方法。在这种晶体管中，栅极部分具有包含凸起部分和凹陷部分的结构，以获得更大的栅极宽度(例如，参见JP3405681B)。图4A到4D是该传统技术的概念图。此处，图4A是平面图，图4B是沿图4A中4B-4B’线的截面图，图4C是沿图4A中4C-4C’线的截面图，以及图4D是沿图4A中4D-4D’线的截面图。此处，为便于观察图4A，透明地示出了沟槽外的栅电极003和栅绝缘膜004。粗线表示栅电极003的边缘。这一技术揭示了，在栅极部分003含有沟槽结构的情况下，横向MOS晶体管每单位面积栅极宽度的扩展，以及导致的其开态电阻的降低。
然而，上述技术有两个问题。
(1)将说明第一个问题。图5是仅仅去掉图4A到4D中的源区001或漏区002得到的鸟瞰图。此处，栅氧化膜004和栅电极003没有示出。在图5中，以阴影表示与沟槽壁相接触的源区001或漏区002的表面，是与沟道部分接触的部分020。与沟道部分接触的部分020存在于与沟槽壁接触的源区001或漏区002全部表面的每一个上。就是说在图4A到4D的结构中，长度d1、w1和l2的尺寸决定了源区001或漏区002与沟道部分之间的接触面积。当接触面积小时，该面积变成了如由图4D(电流密度在源区和漏区中变得密集)中示出的电流019表示的瓶颈，其阻碍了开态电阻降低。为了增大接触面积，增大d1、w1和l2的长度尺寸就足够了。
首先，考虑长度d1。长度d1对应于在以常规离子注入形成源区001和漏区002中每一个的情况下源区001与漏区002每个的深度，通常较浅，几千
Figure GA20171822200610082032601D00021
其深度有一定的限制。
当沟槽凸起部分007的宽度保持不变时，对应于沟槽凹陷部分008宽度的w1越长，导致每单位面积沟槽数量减小和垂直接触面积减小，导致栅极宽度减小。因此增大w1的长度是不可能的。
至于延长源区001或漏区002与沟槽之间的交叠长度l2的方法，显然在不改变栅极长度延长l2的情况下，面积相应地增大。进一步，当假设源区001和漏区002以与栅电极003自对准的方式形成时，为了延长l2，考虑缩短l1的方法，或者增加源区001和漏区002的杂质扩散长度的方法；由于缩短l1有一定的局限，因此应当采用通过杂质扩散而延长l2的方法。然而，该方法在长度上也有限制，并且有一定风险，例如由于杂质的过度扩散导致源区001或者漏区002的浓度降低。因此，该方法的实际实现是困难的。即，在传统技术中在不改变元件面积的情况下增加接触面积以降低MOS晶体管的开态电阻是困难的。
(2)第二个问题是沟槽深度的限制。增加沟槽的深度可进一步增加每单位面积的栅极宽度。然而，这仅适用于阱区005中的情况。用常规方法形成的阱区005有深度的限制。这样，沟槽不可能比阱区005更深。如果沟槽被制作得比阱区005深，电流将泄漏到衬底。
发明内容
为了解决上述两个问题提出了本发明，并由此提供一种具有高驱动性能的横向MOS晶体管。该具有高驱动性能的横向MOS晶体管包括在长度方向与栅极长度方向平行的沟槽中形成的栅电极，其具有长的每单位面积栅极宽度。本发明的横向MOS晶体管在不增加平面元件面积的情况下获得了低开态电阻和高驱动性能。
(1)一种半导体器件，在其结构中：距n型或p型的半导体衬底表面一定深度设置高阻抗p型半导体阱区；多个沟槽从阱区表面延伸到某一深度；栅绝缘膜形成在其上形成了沟槽的凹凸部分的表面上；栅电极嵌入在沟槽中，并且包括设置栅电极膜，该栅电极膜设置在与嵌入凹凸部分区域中的沟槽中的栅电极相接触的衬底表面上，除了沟槽两端附近的部分之外；以及为两个低阻抗n型半导体层的源区和漏区，它们位于除了栅电极膜下部的阱区中，位置比阱区深度浅。
(2)半导体器件的制造方法，包括：形成沟槽区；以及通过多方向倾斜离子注入形成阱区。
(3)半导体器件的制造方法，包括形成阱区的步骤，该形成阱区的步骤包括：在半导体衬底表面上通过离子注入形成p型半导体区域；通过外延生长在半导体衬底表面上形成半导体；以及在该通过外延生长形成的半导体表面上通过离子注入形成p型半导体区。
依照本发明，由于沟槽两端附近的部分变成源漏区，所以增加源、漏区与沟道区之间的接触面积能够降低开态电阻。
依照本发明，在沟槽形成之后立即使用多方向倾斜离子注入形成阱区。这样阱区形成得比凹陷部分的底面更深。因此与在形成沟槽之前形成阱区的方法相比，沟槽可以形成得更深。因此，能够获得更大的单位面积栅极宽度。
进一步，依照本发明，通过离子注入在半导体衬底表面和外延膜之间形成通过第二导电型半导体区域的热扩散形成的连接，其中在对外延形成沟槽结构后通过倾斜离子注入形成第二导电型半导体区域。这样，阱可以制造得更深。因此，凹陷部分的底表面可以制造得更深，从而单位面积的栅极宽度能够进一步增加。
附图说明
在附图中：
图1A是本发明基本结构的平面图；
图1B是本发明基本结构的鸟瞰图；
图2A是沿图1A中2A-2A’线的截面图；
图2B是沿图1A中2B-2B’线的截面图；
图3A是沿图1A中3A-3A’线的截面图；
图3B是沿图1A中3B-3B’线的截面图；
图4A是传统技术实施例的平面图；
图4B是沿图4A中4B-4B’线的传统技术实施例的截面图；
图4C是沿图4A中4C-4C’线的传统技术实施例的截面图；
图4D是沿图4A中4D-4D’线的传统技术实施例的截面图；
图5是图4中示出的源区或漏区的鸟瞰图，其中阴影部分表示沟道；
图6A-6C是依照本发明的制造过程的鸟瞰图；
图7是当d1＜d2的情况下沿图1A中2B-2B’线的截面图；
图8是依照本发明的DDD结构的鸟瞰图；
图9是依照本发明的LDMOS结构的鸟瞰图；
图10A是紧接多方向倾斜离子注入之后沟槽深度相对较浅的结构的截面图；
图10B是多方向倾斜离子注入之后离子热扩散情况下沟槽深度相对较浅的结构的截面图；
图11A是紧接多方向倾斜离子注入之后沟槽深度更深并且离子注入角度θ更大的结构的截面图；
图11B是多方向倾斜离子注入之后离子热扩散的情况下沟槽深度更深并且离子注入角度θ更大的结构的截面图；
图12是沟槽深度更深并且离子注入角度θ更小的结构的截面图；
图13A的截面图示出了在通过外延生长和倾斜离子注入制造阱的方法中，在半导体衬底表面中注入了离子的结构；
图13B的截面图示出了在通过外延生长和倾斜离子注入制造阱的方法中，在图13A的衬底表面上使用外延生长形成了半导体膜的结构；
图13C的截面图示出了在通过外延生长和倾斜离子注入制造阱的方法中，在图13B中形成了沟槽结构的结构；
图13D的截面图示出了在通过外延生长和倾斜离子注入制造阱的方法中，在图13C中进行了多方向倾斜注入离子的结构；以及
图13E的截面图示出了在通过外延生长和倾斜离子注入制造阱的方法中，在图13D中进行热扩散之后的结构。
具体实施方式
实施例
图1A和1B每个都显示了本发明的典型实施例。图1A是发明的平面图，图1B是图1A的鸟瞰图。参考图1A，为了便于观察，使沟槽外的栅电极003和栅绝缘膜004为透明的。粗线表示栅电极003的边缘。并且，图2A是沿图1A中2A-2A’线的截面图，图2B是沿图1A中2B-2B’线的截面图。图3A是沿图1A中3A-3A’线的截面图，图3B是沿图1A中3B-3B’线的截面图。在图4所示的传统实例中，栅电极003覆盖整个沟槽部分。相反地，在图1到3所示的本发明中，沟槽两端附近的部分未被栅电极003覆盖。在该结构中，更长的l3(更长的l2)能够提供源、漏区与沟道区更大的接触面积，其解决了前述的第一个问题。
接下来，描述制造方法。图6A到6C每个都显示了依照本发明的制造方法的实例。如图6A所示，在其表面附近形成了阱区005的高电阻n型或p型的半导体衬底006上形成多个沟槽。在该示例中，由于沟槽深度比阱区005的深度更深将导致在衬底中有漏电流，因此很难获得深沟槽。然而，当形成阱区005的离子注入是按图10A所示在形成沟槽区之后立刻从多方向进行的倾斜离子注入时，能够进一步增加沟槽深度。这是因为通过左、右倾斜离子注入017将离子注入到沟槽的侧面和上表面，通过从前、后方的倾斜离子注入(未示出)将离子注入到沟槽上表面和底面，并且通过图10B所示的随后的热扩散，阱区的形成深度增加，超过沟槽底部。在上述方法中，与在形成阱区005之后再形成沟槽区的方法相比，可确保形成的沟槽深度增加。结果，能够获得更大的单位面积栅极宽度，且前述的第二个问题得以消除。
即使在上述方法中，沟槽深度仍存在限制。简单地增加沟槽深度而不改变倾斜离子注入的角度θ，会在沟槽底部的侧面形成没有注入离子的区域，如图11A中所示，导致即使热扩散之后阱区005对沟槽的包围仍不足，如图11B所示。另一方面，为了将离子注入到沟槽底部的沟槽侧面而进行的较小的角度θ的倾斜离子注入会导致沟槽侧面的离子注入不足，如图12所示，导致热扩散之后阱的离子浓度分布不均匀。
然而，结合倾斜离子注入和外延生长可以使沟槽深度增加到超过该限制。如图13A所示，在半导体衬底006表面上形成区域016，对该区域016进行离子注入以具有同样的导电类型。接着，如图13B所示，通过外延生长沉积半导体膜018。之后，如图13C所示形成沟槽结构，并且如图13D所示进行多方向倾斜离子注入。由于离子注入层存在于外延层和半导体衬底之间，所以通过热扩散能够形成环绕所有沟槽的阱，如图13E所示。用这一方法，沟槽宽度可以进一步增加，从而能够获得更大的单位面积栅极宽度。
接着，如图6B所示，氧化衬底表面，继而形成栅绝缘膜004和栅电极膜003，蚀刻除了将成为沟道的区域上的栅电极膜003外的栅电极膜003。这时，长度为l3的沟槽两端的上部上的栅电极003也被蚀刻封装到不会由于如图5所示的源、漏区与沟道的接触面积减少而阻止开态电阻减小的程度，并且被嵌入沟槽内使得栅电极003的厚度满足d2＞0。
随后，如图6C所示，通过离子注入和杂质扩散形成源区001和漏区002。在d1＜d2并且源区001和漏区002相隔沟道部分的情况下，可以通过倾斜离子注入形成源和漏区，如图7所示。在这一例子中，图7是沿图1A中2B-2B’线的截面图。最后，在该结构表面上形成钝化膜，如图6C所示，在源、栅、漏部分限定接触孔，并抽头相应的电极以完成该过程。在上述实施例中，不言自明，改变导电类型可以用同样的方法形成p沟道MOS结构。并且，双阱技术的应用使得能够在一个芯片上制造具有高驱动性能的CMOS结构，和生产混合型IC。以上描述给出了本发明的基本结构和基本制造方法。
现在，将描述该基本结构的应用。
在普通的平面MOS晶体管中，存在为了提高耐压的基于基本结构的各种结构。在本发明中，通过将图8所示的传统技术DDD(双扩散漏)结构、或图9所示的LDMOS(横向双扩散MOS)结构、或类似结构与该基本结构(图1)相结合，可以很容易获得耐压的提高。
并且，当MOS晶体管处于导通状态时，图1所示的凹陷部分007的宽度大约是
Figure GA20171822200610082032601D00061
由此凹陷部分的内部完全耗尽，亚阈值特性得以提高。从而，减少了源漏之间的泄漏电流，可以降低阈值电压，因而进一步提高了驱动性能。
本发明的实施例已描述，然而本发明不仅仅局限于上述实施例，且在不脱离发明要旨的范围内可以修改该实施例。

Claims (9)

1.一种半导体器件，包括：
具有高阻抗的第一导电类型的阱区，设置在距半导体衬底表面的一定深度；
多个沟槽，从所述阱区的表面延伸到所述阱区中；
栅绝缘膜，设置在所述多个沟槽所形成的凹凸部分的表面上；
栅电极，嵌入到所述多个沟槽中；
栅电极膜，设置在与嵌入所述凹凸部分中的所述多个沟槽中的栅电极相接触的半导体衬底表面上，除了所述多个沟槽的两端附近的部分之外；以及
具有低阻抗的第二导电类型的源区和漏区，设置在除了所述栅电极膜下部的阱区内，位置比所述阱区的深度浅，
其中，所述多个沟槽的延伸方向平行于从所述源区到所述漏区的方向。
2.根据权利要求1的半导体器件，进一步包括DDD结构。
3.根据权利要求1的半导体器件，进一步包括LDMOS结构。
4.根据权利要求1的半导体器件，其中，所述凹凸部分的凸起部分的宽度大约为
5.根据权利要求1的半导体器件，其中，所述凹凸部分的凸起部分的内部具有当所述半导体器件处于导通状态时变得完全耗尽的宽度。
6.根据权利要求1的半导体器件，其中，所述该半导体器件与双阱技术相结合。
7.根据权利要求1的半导体器件，其中，导电类型是相反的。
8.一种制造根据权利要求1的半导体器件的方法，包括以下步骤：
形成所述沟槽区域；以及
通过多方向的倾斜离子注入形成所述阱区。
9.一种制造根据权利要求1的半导体器件的方法，具有形成所述阱区的步骤，所述形成所述阱区的步骤包括以下步骤：
在所述半导体衬底的表面上通过离子注入形成具有第一导电类型的第一半导体区域；
通过外延生长在所述半导体衬底的表面上形成半导体；
形成多个沟槽，所述多个沟槽从所述外延半导体表面延伸到所述半导体衬底；以及
通过多方向的倾斜离子注入形成具有与所述第一半导体区域相同的导电类型的第二半导体区域，以便在热扩散之后形成阱区。
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