JP2006294645A - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 55
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 238000005468 ion implantation Methods 0.000 claims description 31
- 239000000758 substrate Substances 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 18
- 238000005516 engineering process Methods 0.000 claims description 6
- 235000004522 Pentaglottis sempervirens Nutrition 0.000 abstract description 8
- 240000004050 Pentaglottis sempervirens Species 0.000 abstract description 7
- 150000002500 ions Chemical class 0.000 description 7
- 230000015556 catabolic process Effects 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 6
- 239000012535 impurity Substances 0.000 description 4
- 230000007423 decrease Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
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Abstract
【解決手段】 ゲート長方向に対し水平に複数本のトレンチ007を形成することによって単位面積当たりのゲート幅を増大させる高駆動能力横型MOSにおいて、図((a)は平面図、(b)は鳥瞰図)に示すようにトレンチ両端付近がソース領域001及びドレイン領域002となるため、ソース領域001及びドレイン領域002とチャネル領域の接触面積を大きくすることができ、オン抵抗の低減が可能となる。
【選択図】 図1
Description
(1)1つ目の問題点を示す。図5は図4のソース領域001もしくはドレイン領域002のみを取り出した鳥瞰図である。ここでゲート酸化膜004とゲート電極003は図示していない。図3のソース領域001もしくはドレイン領域002において、点線で表したトレンチ壁に接した極表面の色の濃い部分がチャネル部と接する部分020である。このチャネル部と接する部分020はトレンチ壁に接触しているソース領域001もしくはドレイン領域002の極表面全てに存在する。つまり、図4の構造においてソース領域001もしくはドレイン領域002と前記チャネル部の接触面積は寸法d1、w1、l2の長さによって決定される。前記接触面積が小さい場合、その部分が図4(d)の電流019が示すようにボトルネックとなり(電流密度がソース領域及びドレイン領域で密となり)、オン抵抗低減を阻害する。前記接触面積を大きくするには寸法d1、w1、l2の長さを長く取ればよい。まず、寸法d1について考えると、ソース領域001及びドレイン領域001を通常のイオン注入によって形成した場合のソース領域001及びドレイン領域001の深さである寸法d1は一般に数千Aと浅く、長くするには限界がある。前記トレンチの凸部幅を変えずに前記トレンチの凹部幅である寸法w1を長くすると、単位平面積あたりの前記トレンチ数が減少し垂直な接触面積が減少することとなり、ゲート幅が短くなるため寸法w1を長くすることができない。
(2)2つ目の問題点は、トレンチ深さに限界があることである。トレンチ深さを深くすることで単位平面積あたりのゲート幅を更に増加させる事が可能であるが、それはウェル領域005内に限った話で、一般的方法で作成するウェル領域005の深さには限界があるため、ウェル領域005の深さ以上にトレンチを深くすることはできない。仮にウェル領域005の深さ以上にトレンチを深くすると、基板に電流が漏れてしまう。
(2)DDD構造を有する(1)に記載の半導体装置とした。
(3)LDMOS構造を有する(1)に記載の半導体装置とした。
(4)前記凹凸部の凸部の幅が1000A程度の(1)から(3)に記載のいずれかの半導体装置とした。
(5)ツインウェル技術を併合した(1)から(4)に記載のいずれかの半導体装置とした。
(6)導電型を反転した(1)から(5)に記載のいずれかの半導体装置とした。
(7)(1)から(6)に記載の半導体装置において、前記トレンチ領域形成後に多方向からによる斜めイオン注入によって前記ウェル領域を形成する半導体装置の製造法とした。
(8)(1)から(6)に記載の半導体装置において、前記半導体基板の表面にイオン注入によってp型半導体領域を作成する工程と、前記半導体基板の表面に半導体をエピタキシャル成長させる工程と、前記のエピタキシャル成長させた半導体表面にイオン注入によってp型半導体領域を作成する工程により、前記ウェル領域を作成する工程を有する半導体装置の製造法とした。
本発明(請求項2〜3)によれば、上記の構造及び製造法をベースにし、DDDやLDMOSなどの構造を採用するといった従来技術との併合が可能であるため、容易に耐圧の向上が図れる。
002 ドレイン領域
003 ゲート電極
004 ゲート絶縁膜
005 ウェル領域
006 高抵抗半導体基板
007 凸部
008 凹部
009 高抵抗n型半導体領域
010 高抵抗n型半導体基板
016 ウェルと同じ導電型となるようイオン注入を施された領域
017 イオン注入の方向
018 エピタキシャル成長による半導体膜
019 電流
020 チャネル部と接している部分
Claims (9)
- 半導体基板表面から一定の深さに設けられた高抵抗第一導電型半導体のウェル領域と、前記ウェル領域の表面から途中の深さまで達する複数本のトレンチと、前記トレンチが形成する凹凸部の表面に設けられたゲート絶縁膜と、前記トレンチ内部に埋め込まれたゲート電極と、前記トレンチ両端付近を除く前記凹凸部領域において前記トレンチ内部に埋め込まれたゲート電極と接触して基板表面に設けられたゲート電極膜と、前記ゲート電極膜の下部を除く前記ウェル領域において前記ウェル領域の深さより浅く設けられた2つの低抵抗第二導電型半導体層であるソース領域とドレイン領域を有する半導体装置。
- DDD構造を有する請求項1に記載の半導体装置。
- LDMOS構造を有する請求項1に記載の半導体装置。
- 前記凹凸部の凸部の幅が1000A程度の請求項1から3に記載のいずれかの半導体装置。
- 前記凹凸部の凸部は前記半導体装置がオン状態のときに凸部内部が全て空乏化する幅である請求項1から3に記載のいずれかの半導体装置。
- ツインウェル技術を併合した請求項1から請求項5に記載のいずれかの半導体装置。
- 導電型を反転した請求項1から請求項6に記載のいずれかの半導体装置。
- 請求項1から請求項7に記載の半導体装置の製造方法において、前記トレンチ領域形成後に多方向からによる斜めイオン注入によって前記ウェル領域を形成する半導体装置の製造方法。
- 請求項1から請求項7に記載の半導体装置の製造方法において、前記半導体基板の表面にイオン注入によって一導電型の第一の半導体領域を作成する工程と、前記半導体基板の表面に半導体をエピタキシャル成長させる工程と、前記のエピタキシャル成長させた半導体表面にイオン注入によって前記第一の半導体領域と同じ導電型を有する第二の半導体領域を作成する工程により、前記ウェル領域を作成する工程を有する半導体装置の製造方法。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005108978A JP4976658B2 (ja) | 2005-04-05 | 2005-04-05 | 半導体装置の製造方法 |
US11/397,470 US7492035B2 (en) | 2005-04-05 | 2006-04-04 | Semiconductor device and method of manufacturing the same |
CN2006100820326A CN1848455B (zh) | 2005-04-05 | 2006-04-05 | 半导体器件及其制造方法 |
KR1020060031053A KR101235502B1 (ko) | 2005-04-05 | 2006-04-05 | 반도체 장치 및 그 제조 방법 |
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JP2005108978A JP4976658B2 (ja) | 2005-04-05 | 2005-04-05 | 半導体装置の製造方法 |
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Cited By (6)
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JP2008192985A (ja) * | 2007-02-07 | 2008-08-21 | Seiko Instruments Inc | 半導体装置、及び半導体装置の製造方法 |
WO2009028375A1 (ja) | 2007-08-28 | 2009-03-05 | Seiko Instruments Inc. | 半導体装置及びその製造方法 |
US8207575B2 (en) | 2008-02-26 | 2012-06-26 | Seiko Instruments Inc. | Semiconductor device and method of manufacturing the same |
US8236648B2 (en) | 2007-07-27 | 2012-08-07 | Seiko Instruments Inc. | Trench MOS transistor and method of manufacturing the same |
US8436421B2 (en) | 2010-01-25 | 2013-05-07 | Renesas Electronics Corporation | Semiconductor device with trench gate transistors and method for production thereof |
US8476701B2 (en) | 2010-05-19 | 2013-07-02 | Renesas Electronics Corporation | Semiconductor device with gate electrode including a concave portion |
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US7416948B2 (en) * | 2003-12-30 | 2008-08-26 | Fairchild Semiconductor Corporation | Trench FET with improved body to gate alignment |
JP5165954B2 (ja) | 2007-07-27 | 2013-03-21 | セイコーインスツル株式会社 | 半導体装置 |
US9997599B2 (en) * | 2013-10-07 | 2018-06-12 | Purdue Research Foundation | MOS-based power semiconductor device having increased current carrying area and method of fabricating same |
US9780213B2 (en) * | 2014-04-15 | 2017-10-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device having a reversed T-shaped profile in the metal gate line-end |
JP2015207639A (ja) | 2014-04-18 | 2015-11-19 | ソニー株式会社 | 高周波スイッチ用半導体装置、高周波スイッチおよび高周波モジュール |
CN105097916A (zh) * | 2014-05-05 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Mos晶体管器件及其制作方法 |
CN105990423A (zh) * | 2015-02-02 | 2016-10-05 | 无锡华润上华半导体有限公司 | 横向双扩散场效应管 |
KR102385564B1 (ko) * | 2017-06-13 | 2022-04-12 | 삼성전자주식회사 | 반도체 소자 |
CN112614909B (zh) * | 2020-11-27 | 2022-12-27 | 中国电子科技集团公司第十三研究所 | 光导开关器件 |
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CN2468193Y (zh) * | 2001-02-27 | 2001-12-26 | 北京福创光电子股份有限公司 | 一种电流调制增益耦合激光器 |
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- 2005-04-05 JP JP2005108978A patent/JP4976658B2/ja active Active
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- 2006-04-04 US US11/397,470 patent/US7492035B2/en not_active Expired - Fee Related
- 2006-04-05 KR KR1020060031053A patent/KR101235502B1/ko active IP Right Grant
- 2006-04-05 CN CN2006100820326A patent/CN1848455B/zh not_active Expired - Fee Related
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JPH04268767A (ja) * | 1991-02-25 | 1992-09-24 | Fujitsu Ltd | 半導体装置 |
JPH11103058A (ja) * | 1997-07-31 | 1999-04-13 | Toshiba Corp | 半導体装置 |
JP2001015742A (ja) * | 1999-06-30 | 2001-01-19 | Toshiba Corp | 半導体装置 |
JP2001102574A (ja) * | 1999-09-29 | 2001-04-13 | Toshiba Corp | トレンチゲート付き半導体装置 |
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US8168494B2 (en) | 2007-02-07 | 2012-05-01 | Seiko Instruments Inc. | Trench MOS transistor and method of manufacturing the same |
KR101473003B1 (ko) * | 2007-02-07 | 2014-12-15 | 세이코 인스트루 가부시키가이샤 | 반도체 장치 및 반도체 장치의 제조 방법 |
US8803231B2 (en) | 2007-02-07 | 2014-08-12 | Seiko Instruments, Inc. | Trench MOS transistor and method of manufacturing the same |
JP2008192985A (ja) * | 2007-02-07 | 2008-08-21 | Seiko Instruments Inc | 半導体装置、及び半導体装置の製造方法 |
US8236648B2 (en) | 2007-07-27 | 2012-08-07 | Seiko Instruments Inc. | Trench MOS transistor and method of manufacturing the same |
WO2009028375A1 (ja) | 2007-08-28 | 2009-03-05 | Seiko Instruments Inc. | 半導体装置及びその製造方法 |
KR20100065152A (ko) | 2007-08-28 | 2010-06-15 | 세이코 인스트루 가부시키가이샤 | 반도체 장치 및 그 제조 방법 |
EP2187431A1 (en) * | 2007-08-28 | 2010-05-19 | Seiko Instruments Inc. | Semiconductor device and method for manufacturing the same |
US8390061B2 (en) | 2007-08-28 | 2013-03-05 | Seiko Instruments Inc. | Semiconductor device having a trench structure and method for manufacturing the same |
JP2009054840A (ja) * | 2007-08-28 | 2009-03-12 | Seiko Instruments Inc | 半導体装置及びその製造方法 |
EP2187431A4 (en) * | 2007-08-28 | 2012-02-15 | Seiko Instr Inc | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME |
KR20160075873A (ko) | 2007-08-28 | 2016-06-29 | 에스아이아이 세미컨덕터 가부시키가이샤 | 반도체 장치 및 그 제조 방법 |
KR101635648B1 (ko) | 2007-08-28 | 2016-07-01 | 에스아이아이 세미컨덕터 가부시키가이샤 | 반도체 장치 및 그 제조 방법 |
KR101747615B1 (ko) | 2007-08-28 | 2017-06-14 | 에스아이아이 세미컨덕터 가부시키가이샤 | 반도체 장치 및 그 제조 방법 |
US8207575B2 (en) | 2008-02-26 | 2012-06-26 | Seiko Instruments Inc. | Semiconductor device and method of manufacturing the same |
US8436421B2 (en) | 2010-01-25 | 2013-05-07 | Renesas Electronics Corporation | Semiconductor device with trench gate transistors and method for production thereof |
US8476701B2 (en) | 2010-05-19 | 2013-07-02 | Renesas Electronics Corporation | Semiconductor device with gate electrode including a concave portion |
US8871592B2 (en) | 2010-05-19 | 2014-10-28 | Renesas Electronics Corporation | Method of manufacturing a semiconductor device including concave portion |
Also Published As
Publication number | Publication date |
---|---|
US20060223253A1 (en) | 2006-10-05 |
KR101235502B1 (ko) | 2013-02-20 |
US7492035B2 (en) | 2009-02-17 |
CN1848455A (zh) | 2006-10-18 |
CN1848455B (zh) | 2010-09-01 |
JP4976658B2 (ja) | 2012-07-18 |
KR20060107352A (ko) | 2006-10-13 |
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