CN101790781B - 集成电路管芯的封装方法 - Google Patents
集成电路管芯的封装方法 Download PDFInfo
- Publication number
- CN101790781B CN101790781B CN2008801046039A CN200880104603A CN101790781B CN 101790781 B CN101790781 B CN 101790781B CN 2008801046039 A CN2008801046039 A CN 2008801046039A CN 200880104603 A CN200880104603 A CN 200880104603A CN 101790781 B CN101790781 B CN 101790781B
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- die
- bond coat
- bond
- release film
- solvent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Die Bonding (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/846,671 | 2007-08-29 | ||
| US11/846,671 US7595226B2 (en) | 2007-08-29 | 2007-08-29 | Method of packaging an integrated circuit die |
| PCT/US2008/068076 WO2009032389A1 (en) | 2007-08-29 | 2008-06-25 | Method of packaging an integrated circuit die |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101790781A CN101790781A (zh) | 2010-07-28 |
| CN101790781B true CN101790781B (zh) | 2012-06-13 |
Family
ID=40408116
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2008801046039A Expired - Fee Related CN101790781B (zh) | 2007-08-29 | 2008-06-25 | 集成电路管芯的封装方法 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US7595226B2 (enExample) |
| EP (1) | EP2186125A1 (enExample) |
| JP (1) | JP5187863B2 (enExample) |
| KR (1) | KR101483419B1 (enExample) |
| CN (1) | CN101790781B (enExample) |
| TW (1) | TWI423350B (enExample) |
| WO (1) | WO2009032389A1 (enExample) |
Families Citing this family (43)
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| US8035216B2 (en) * | 2008-02-22 | 2011-10-11 | Intel Corporation | Integrated circuit package and method of manufacturing same |
| US8580612B2 (en) * | 2009-02-12 | 2013-11-12 | Infineon Technologies Ag | Chip assembly |
| TWI456715B (zh) * | 2009-06-19 | 2014-10-11 | 日月光半導體製造股份有限公司 | 晶片封裝結構及其製造方法 |
| TWI466259B (zh) * | 2009-07-21 | 2014-12-21 | 日月光半導體製造股份有限公司 | 半導體封裝件、其製造方法及重佈晶片封膠體的製造方法 |
| TWI405306B (zh) | 2009-07-23 | 2013-08-11 | 日月光半導體製造股份有限公司 | 半導體封裝件、其製造方法及重佈晶片封膠體 |
| US20110084372A1 (en) | 2009-10-14 | 2011-04-14 | Advanced Semiconductor Engineering, Inc. | Package carrier, semiconductor package, and process for fabricating same |
| US20110108999A1 (en) * | 2009-11-06 | 2011-05-12 | Nalla Ravi K | Microelectronic package and method of manufacturing same |
| JP5551568B2 (ja) * | 2009-11-12 | 2014-07-16 | 日東電工株式会社 | 樹脂封止用粘着テープ及びこれを用いた樹脂封止型半導体装置の製造方法 |
| US8378466B2 (en) | 2009-11-19 | 2013-02-19 | Advanced Semiconductor Engineering, Inc. | Wafer-level semiconductor device packages with electromagnetic interference shielding |
| US8742561B2 (en) | 2009-12-29 | 2014-06-03 | Intel Corporation | Recessed and embedded die coreless package |
| US8901724B2 (en) | 2009-12-29 | 2014-12-02 | Intel Corporation | Semiconductor package with embedded die and its methods of fabrication |
| US8569894B2 (en) | 2010-01-13 | 2013-10-29 | Advanced Semiconductor Engineering, Inc. | Semiconductor package with single sided substrate design and manufacturing methods thereof |
| US8372689B2 (en) | 2010-01-21 | 2013-02-12 | Advanced Semiconductor Engineering, Inc. | Wafer-level semiconductor device packages with three-dimensional fan-out and manufacturing methods thereof |
| US8320134B2 (en) | 2010-02-05 | 2012-11-27 | Advanced Semiconductor Engineering, Inc. | Embedded component substrate and manufacturing methods thereof |
| TWI411075B (zh) | 2010-03-22 | 2013-10-01 | 日月光半導體製造股份有限公司 | 半導體封裝件及其製造方法 |
| US8368232B2 (en) * | 2010-03-25 | 2013-02-05 | Qualcomm Incorporated | Sacrificial material to facilitate thin die attach |
| US8624374B2 (en) | 2010-04-02 | 2014-01-07 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof |
| US8278746B2 (en) | 2010-04-02 | 2012-10-02 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages including connecting elements |
| US8535989B2 (en) | 2010-04-02 | 2013-09-17 | Intel Corporation | Embedded semiconductive chips in reconstituted wafers, and systems containing same |
| US8319318B2 (en) | 2010-04-06 | 2012-11-27 | Intel Corporation | Forming metal filled die back-side film for electromagnetic interference shielding with coreless packages |
| US8618652B2 (en) | 2010-04-16 | 2013-12-31 | Intel Corporation | Forming functionalized carrier structures with coreless packages |
| US9847308B2 (en) | 2010-04-28 | 2017-12-19 | Intel Corporation | Magnetic intermetallic compound interconnect |
| US8939347B2 (en) | 2010-04-28 | 2015-01-27 | Intel Corporation | Magnetic intermetallic compound interconnect |
| US8313958B2 (en) | 2010-05-12 | 2012-11-20 | Intel Corporation | Magnetic microelectronic device attachment |
| US8434668B2 (en) | 2010-05-12 | 2013-05-07 | Intel Corporation | Magnetic attachment structure |
| US8609532B2 (en) | 2010-05-26 | 2013-12-17 | Intel Corporation | Magnetically sintered conductive via |
| US20120001339A1 (en) | 2010-06-30 | 2012-01-05 | Pramod Malatkar | Bumpless build-up layer package design with an interposer |
| US8372666B2 (en) | 2010-07-06 | 2013-02-12 | Intel Corporation | Misalignment correction for embedded microelectronic die applications |
| US8754516B2 (en) | 2010-08-26 | 2014-06-17 | Intel Corporation | Bumpless build-up layer package with pre-stacked microelectronic devices |
| US8501544B2 (en) * | 2010-08-31 | 2013-08-06 | Stats Chippac, Ltd. | Semiconductor device and method of forming adhesive material over semiconductor die and carrier to reduce die shifting during encapsulation |
| US8304913B2 (en) | 2010-09-24 | 2012-11-06 | Intel Corporation | Methods of forming fully embedded bumpless build-up layer packages and structures formed thereby |
| US8941222B2 (en) | 2010-11-11 | 2015-01-27 | Advanced Semiconductor Engineering Inc. | Wafer level semiconductor package and manufacturing methods thereof |
| US9406658B2 (en) | 2010-12-17 | 2016-08-02 | Advanced Semiconductor Engineering, Inc. | Embedded component device and manufacturing methods thereof |
| US8937382B2 (en) | 2011-06-27 | 2015-01-20 | Intel Corporation | Secondary device integration into coreless microelectronic device packages |
| US8848380B2 (en) | 2011-06-30 | 2014-09-30 | Intel Corporation | Bumpless build-up layer package warpage reduction |
| US9245773B2 (en) * | 2011-09-02 | 2016-01-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device packaging methods and structures thereof |
| WO2013172814A1 (en) | 2012-05-14 | 2013-11-21 | Intel Corporation | Microelectronic package utilizing multiple bumpless build-up structures and through-silicon vias |
| WO2013184145A1 (en) | 2012-06-08 | 2013-12-12 | Intel Corporation | Microelectronic package having non-coplanar, encapsulated microelectronic devices and a bumpless build-up layer |
| CN102842564B (zh) * | 2012-09-12 | 2014-06-25 | 矽力杰半导体技术(杭州)有限公司 | 集成开关电源的倒装封装装置及其倒装封装方法 |
| NL2011512C2 (en) * | 2013-09-26 | 2015-03-30 | Besi Netherlands B V | Method for moulding and surface processing electronic components and electronic component produced with this method. |
| US11075173B2 (en) * | 2018-10-31 | 2021-07-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of forming same |
| KR102747644B1 (ko) * | 2019-07-22 | 2024-12-27 | 삼성전자주식회사 | 반도체 패키지 및 그 제조 방법 |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010019770A (ko) * | 1999-08-30 | 2001-03-15 | 윤덕용 | 도포된 이방성 전도 접착제를 이용한 웨이퍼형 플립 칩 패키지제조방법 |
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| US20060170096A1 (en) * | 2005-02-02 | 2006-08-03 | Yang Jun Y | Chip scale package and method for manufacturing the same |
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| WO2009020467A1 (en) * | 2007-08-07 | 2009-02-12 | Skyworks Solutions, Inc. | Near chip scale package integration process |
-
2007
- 2007-08-29 US US11/846,671 patent/US7595226B2/en active Active
-
2008
- 2008-06-25 WO PCT/US2008/068076 patent/WO2009032389A1/en not_active Ceased
- 2008-06-25 CN CN2008801046039A patent/CN101790781B/zh not_active Expired - Fee Related
- 2008-06-25 KR KR1020107004382A patent/KR101483419B1/ko not_active Expired - Fee Related
- 2008-06-25 EP EP08771855A patent/EP2186125A1/en not_active Withdrawn
- 2008-06-25 JP JP2010522986A patent/JP5187863B2/ja not_active Expired - Fee Related
- 2008-07-15 TW TW097126812A patent/TWI423350B/zh not_active IP Right Cessation
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010019770A (ko) * | 1999-08-30 | 2001-03-15 | 윤덕용 | 도포된 이방성 전도 접착제를 이용한 웨이퍼형 플립 칩 패키지제조방법 |
Also Published As
| Publication number | Publication date |
|---|---|
| KR101483419B1 (ko) | 2015-01-16 |
| JP5187863B2 (ja) | 2013-04-24 |
| WO2009032389A1 (en) | 2009-03-12 |
| EP2186125A1 (en) | 2010-05-19 |
| CN101790781A (zh) | 2010-07-28 |
| TWI423350B (zh) | 2014-01-11 |
| KR20100051692A (ko) | 2010-05-17 |
| JP2010538462A (ja) | 2010-12-09 |
| US20090061564A1 (en) | 2009-03-05 |
| US7595226B2 (en) | 2009-09-29 |
| TW200915441A (en) | 2009-04-01 |
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