CN101743627B - 在窄隔离有界的源极/漏极区上形成改善的epi填充的方法及由此形成的结构 - Google Patents

在窄隔离有界的源极/漏极区上形成改善的epi填充的方法及由此形成的结构 Download PDF

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CN101743627B
CN101743627B CN200880006516XA CN200880006516A CN101743627B CN 101743627 B CN101743627 B CN 101743627B CN 200880006516X A CN200880006516X A CN 200880006516XA CN 200880006516 A CN200880006516 A CN 200880006516A CN 101743627 B CN101743627 B CN 101743627B
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P·拉纳德
K·扎瓦兹基
C·奥特
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Abstract

介绍了形成微电子器件的方法和相关结构。这些方法可以包括等离子刻蚀晶体管的源极/漏极区的一部分，然后沿着(100)面选择性地湿法刻蚀所述源极漏极区，以在凹的源极/漏极区中形成至少一个(111)区。

Description

在窄隔离有界的源极/漏极区上形成改善的EPI填充的方法及由此形成的结构
背景技术
对形成诸如利用晶体管的器件的微电子器件的工艺的一个关注之处涉及利用外延材料(例如利用硅锗材料)填充源极/漏极区的步骤。随着晶体管几何结构变得越来越小，对于每一代微电子器件来说源极/漏极区变得越来越窄，因此，利用外延材料进行填充变得越来越难。在器件制造期间，不好的外延填充可能导致晶体管的产量变低。
附图说明
尽管以具体指出并明确要求了被示为本发明的内容的权利要求对说明书进行了总结，但是当结合附图阅读本发明的以下说明时，从其中能够容易地了解到本发明的优点，附图中：
图1a-1d示出了根据本发明的实施例的结构。
图1e示出了根据现有技术的结构。
具体实施方式
在以下详细的说明中参考附图，附图以说明的方式示出了可以实施本发明的具体实施例。对这些实施例进行了充分详细的说明，以使本领域技术人员能够实施本发明。应该理解的是，本发明的各实施例尽管不同，但并非彼此排斥。例如，在本文中结合一个实施例描述的特定特征、结构或特性可以在另一实施例中实施而不偏离本发明的精神和范围。此外，应该理解的是，可以修改在每个所公开的实施例中的单个元件的位置或布置而不偏离本发明的精神和范围。因此，以下详细的说明不是限制性的，本发明的范围仅由被恰当理解的所附权利要求以及权利要求有权要求的等价物的全部范围来限定。在附图中，在几个视图中类似的参考标记表示相同或相似的功能性。
对形成微电子结构的方法和相关结构进行说明。这些方法可以包括等离子刻蚀晶体管的源极/漏极区的一部分，然后沿着(100)面选择性地湿法刻蚀源极漏极区，以在凹的源极/漏极区中形成至少一个(111)区。本发明的方法能够利用可以显著地改变凹的源极/漏极区的几何形状的刻蚀化学性质(chemistries)，这例如能够显著地改善隔离有界(isolation bounded)的源极/漏极区上的外延填充。
图1a-1d示出了例如形成诸如晶体管结构的源极/漏极区的微电子结构的方法的实施例。图1a示出了晶体管结构100的一部分的截面图。晶体管结构100可以包括栅极区102，该栅极区102可以包括栅极氧化物区101和栅极103。晶体管结构100还可以包括间隔体105和位于栅极氧化物区101下面的沟道区107。晶体管结构100可以进一步包括源极/漏极区106，源极/漏极区106可以与栅极区102的至少一侧相邻。源极/漏极区106可以包括硅和/或含硅的材料。
在一个实施例中，可以利用干法刻蚀工艺104对源极/漏极区106的一部分进行刻蚀(图1b)。在一个实施例中，如本领域所公知的，可以利用例如等离子干法刻蚀工艺对源极/漏极区106进行干法刻蚀。根据具体的应用，可以改变干法刻蚀104的具体工艺参数。
在一个实施例中，可以通过干法刻蚀工艺104来设置源极/漏极区106的隔离边缘109处的深度108。在一个实施例中，隔离边缘深度109的深度可以包括在大约500至大约600埃之间或者更小，但这将取决于具体的应用。隔离边缘109可以包括一个区域，在该区域中诸如ILD(层间电介质)的隔离材料123(例如，参见图1d)可以被设置为与源极漏极区106相邻。
干法刻蚀工艺104可以在源极/漏极区106中形成最初的凹深110。通常凹的刻蚀深度110可以与栅极区102相邻，而隔离边缘109深度108可以与隔离边缘109相邻。在一个实施例中，最初的凹深110可以包括大约500至大约600埃，或者更小的深度，但这将取决于具体的应用。
接下来，可以使用选择性的湿法刻蚀工艺115来湿法刻蚀源极/漏极区106(图1c)。在一个实施例中，湿法刻蚀工艺115可以沿着(100)面选择性地刻蚀源极/漏极区106，并且接下来在(111)面上停止，以在凹的源极/漏极区106中形成至少一个(111)区116。在一个实施例中，湿法刻蚀工艺115可以包括含羟基(OH)的物质，例如但不限于氢氧化钾、TMAH以及氢氧化钠。
通过湿法刻蚀工艺115可以独立地设置源极/漏极区106的最终凹深112。干法刻蚀的较浅深度将改善隔离边缘109附近的外延填充(在接下来的处理期间)，而湿法刻蚀的更深的深度(Y’)将改善晶体管结构100中的沟道应变(通过增加外延材料体积填充)。可以根据具体的应用来改变干法和湿法刻蚀的具体工艺参数和尺寸。
在一个实施例中，湿法刻蚀工艺115可以在源极/漏极区106的底部113处生成两个(111)面。在一个实施例中，湿法刻蚀工艺115可以沿着晶体管结构100的隔离边缘109形成(111)区。在一个实施例中，可以在源极/漏极区106内形成外延材料118(图1d)。在一个实施例中，外延材料118可以包括硅锗材料。可以使用本领域所公知的任何适当技术在源极/漏极区106中生长外延材料118。在一个实施例中，可以沿着晶体管结构100的隔离边缘109的(111)面来形成外延材料118。
在不采用湿法刻蚀工艺(例如，仅采用干法刻蚀工艺)的情况下，由于在晶体管100的隔离边缘109上仅有很少的外延生长甚至没有外延生长的原因，所以在选择性外延生长的刻蚀轮廓(profile)中可能产生严重的问题。不采用湿法刻蚀115(其在隔离边缘上产生(111)硅面)，在隔离边缘109上将可能不产生外延生长。
沿着隔离边缘109生成(111)面导致源极/漏极区106的外延填充的改善。图1e(现有技术)示出了在相对于源极/漏极106底部113的外延生长厚度上的区别。图1e的现有技术刻蚀示出了从隔离边缘109的底部113开始的外延填充非常不好。如图1d所示，在执行干法刻蚀104之后利用湿法刻蚀115产生源极/漏极区106的非常稳健(robust)的外延填充。
另外，将外延材料118的一部分升高到栅极区102之上(在栅极氧化物面的底部之上)。在一个实施例中，可以将外延材料的升高部分120升高(包括高度)至少大约10nm，但这将取决于具体的应用。现有技术的晶体管结构100(图1e)典型地不形成外延材料118的升高部分。在湿法刻蚀工艺115期间增加湿法刻蚀的深度将提高晶体管结构100的性能。
在一个实施例中，可以在栅极区102之下形成顶点(在源极/漏极区106中两个(111)面之间的交点)。顶点122可以改善晶体管结构100的电性能。
在一个实施例中，可以在源极/漏极区106上形成接点，和/或将接点连接至源极/漏极区106(图1d)。通过利用本发明的实施例，可以将接点124完全着陆(land)，换句话说，使得接点124与源极/漏极区106的外延材料118形成完全接触。因为现有技术晶体管典型地并不是充分填充源极/漏极区106，所以接点124不可能完全着陆于源极/漏极区106的外延材料118上(图1e)。换句话说，接点124不可能与源极/漏极区106的外延材料118形成完全接触，这将导致器件性能下降以及制造期间的产量损失。
于是，本发明的实施例的益处包括但不限于：生成与源极/漏极区的非常好的接触，生成有应力的外延填充，该外延填充使得晶体管沟道产生应变，从而改善晶体管的迁移率，并且即使对于非常严格的设计规则来说能够实现稳健的外延填充工艺。另外，本发明的实施例能够降低隔离有界的晶体管的外部电阻，并且降低隔离有界的晶体管中的开路接点(opencontact)。
尽管上述说明已经具体说明了可以在本发明的方法中使用的某些步骤和材料，但是本领域技术人员应该理解的是，可以作出许多修改和替换。因此，所有这种修改、变化、替换和添加都应当被看作落在如所附权利要求限定的本发明的精神和范围内。此外，应该理解的是微电子器件的某些方面在本领域中是公知的。因此，应该理解的是在本文中提供的附图仅示出了示例的微电子器件的与实施本发明有关的部分。因此本发明不限于本文所述的结构。

Claims (12)

1.一种用于形成微电子结构的方法，包括
干法刻蚀晶体管的源极/漏极区的一部分；并且
沿着(100)面选择性地湿法刻蚀所述源极漏极区，以在凹的源极/漏极区中形成至少一个(111)区，
其中沿着所述源极/漏极区的隔离边缘形成(111)区；并且
在沿着所述隔离边缘形成的所述(111)区上生长外延材料。
2.根据权利要求1所述的方法，其中通过所述干法刻蚀来设置隔离边缘的深度。
3.根据权利要求1所述的方法，其中通过所述湿法刻蚀来设置所述源极/漏极区的最终凹深。
4.根据权利要求1所述的方法，其中对所述干法刻蚀和湿法刻蚀中的至少一个的深度进行优化以改善所述晶体管的电性能。
5.根据权利要求1所述的方法，还包括沿着所述至少一个(111)区生长外延材料，其中将所述外延材料的一部分升高至栅极区平面之上，并且其中所述外延材料填充所述源极/漏极区。
6.根据权利要求5所述的方法，还包括形成到达所述填充的源极/漏极区的接点，其中所述接点完全着落于所述源极/漏极区上。
7.根据权利要求1所述的方法，其中在所述源极/漏极区中的两个(111)区之间的交点形成于栅极区之下。
8.一种微电子结构，包括：
晶体管的凹的源极/漏极区，其包括至少一个(111)区的，其中在所述源极/漏极区中的两个(111)区之间的交点形成于所述晶体管的栅极区之下，以及
布置在所述源极/漏极区内的外延材料，
其中在沿着所述源极/漏极区的隔离边缘区的(111)面上布置所述外延材料。
9.根据权利要求8所述的微电子结构，其中所述外延材料包括硅锗。
10.根据权利要求8所述的微电子结构，还包括所述外延材料的升高部分，其中所述升高部分布置在所述栅极区之上。
11.根据权利要求10所述的微电子结构，其中将所述升高部分升高为在所述栅极区上至少10nm。
12.根据权利要求8所述的微电子结构，还包括布置在所述源极/漏极区上的接点，其中所述接点完全着落于所述源极漏极区上。
CN200880006516XA 2007-03-30 2008-03-28 在窄隔离有界的源极/漏极区上形成改善的epi填充的方法及由此形成的结构 Active CN101743627B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/694,458 US7691752B2 (en) 2007-03-30 2007-03-30 Methods of forming improved EPI fill on narrow isolation bounded source/drain regions and structures formed thereby
US11/694,458 2007-03-30
PCT/US2008/058721 WO2008121855A1 (en) 2007-03-30 2008-03-28 Methods of forming improved epi fill on narrow isolation bounded source/drain regions and structures formed thereby

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