CN101699623B - 半导体装置 - Google Patents

半导体装置 Download PDF

Info

Publication number
CN101699623B
CN101699623B CN200910179290XA CN200910179290A CN101699623B CN 101699623 B CN101699623 B CN 101699623B CN 200910179290X A CN200910179290X A CN 200910179290XA CN 200910179290 A CN200910179290 A CN 200910179290A CN 101699623 B CN101699623 B CN 101699623B
Authority
CN
China
Prior art keywords
electrode
semiconductor
conductive plate
semiconductor device
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN200910179290XA
Other languages
English (en)
Other versions
CN101699623A (zh
Inventor
秋庭隆史
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Publication of CN101699623A publication Critical patent/CN101699623A/zh
Application granted granted Critical
Publication of CN101699623B publication Critical patent/CN101699623B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49524—Additional leads the additional leads being a tape carrier or flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/37147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/3754—Coating
    • H01L2224/37599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/4005—Shape
    • H01L2224/4009—Loop shape
    • H01L2224/40095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73219—Layer and TAB connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73221—Strap and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/84801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/8485—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Dc-Dc Converters (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Die Bonding (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

本发明提供一种半导体装置。在以往的半导体装置中，存在有DC-DC转换电路的电源能量转换效率被MOSFET特性影响的问题。本发明的半导体装置(1)，在芯片焊盘(5)上固定有三个MOSFET元件(2～4)。MOSFET元件(2～4)的源极电极(9～11)通过导电板(24)而共同连接。MOSFET元件(2～4)的漏极电极(26、28、29)共同连接。MOSFET(2～4)的栅极电极(6～8)个别地连接。通过该结构，MOSFET元件(2～4)可根据目的而个别地驱动。

Description

半导体装置
本申请是三洋电机株式会社于2007年6月26日提交的名称为“半导体装置”、申请号为200710126273.0号发明专利申请的分案申请。
技术领域
本发明涉及将多个半导体元件封装在一个封装内并使半导体元件特性提高的半导体装置。
背景技术
作为现有的半导体装置的一实施例，公知有如下的电力用半导体装置封装。将第一电力用MOSFET芯片和第二电力用MOSFET芯片形成层积构造且并联连接，一体地树脂封装。第一及第二电力用MOSFET芯片在电气上具有同一构造，在芯片的表面侧形成源极电极和栅极电极，在芯片的背面侧形成有漏极电极。并且，在引线架上通过焊锡而固定安装有第一电力用MOSFET芯片。第二电力用MOSFET芯片的表面侧配置在第一电力用的MOSFET芯片上。在两芯片间配置电极配线金属板，经由电极配线金属板而将源极电极彼此及栅极电极彼此分别固定安装。另外，第二电力用MOSFET芯片的漏极电极经由金属架与固定有第一电力用MOSFET芯片的漏极电极的引线架电连接(例如，参照专利文献1)。
专利文献1：(日本)特开2005-302951号公报(第3～4页、第1～2图)
在现有的半导体装置中，如上所述，电气上具有同一构造的第一及第二电力用MOSFET芯片并联连接，基于向栅极电极发送的同一控制信号，进行同一驱动。通过该构造，能够避免封装尺寸的增大，并且降低接通电阻值，可实现额定电流大的电力用半导体装置封装。但是，例如在用于DC-DC转换电路中时，由于第一及第二MOSFET芯片进行同一驱动，故具有在低电流区域电容大，电源能量转换效率降低的问题。
发明内容
本发明是鉴于上述各问题而构成的，本发明的半导体装置，其将多个半导体元件在一体连接的状态下封装在一个封装内而构成，所述半导体元件在一主面上具有流过主电流的主电极和授受控制信号的控制电极，其特征在于，具有：导电板，其相对所述多个半导体元件的主电极一体连接；导电部件，其相对所述多个半导体元件的控制电极分别地连接。因此，在本发明中，在一体地连接的状态的多个半导体元件的主电极上固定有共同的导电板。并且，导电部件与半导体元件的控制电极分别独立地连接。通过该构造，能够分别独立地驱动多个半导体元件，并且可根据目的而改变电流量并进行效率改进。
另外，本发明的半导体装置，其将多个半导体芯片封装在一个封装内而构成，所述半导体芯片在一主面上具有流过主电流的主电极和授受控制信号的控制电极，其特征在于，具有：导电板，其相对所述多个半导体芯片的主电极一体连接；导电部件，其相对所述多个半导体芯片的控制电极分别地连接。因此，在本发明中，在多个半导体芯片的主电极上固定共同的导电板。并且，导电部件与多个半导体芯片的控制电极分别独立地连接。根据该构造，通过分别独立地驱动多个半导体芯片，可根据目的而改变电流量并进行效率改进。
另外，在本发明的半导体装置中，所述导电板为平板形状。因此，在本发明中，通过将导电板形成为平板形状，能够将封装的厚度减薄。
另外，在本发明的半导体装置中，所述导电板仅在与所述半导体元件的主电极连接的连接区域具有焊锡润湿性。因此，在本发明中，通过利用焊锡润湿性的自调整技术，能够将导电板和半导体元件的主电极固定。
另外，在本发明的半导体装置中，在所述导电板上形成有多个凹凸形状，所述半导体芯片的主电极在所述导电板的凹部形状区域连接。因此，本发明通过在导电板上形成对应半导体芯片的主电极的多个凹部，能够防止导电板在半导体芯片端部接触。
另外，在本发明的半导体装置中，所述导电部件是金属细线。因此，在本发明中，多个半导体元件可对应目的而分别独立地驱动。
在本发明中，在多个半导体元件的主电极上固定有共同的导电板。在多个半导体元件的控制电极中，能够通过个别的导电部件而个别地施加电位。通过该构造，能够分别独立地驱动多个半导体元件。例如，通过将该半导体装置用于DC-DC转换电路，电源能量转换效率在高效率状态下推移。
另外，在本发明中，导电板形成为平板形状。并且，在导电板上形成有焊锡润湿性优良的区域。通过该构造，能够利用采用了焊锡的润湿性的自调整技术，进而可将封装厚度减薄。
另外，在本发明中，在导电板上形成有对应于半导体芯片的主电极的多个凹部。通过该构造，导电板不与在半导体芯片侧面露出的漏极区域短路，可防止半导体芯片的短路。
在本发明中，将多个半导体元件封装在一个封装内。多个半导体元件一体地连接并为一个芯片。通过该构造，可通过一次芯片接合工序而固定多个半导体元件。
另外，在本发明中，在多个半导体元件的控制电极上个别地连接有金属细线。通过该构造，可个别地驱动多个半导体元件。
附图说明
图1是用于说明本发明实施方式的半导体装置的平面图。
图2是用于说明本发明实施方式的半导体装置的剖面图，(A)是沿图1的A-A线的剖面图，(B)是沿图1的B-B线的剖面图。
图3(A)是用于说明使用本发明实施方式的半导体装置的DC-DC转换电路的电源能量转换效率的图，(B)是用于说明使用本发明实施方式的半导体装置的DC-DC转换电路的电源能量转换效率的图。
图4是用于说明本发明实施方式的半导体装置的平面图。
图5是用于说明本发明实施方式的半导体装置的剖面图，(A)是沿图4的C-C线的剖面图，(B)是沿图4的D-D线的剖面图。
附图标记说明
1半导体装置
2MOSFET元件
3MOSFET元件
4MOSFET元件
5芯片焊盘
12封装
24导电板
42MOSFET芯片
43MOSFET芯片
44MOSFET芯片
64导电板
具体实施方式
以下，参照图1～图3详细说明本发明一实施方式的半导体装置。图1是用于说明本发明实施方式的半导体装置的平面图。图2(A)是沿图1所示的半导体装置的A-A线的剖面图，图2(B)是沿图1所示的半导体装置的B-B线的剖面图。图3(A)及(B)是用于说明使用本发明实施方式的半导体装置的DC-DC转换电路的电源能量转换效率的图。另外，在图1中，对图2(A)、(B)所示的钝化膜未作图示。
如图1所示，在本实施方式的半导体装置1中，例如三个MOSFET元件2～4经由导电性粘接剂、例如焊锡膏、银膏等导电膏25(参照图2(A))固定在芯片焊盘5上。MOSFET元件2～4为同一单元构造，具有同一元件尺寸。并且，MOSFET元件2～4一体连接并为一个芯片。在芯片表面侧形成有栅极电极6～8及源极电极9～11。另外，在芯片背面侧形成有漏极电极26、28、29(参照图2(B))。并且，虚线表示封装的外形，从封装12导出引线13～20并用作为外部端子。即，在半导体装置1中，将多个半导体元件、例如三个MOSFET元件2～4封装在一个封装12内。
芯片焊盘5及引线13～20通过成形铜(Cu)引线架(以下，称为Cu架)而形成。引线13～16与芯片焊盘5连接而形成。芯片焊盘5与MOSFET元件2～4的漏极电极26、28、29固着，引线13～16被用作为漏极端子。另外，在各个MOSFET元件2～4上分别形成有漏极电极26、28、29，MOSFET元件2～4为一体的状态，漏极电极26、28、29也为一体的状态。并且，经由芯片焊盘5对漏极电极26、28、29施加共同的电位。
MOSFET元件2的栅极电极6经由金属细线21与引线18电连接，引线18被用作为栅极端子。同样地，MOSFET元件3、4的栅极电极7、8分别经由金属细线22、23与引线19、20电连接，引线19、20被用作为栅极端子。
MOSFET元件2～4的源极电极9～11经由导电性粘接剂、例如焊锡膏27、30、31(参照图2(B))与Cu架等由导电性材料构成的导电板24固着。MOSFET元件2～4具有各自独立的源极电极9～11，在源极电极9～11上经由导电板24施加共同电位。并且，从导电板24导出的引线17被用作源极端子。
通过该构造，可相对封装在封装12内的MOSFET元件2～4施加共同的漏极电位及源极电位。另一方面，可对MOSFET元件2～4个别地施加栅极电位。结果，能够个别地驱动封装12内的MOSFET元件2～4，并且可调节从一个封装12输出的电流量，能够改进效率(参照后述的图3(A)及(B))。
如图2(A)所示，在芯片焊盘5的上面经由导电膏25固定有MOSFET元件2的漏极电极26。另外，在MOSFET元件2的上面形成有例如由氮化硅(SiN)构成的钝化膜35。MOSFET元件2的源极电极9从设于钝化膜35上的开口部露出。在MOSFET元件2的源极电极9的上面经由焊锡膏27而固定有导电板24。在导电板24的粘接面侧，通过镀敷法等将焊锡润湿性高的金属薄膜3至少形成在与MOSFET元件2的源极电极9固着的区域。另外，也可以通过蒸镀法形成金属薄膜32。通过利用焊锡膏27的焊锡润湿性，能够位置精度优良地将MOSFET元件2的源极电极9和导电板24固定。并且，从导电板24导出的引线17在MOSFET元件2附近向下方弯折，实质上与芯片焊盘5位于同一平面上。并且，引线13、17从封装12的侧面导出。
如图2(B)所示，在芯片焊盘5的上面经由导电膏25固定有MOSFET元件2～4的漏极电极26、28、29。如图所示，对半导体晶片(未图示)切割并分割成半导体芯片时，在MOSFET元件2与MOSFET元件3之间以及MOSFET元件3与MOSFET元件4之间不进行切割。结果，MOSFET元件2～4为一体的状态，被作为一个芯片处理。因此，在将MOSFET元件2～4固定在芯片焊盘5上面时，可通过一次芯片接合工序进行。
在MOSFET元件2～4的源极电极9～11的上面经由焊锡膏27、30、31固定有导电板24。如上所述，在导电板24的粘接面侧，通过镀敷法等将焊锡润湿性高的金属薄膜32～34至少形成在与MOSFET元件2～4的源极电极9～11固着的区域上。并且，通过利用焊锡膏27、30、31的焊锡润湿性，能够位置精度良好地将MOSFET元件2～4的源极电极9～11和导电板24固定。通过该构造，导电板24为平板形状，并且能够将封装12(由虚线图示)的厚度减薄。
在图3(A)及(B)中，X轴表示MOSFET芯片的电流量，Y轴表示将MOSFET芯片用于DC-DC转换电路时的电源能量转换效率。另外，图3(A)中所谓的芯片是由一个MOSFET元件得到的芯片。
在图3(A)中，虚线表示将芯片尺寸小(电容小)的一个MOSFET芯片用于DC-DC转换电路的情况。点划线表示将芯片尺寸大(电容大)的一个MOSFET芯片用于DC-DC转换电路的情况。另外，点划线表示的大尺寸的芯片尺寸(面积)为虚线表示的小尺寸的芯片尺寸的大约3倍。
如点划线所示，在使用芯片尺寸小的MOSFET芯片时，由于电容值小，故在低电流区域，电源能量转换效率表示为高效率。另一方面，由于在大电流区域的接通电阻大，故电源能量转换效率表示为低效率。如点划线所示，使用芯片尺寸大的MOSFET芯片时，由于电容值大，故在低电流区域，电流能量转换效率表示为低效率。另一方面，由于在大电流区域的接通电阻值小，故电源能量转换效率表示为高效率。
在图3(B)中，实线为本实施方式，表示将可个别驱动的多个MOSFET元件用于DC-DC转换电路的情况。在本实施方式中，如上所述，将三个MOSFET元件2～4(参照图1)并联连接，可对MOSFET元件2～4的栅极电极6～8个别地施加栅极电压。通过该构造，在DC-DC转换电路的低电流区域，通过仅驱动MOSFET元件2，可使电源能量转换效率为高效率。接下来，在驱动MOSFET元件2的状态下，通过驱动MOSFET元件3，能够提高DC-DC转换电流中的中电流区域的电流能量转换效率为高效率。最后，在驱动MOSFET元件2、3的状态下，通过驱动MOSFET元件4，能够使DC-DC转换电路中的大电流区域的电源能量转换效率为高效率。
即，如使用图3(A)进行的说明那样，对应于DC-DC转换电路中的电流区域，调整MOSFET元件2～4的驱动。通过该调整，如图3(B)所示，能够在高效率状态下使电源能量转换效率推移。
另外，在本实施方式中，对芯片焊盘5及导电板24由Cu架成形的情况进行了说明，但不限于本方式。例如，可以代替Cu架而使用以Fe-Ni为主材料的框架，也可以是其他金属材料。另外，在本实施方式中，对将三个MOSFET元件作为一个芯片并封装在一个封装内的构造进行了说明，但不限于本方式。也可以例如将四个以上的MOSFET元件作为一个芯片并封装在一个封装内，并且可分别独立地驱动。另外，在本实施方式中，对使用同一单元构造、同一元件尺寸的三个MOSFET元件的情况进行了说明，但不限于该情况。可以在一个封装内封装同一单元构造的不同元件尺寸的半导体元件。另外，在本实施方式中，对在导电板24上形成金属薄膜32～34的情况进行了说明，但不限于该情况。例如，可以在源极电极9～11上涂敷有焊锡膏27、30、31的状态下固定导电板24，此时，即使不形成金属薄膜32～34也可以得到同样的效果。除此之外，在不脱离本发明主旨的范围内，可进行各种变更。
接下来，参照图4～图5详细说明本发明其他实施方式的半导体装置。图4是用于说明本实施方式的半导体装置的平面图。图5(A)是沿图4所示的半导体装置的C-C线的剖面图，图5(B)是沿图4所示的半导体装置的D-D线的剖面图。另外，对图4及图5所示的本实施方式的半导体装置进行说明时，参照上述图3(A)及(B)的DC-DC转换电路的电源能量转换效率的说明。另外，在图4中对图5(A)及(B)所示的钝化膜未作图示。
如图4所示，在本实施方式的半导体装置41中，例如三个MOSFET芯片42～44经由导电性粘接剂、例如焊锡膏、银膏等导电膏65(参照图5(A))固定在芯片焊盘45上。MOSFET芯片42～44为同一单元构造且同一芯片尺寸，在芯片表面侧形成有栅极电极46～48及源极电极49～51。另外，在芯片背面侧形成有漏极电极66、70、71(参照图5(B))。并且，虚线表示封装的外形，从封装52导出引线53～60，其被用作为外部端子。即，在半导体装置41中，将多个半导体元件、例如三个MOSFET芯片42～44封装在一个封装52内。
芯片焊盘45及引线53～60通过成形铜(Cu)引线架(以下，称为Cu架)而形成。引线53～56与芯片焊盘45连接而形成。芯片焊盘45与MOSFET芯片42～44的漏极电极66、70、71固着，引线53～56被用作为漏极端子。MOSFET芯片42～44具有各自独立的漏极电极66、70、71，经由芯片焊盘45对漏极电极66、70、71施加共同电位。
MOSFET芯片42的栅极电极46经由金属细线61与引线58电连接，引线58被用作为栅极端子。同样地，MOSFET芯片43、44的栅极电极47、48分别经由金属细线62、63与引线59、60电连接，引线59、60被用作为栅极端子。
MOSFET芯片42～44的源极电极49～51经由导电性粘接剂、例如焊锡膏、银膏等导电膏67、72、73(参照图5(B))与Cu架等由导电性材料构成的导电板64固着。MOSFET芯片42～44具有各自独立的源极电极49～51，在源极电极49～51上经由导电板64施加共同电位。并且，从导电板64导出的引线57被用作源极端子。
通过该构造，可相对封装在封装52内的MOSFET芯片42～44施加共同的漏极电位及源极电位。另一方面，可对MOSFET芯片42～44个别地施加栅极电位。结果，能够个别地驱动封装52内的MOSFET芯片42～44，并且可调节从一个封装52输出的电流量，能够改进效率(参照后述的图3(A)及(B))。
如图5(A)所示，在芯片焊盘45的上面经由导电膏65固定有MOSFET芯片42的漏极电极66。另外，在MOSFET芯片42的上面形成有例如由氮化硅(SiN)构成的钝化膜81。MOSFET芯片42的源极电极49从设于钝化膜81上的开口部露出。在MOSFET芯片42的源极电极49上面经由导电膏67而固定有导电板64。从导电板64导出的引线57在MOSFET芯片42附近向下方弯折，实质上与芯片焊盘45位于同一平面上。并且，引线53、57从封装52的侧面导出。
如图5(B)所示，在芯片焊盘45的上面经由导电膏65、68、69固定有MOSFET芯片42～44的漏极电极66、70、71。在MOSFET芯片42～44的源极电极49～51上面经由导电膏67、72、73固定有导电板64。如图所示，导电板64具有凹凸形状并且导电板64在凹部形状74～76的区域与源极电极49～51固着。即，在MOSFET芯片42、43分离的区域77以及MOSFET芯片43、44分离的区域78的上方配置有导电板64的凸部形状79、80。结果，在导电板64和MOSFET芯片42～44侧面(圆箭头表示的区域)露出的漏极区域不会经由导电膏67、72、73而短路。即，能够防止MOSFET芯片42～44的源极-漏极间的短路。另外，导电板64的凹部形状74～76的区域对应MOSFET芯片42～44的源极电极49～51的形成区域而较宽形成，能够降低MOSFET芯片42～44的接通电阻值。
并且，在MOSFET芯片42～44个别地固定在芯片焊盘45上面的构造中，如图3(A)及(B)所说明地那样，也能够对应DC-DC转换电路的电路区域，调整MOSFET芯片42～44的驱动。通过该调整，如图3(B)所示，能够在高效状态下使电源能量转换效率推移。另外，在图3(B)的说明中，对将三个MOSFET元件为一个芯片的情况进行了说明，但如图4所示在三个半导体芯片(在各个半导体芯片上形成一个半导体元件的构造)的情况下也能够得到同样的效果。
另外，在本实施方式中，对芯片焊盘45及导电板64由Cu架形成的情况进行了说明，但不限于该情况。例如，可代替Cu架而使用以Fe-Ni为主材料的框架，也可以为其他金属材料。另外，在本实施方式中，对将三个MOSFE芯片封装在一个封装内的构造进行了说明，但不限于该方式。例如，可将四个以上的MOSFET元件封装在一个封装内并可分别独立地驱动。另外，在本实施方式中，对使用同一单元构造、同一元件尺寸的三个MOSFET元件的情况进行了说明，但不限于该情况。可以在一个封装内封装同一单元构造的不同元件尺寸的半导体元件。除此之外，在不脱离本发明主旨的范围内，可进行各种变更。

Claims (6)

1.一种半导体装置，其将多个半导体元件在一体连接的状态下封装在一个封装内，所述半导体元件在一主面上具有流过主电流的主电极和授受控制信号的控制电极，并且在与所述一主面相反的相反主面具有背面电极，该半导体装置的特征在于，
所述多个半导体元件的背面电极固着于共同的芯片焊盘，
所述半导体装置具有相对所述多个半导体元件的主电极一体连接且施加共同电位的导电板，
分别施加电位的导电部件与所述多个半导体元件的控制电极连接，
至少所述多个半导体元件、所述导电板及所述导电部件树脂封装在所述封装内，
从所述封装导出：经由所述导电板向所述主电极施加电位的第一电极端子、经由所述芯片焊盘向所述背面电极施加电位的第二电极端子及经由所述导电部件向所述控制电极个别地施加电位的多个第三电极端子，
所述多个半导体元件基于来自所述控制电极的所述控制信号个别地被驱动。
2.一种半导体装置，其将多个半导体芯片封装在一个封装内，所述半导体芯片在一主面上具有流过主电流的主电极和授受控制信号的控制电极，并且在与所述一主面相反的相反主面具有背面电极，该半导体装置的特征在于，
所述多个半导体芯片的背面电极固着于共同的芯片焊盘，
所述半导体装置具有相对所述多个半导体芯片的主电极一体连接且施加共同电位的导电板，
分别施加电位的导电部件与所述多个半导体芯片的控制电极连接，
至少所述多个半导体芯片、所述导电板及所述导电部件树脂封装在所述封装内，
从所述封装导出：经由所述导电板向所述主电极施加电位的第一电极端子、经由所述芯片焊盘向所述背面电极施加电位的第二电极端子及经由所述导电部件向所述控制电极个别地施加电位的多个第三电极端子，
所述多个半导体芯片基于来自所述控制电极的所述控制信号个别地被驱动。
3.如权利要求1或2所述的半导体装置，其特征在于，所述导电板是铜板。
4.如权利要求1或2所述的半导体装置，其特征在于，所述导电部件是金属细线。
5.如权利要求1所述的半导体装置，其特征在于，所述导电板为平板形状，仅在与所述主电极连接的连接区域具有焊锡润湿性，所述导电板经由焊锡与所述主电极直接连接。
6.如权利要求2所述的半导体装置，其特征在于，在所述导电板上形成有多个凹凸形状，所述导电板在所述凹部形状区域经由焊锡与所述主电极直接连接。
CN200910179290XA 2006-06-26 2007-06-26 半导体装置 Expired - Fee Related CN101699623B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2006175278A JP5165214B2 (ja) 2006-06-26 2006-06-26 半導体装置
JP175278/06 2006-06-26

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
CNA2007101262730A Division CN101097908A (zh) 2006-06-26 2007-06-26 半导体装置

Publications (2)

Publication Number Publication Date
CN101699623A CN101699623A (zh) 2010-04-28
CN101699623B true CN101699623B (zh) 2012-12-12

Family

ID=39008996

Family Applications (2)

Application Number Title Priority Date Filing Date
CN200910179290XA Expired - Fee Related CN101699623B (zh) 2006-06-26 2007-06-26 半导体装置
CNA2007101262730A Pending CN101097908A (zh) 2006-06-26 2007-06-26 半导体装置

Family Applications After (1)

Application Number Title Priority Date Filing Date
CNA2007101262730A Pending CN101097908A (zh) 2006-06-26 2007-06-26 半导体装置

Country Status (5)

Country Link
US (1) US20080122063A1 (zh)
JP (1) JP5165214B2 (zh)
KR (1) KR100849015B1 (zh)
CN (2) CN101699623B (zh)
TW (1) TW200802786A (zh)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101506535B1 (ko) 2007-02-28 2015-03-27 제이엔씨 주식회사 포지티브형 감광성 수지 조성물
JP5107839B2 (ja) * 2008-09-10 2012-12-26 ルネサスエレクトロニクス株式会社 半導体装置
CN103824784B (zh) * 2010-05-05 2016-10-12 万国半导体有限公司 用连接片实现连接的半导体封装的方法
US9842797B2 (en) 2011-03-07 2017-12-12 Texas Instruments Incorporated Stacked die power converter
US10128219B2 (en) 2012-04-25 2018-11-13 Texas Instruments Incorporated Multi-chip module including stacked power devices with metal clip
US9129959B2 (en) 2012-08-21 2015-09-08 Infineon Technologies Ag Method for manufacturing an electronic module and an electronic module
JP6161251B2 (ja) * 2012-10-17 2017-07-12 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US9837380B2 (en) 2014-01-28 2017-12-05 Infineon Technologies Austria Ag Semiconductor device having multiple contact clips
CN104332458B (zh) * 2014-11-05 2018-06-15 中国电子科技集团公司第四十三研究所 功率芯片互连结构及其互连方法
JP6599736B2 (ja) * 2015-11-20 2019-10-30 株式会社三社電機製作所 半導体モジュール
KR102132056B1 (ko) * 2016-03-30 2020-07-09 매그나칩 반도체 유한회사 전력 반도체 모듈 및 이의 제조 방법
JP6995674B2 (ja) * 2018-03-23 2022-01-14 株式会社東芝 半導体装置
JP7180490B2 (ja) * 2019-03-26 2022-11-30 株式会社デンソー 半導体装置およびその製造方法
EP4231345A1 (en) * 2022-02-22 2023-08-23 Infineon Technologies Austria AG Power semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1284216A (zh) * 1997-12-04 2001-02-14 艾利森电话股份有限公司 电子电路及其制造方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5245166Y2 (zh) * 1973-11-14 1977-10-14
JPS58119665A (ja) * 1982-01-11 1983-07-16 Hitachi Ltd 半導体装置及びその製法
FR2730365A1 (fr) * 1995-02-08 1996-08-09 Bull Sa Circuit integre avec conductance reglable a partir d'un signal numerique de consigne
US5814884C1 (en) * 1996-10-24 2002-01-29 Int Rectifier Corp Commonly housed diverse semiconductor die
US6249041B1 (en) * 1998-06-02 2001-06-19 Siliconix Incorporated IC chip package with directly connected leads
US6040626A (en) * 1998-09-25 2000-03-21 International Rectifier Corp. Semiconductor package
KR20000057810A (ko) * 1999-01-28 2000-09-25 가나이 쓰토무 반도체 장치
JP2001068498A (ja) * 1999-08-27 2001-03-16 Toshiba Corp 半導体装置
JP4047572B2 (ja) * 2001-10-31 2008-02-13 三菱電機株式会社 電力用半導体装置
JP3993461B2 (ja) * 2002-05-15 2007-10-17 株式会社東芝 半導体モジュール
US6731000B1 (en) * 2002-11-12 2004-05-04 Koninklijke Philips Electronics N.V. Folded-flex bondwire-less multichip power package
JP4115882B2 (ja) * 2003-05-14 2008-07-09 株式会社ルネサステクノロジ 半導体装置
JP2005217072A (ja) * 2004-01-28 2005-08-11 Renesas Technology Corp 半導体装置
JP2005302951A (ja) * 2004-04-09 2005-10-27 Toshiba Corp 電力用半導体装置パッケージ
JP2007184525A (ja) * 2005-12-07 2007-07-19 Mitsubishi Electric Corp 電子機器装置

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1284216A (zh) * 1997-12-04 2001-02-14 艾利森电话股份有限公司 电子电路及其制造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
JP特开平7-335673A 1995.12.22

Also Published As

Publication number Publication date
JP2008004873A (ja) 2008-01-10
JP5165214B2 (ja) 2013-03-21
KR100849015B1 (ko) 2008-07-30
CN101097908A (zh) 2008-01-02
KR20070122372A (ko) 2007-12-31
CN101699623A (zh) 2010-04-28
TW200802786A (en) 2008-01-01
US20080122063A1 (en) 2008-05-29

Similar Documents

Publication Publication Date Title
CN101699623B (zh) 半导体装置
CN101908530B (zh) 半导体装置
US7443014B2 (en) Electronic module and method of assembling the same
US9159720B2 (en) Semiconductor module with a semiconductor chip and a passive component and method for producing the same
US6975023B2 (en) Co-packaged control circuit, transistor and inverted diode
TWI553826B (zh) Semiconductor device
US7906375B2 (en) Compact co-packaged semiconductor dies with elevation-adaptive interconnection plates
US7705470B2 (en) Semiconductor switching module and method
US7868432B2 (en) Multi-chip module for battery power control
CN101989598B (zh) 多晶片封装
CN112701095B (zh) 一种功率芯片堆叠封装结构
JP6053752B2 (ja) カスタマイズされた占有面積を有する極薄パワートランジスタ及び同期バックコンバータ
CN100461401C (zh) 半导体器件
CN105283956A (zh) 具有竖直堆叠的半导体芯片的集成化多路输出电源转换器
CN101202266A (zh) 芯片级封装及其制造方法和大功率集成电路器件
US6433424B1 (en) Semiconductor device package and lead frame with die overhanging lead frame pad
JP3510838B2 (ja) 半導体装置およびその製造方法
CN112701094A (zh) 一种功率器件封装结构及电力电子设备
JP2000058820A (ja) パワー半導体素子及びパワーモジュール
US7750445B2 (en) Stacked synchronous buck converter
JP2003209132A (ja) リードフレーム組立体及びそれを使用した半導体装置
CN112530919A (zh) 公共源极平面网格阵列封装
CN220796724U (zh) 一种双面半桥功率模块
CN216015357U (zh) 一种低内阻超薄型功率器件的封装结构
US9362221B2 (en) Surface mountable power components

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20121212

Termination date: 20210626

CF01 Termination of patent right due to non-payment of annual fee