CN101661928A - 芯片封装体 - Google Patents

芯片封装体 Download PDF

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Publication number
CN101661928A
CN101661928A CN200910004085A CN200910004085A CN101661928A CN 101661928 A CN101661928 A CN 101661928A CN 200910004085 A CN200910004085 A CN 200910004085A CN 200910004085 A CN200910004085 A CN 200910004085A CN 101661928 A CN101661928 A CN 101661928A
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chip
welding resisting
layer
resisting layer
conductive layer
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沈更新
林峻莹
周世文
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BERMUDA CHIPMOS TECHNOLOGIES Co Ltd
Chipmos Technologies Inc
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BERMUDA CHIPMOS TECHNOLOGIES Co Ltd
Chipmos Technologies Inc
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Priority claimed from US12/201,231 external-priority patent/US20080315417A1/en
Application filed by BERMUDA CHIPMOS TECHNOLOGIES Co Ltd, Chipmos Technologies Inc filed Critical BERMUDA CHIPMOS TECHNOLOGIES Co Ltd
Publication of CN101661928A publication Critical patent/CN101661928A/zh
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Abstract

本发明提出一种芯片封装体，包括一图案化导电层、一第一防焊层、一第二防焊层、一芯片、多条导线以及一封装胶体。图案化导电层具有相对的一第一表面与一第二表面。第一防焊层配置于第一表面上。第二防焊层配置于第二表面上，其中第二防焊层暴露出部分第二表面。芯片配置于第一防焊层上，其中第一防焊层配置于图案化导电层与芯片之间。导线电性连接至芯片与图案化导电层的暴露于第二防焊层外的部分。封装胶体包覆图案化导电层、第一防焊层、第二防焊层、芯片与导线。

Description

芯片封装体
技术领域
本发明是有关于一种芯片封装体，且特别是有关于一种较薄的芯片封装体。
背景技术
在半导体产业中，集成电路(integrated circuits，IC)的制程主要分为三个阶段：集成电路设计、集成电路的制作及集成电路的封装。
在集成电路的制程中，芯片是经由晶片(wafer)制作、电路设计以及切割晶片等步骤而完成。晶片具有一有源面，其为有多个有源元件形成于其上的表面。于形成晶片内的集成电路之后，在晶片的有源面上形成多个接垫，以使由切割晶片所形成的芯片可透过接垫电性连接至承载器。承载器可为一导线架或一线路板。芯片经由打线接合(wire bonding)或倒装焊(flip chip bonding)等方式电性连接至承载器(carrier)，其中芯片的接垫电性连接至承载器的接垫，以形成一芯片封装体。
一般而言，现有的线路板制程都必需用到核心介电层，而图案化线路层与图案化介电层以全加成法(fully additive process)、半加成法(semi-additiveprocess)、减成法(subtractive process)或是其他适合的方法交替地堆叠于核心介电层上。由前述可知，核心介电层的厚度为线路板的总厚度的主要部分。因此，若无法有效地降低核心介电层的厚度，势必不利于降低芯片封装体的总厚度。
发明内容
本发明提供一种芯片封装体，其厚度较薄。
本发明提出一种芯片封装体包括一图案化导电层、一第一防焊层、一第二防焊层、一芯片、多条导线以及一封装胶体。图案化导电层具有相对的一第一表面与一第二表面。第一防焊层配置于第一表面上。第二防焊层配置于第二表面上，其中第二防焊层暴露出部分第二表面。芯片配置于第一防焊层上，其中第一防焊层配置于图案化导电层与芯片之间。导线电性连接至芯片与图案化导电层的暴露于第二防焊层外的部分。封装胶体包覆图案化导电层、第一防焊层、第二防焊层、芯片与导线。
在本发明的一实施例中，图案化导电层包括多个引脚。
在本发明的一实施例中，第一防焊层具有一第一开口，芯片具有一有源面、一相对于有源面的背面以及多个配置于有源面上的接垫，且第一开口暴露出接垫。
在本发明的一实施例中，第二防焊层具有多个第二开口。
在本发明的一实施例中，芯片封装体更包括多个外部电极，这些外部电极配置于第二开口中并电性连接至图案化导电层。
在本发明的一实施例中，外部电极包括多个焊球。
在本发明的一实施例中，芯片封装体更包括一粘着层，其配置于第一防焊层与芯片之间。
在本发明的一实施例中，粘着层包括一B阶粘着层。
在本发明的一实施例中，封装胶体包覆部分芯片。
在本发明的一实施例中，封装胶体完全包覆芯片。
基于上述，由于本发明的芯片封装体不具有核心介电层，故本发明的芯片封装体的厚度小于现有的芯片封装体的厚度。
附图说明
为让本发明的上述目的、特征和优点能更明显易懂，以下结合附图对本发明的具体实施方式作详细说明，其中：
图1A至图1H为本发明一实施例的芯片封装体剖面图。
主要元件符号说明：
100：芯片封装体
110：导电层
112：第一表面
114：第二表面
120：第一防焊层
122：第一开口
130：图案化导电层
132：引脚
134：第一接垫
140：第二防焊层
142：第二开口
150：芯片
152：有源面
154：背面
156：第二接垫
160：导线
170：粘着层
180：封装胶体
190：外部电极
W：侧壁
具体实施方式
本发明的实施例可参照对应的图示，且于图示或描述中标号相同之处为彼此相同或相似。
图1A至图1H为本发明一实施例的芯片封装体的制程剖面图。请参照图1A，提供一导电层110与一第一防焊层120，其中导电层110具有相对的一第一表面112与一第二表面114，第一防焊层120具有多个第一开口122。此外，第一防焊层120配置于导电层110的第一表面112上。在一较佳的实施例中，可对导电层110施加一棕化(brown oxidation)制程或一黑化(black oxidation)制程，以增加导电层110的表面粗糙度。如此，可提升导电层110与第一防焊层120的接合度。
在本实施例中，形成第一防焊层120的方法为贴附一固态状的防焊层于导电层110的第一表面112上，且此固态状的防焊层于贴附至导电层110之前或之后可被图案化而形成第一防焊层120。在一实施例中，第一防焊层120的形成方式包括先于导电层110的第一表面112上涂布一液态防焊材料(例如B阶液态防焊材料)，然后，固化与图案化此液态防焊材料，以形成第一防焊层120，固化方式可借由加热或是照射紫外光。
接着，请参照图1B，以曝光显影以及蚀刻的方式图案化导电层110，以形成一图案化导电层130，其中图案化导电层130具有多个引脚132。值得注意的是，前述形成图案化导电层130与第一防焊层120的图案化制程的顺序并非用以限定本发明。
然后，请参照图1C，于图案化导电层130的第二表面114上形成一第二防焊层140，其中部分第二表面114暴露于第二防焊层140之外。换言之，形成于部分第二表面114上的第二防焊层140定义出多个第一接垫134。第二防焊层140的形成方法包括封胶、印刷或薄膜贴附。在一较佳的实施例中，可进行一电镀制程(plating process)，以于第一接垫134上形成一电镀导电层(未绘示)。前述电镀导电层可为一镍/金叠层或是其他适合的金属层。
之后，请参照图1D，将多个芯片150粘着至第一防焊层120，并形成多条导线160，以连接第一接垫134与芯片150。各芯片150具有一有源面152、一相对于有源面152的背面154、多个配置于有源面152上的第二接垫156，且一第一开122暴露出这些第二接垫156。各芯片150借由一配置于芯片150与第一防焊层120之间的粘着层170粘着至第一防焊层120，其中第一防焊层120位于图案化导电层130与各芯片150之间。在本实施例中，导线160是以打线接合的方式形成，且各导线160电性连接一第一接垫134与一第二接垫156。导线160例如为金导线。
在本实施例中，粘着层170例如为一B阶粘着层。B阶粘着层可为ABLESTIK的8008或8008TH。此外，B阶粘着层亦可为ABLESTIK的6200、6201或6202或HITACHI Chemical CO.，Ltd.提供的SA-200-6、SA-200-10。在本发明的一实施例中，B阶粘着层170形成在晶片的有源面。当晶片被切割时，可形成多个芯片150，且芯片150具有位于其有源面152上的粘着层170。因此，B阶粘着层170有利于量产。此外，B阶粘着层170的形成方式包括旋转涂布、印刷或是其他适合的制程。更明确而言，粘着层170是形成在芯片150的有源面152上。具体而言，可先提供一晶片，其具有多个成阵列排列的芯片150。然后，于芯片150的有源面152上形成一二阶粘着层，并借由加热或是照射紫外光的方式使此二阶粘着层部分固化，以形成B阶粘着层170。另外，在芯片150粘着至第一防焊层120之前，B阶粘着层170可预先形成在第一防焊层120上。
本实施例中，在芯片150粘着至第一防焊层120之后或在之后的后固化制程中，或者是在一封装胶体包覆芯片150之后，B阶粘着层170才完全固化。
接着，请参照图1E，一封装胶体180包覆图案化导电层130、第一防焊层120、第二防焊层140、芯片150与导线160。封装胶体180的材质例如为环氧树脂(epoxy resin)。
然后，请参照图1F，形成多个第二开口142于第二防焊层140中，以暴露出图案化导电层130的部分第二表面114，之后，分别于这些第二开口142中形成多个外部电极190，以电性连接图案化导电层130。外部电极190例如为焊球。值得注意的是，在第二防焊层140形成于图案化导电层130的第二表面114上的同时，可形成第二防焊层140的第二开口142。
请参照图1G，图1F中的结构经单颗化(singularize)之后可形成多个芯片封装体100。值得注意的是，图案化导电层130未延伸至芯片封装体100的侧壁W，故图案化导电层130未暴露于芯片封装体100的侧壁W的外。在本实施例中，封装胶体180是部分包覆芯片150且暴露出芯片150的背面154，在其他实施例中，封装胶体180亦可完全包覆芯片150(如图1H所示)。
如图1G所示，本实施例的芯片封装体100主要包括一图案化导电层130、一第一防焊层120、一第二防焊层140、一芯片150、多条导线160与一封装胶体180。图案化导电层130具有相对的一第一表面112与一第二表面114。第一防焊层120配置于第一表面112。第二防焊层140配置于第二表面114，其中第二防焊层140暴露出部分的第二表面114。芯片150配置于第一防焊层120上，其中第一防焊层120配置于图案化导电层130与芯片150之间。导线160电性连接芯片150以及由第二防焊层140所暴露出的图案化导电层130。封装胶体180包覆图案化导电层130、第一防焊层120、第二防焊层140、芯片150以及导线160。
综上所述，相较于现有的芯片封装体具有线路板，本发明的芯片封装体无核心介电层且厚度较小。因此，本发明可降低制作成本并提升生产效率。
虽然本发明已以较佳实施例揭示如上，然其并非用以限定本发明，任何本领域技术人员，在不脱离本发明的精神和范围内，当可作些许的修改和完善，因此本发明的保护范围当以权利要求书所界定的为准。

Claims (10)

1.一种芯片封装体，包括：
一图案化导电层，具有相对的一第一表面与一第二表面；
一第一防焊层，配置于该第一表面上；
一第二防焊层，配置于该第二表面上，其中该第二防焊层暴露出部分该第二表面；
一芯片，配置于该第一防焊层上，其中该第一防焊层配置于该图案化导电层与该芯片之间；
多条导线，电性连接至该芯片与该图案化导电层的暴露于该第二防焊层外的部分；以及
一封装胶体，包覆该图案化导电层、该第一防焊层、该第二防焊层、该芯片与该些导线。
2.如权利要求1所述的芯片封装体，其特征在于，该图案化导电层包括多个引脚。
3.如权利要求1所述的芯片封装体，其特征在于，该第一防焊层具有一第一开口，该芯片具有一有源面、一相对于该有源面的背面以及多个配置于该有源面上的接垫，且该第一开口暴露出该些接垫。
4.如权利要求1所述的芯片封装体，其特征在于，该第二防焊层具有多个第二开口。
5.如权利要求4所述的芯片封装体，其特征在于，更包括：
多个外部电极，配置于该些第二开口中，其中该些外部电极电性连接至该图案化导电层。
6.如权利要求5所述的芯片封装体，其特征在于，该些外部电极包括多个焊球。
7.如权利要求1所述的芯片封装体，其特征在于，更包括：
一粘着层，配置于该第一防焊层与该芯片之间。
8.如权利要求7所述的芯片封装体，其特征在于，该粘着层包括一B阶粘着层。
9.如权利要求1所述的芯片封装体，其特征在于，该封装胶体包覆部分该芯片。
10.如权利要求1所述的芯片封装体，其特征在于，该封装胶体完全包覆该芯片。
CN200910004085A 2008-08-29 2009-02-09 芯片封装体 Pending CN101661928A (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106856174A (zh) * 2015-12-09 2017-06-16 南茂科技股份有限公司 半导体封装结构及其制作方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106856174A (zh) * 2015-12-09 2017-06-16 南茂科技股份有限公司 半导体封装结构及其制作方法
CN106856174B (zh) * 2015-12-09 2019-04-30 南茂科技股份有限公司 半导体封装结构及其制作方法

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