TW201010024A - Chip package - Google Patents

Chip package Download PDF

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Publication number
TW201010024A
TW201010024A TW098101386A TW98101386A TW201010024A TW 201010024 A TW201010024 A TW 201010024A TW 098101386 A TW098101386 A TW 098101386A TW 98101386 A TW98101386 A TW 98101386A TW 201010024 A TW201010024 A TW 201010024A
Authority
TW
Taiwan
Prior art keywords
layer
wafer
solder resist
conductive layer
resist layer
Prior art date
Application number
TW098101386A
Other languages
English (en)
Inventor
Geng-Shin Shen
Chun-Ying Lin
Shih-Wen Chou
Original Assignee
Chipmos Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US12/201,231 external-priority patent/US20080315417A1/en
Application filed by Chipmos Technologies Inc filed Critical Chipmos Technologies Inc
Publication of TW201010024A publication Critical patent/TW201010024A/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
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    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2924/01005—Boron [B]
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    • H01L2924/01027—Cobalt [Co]
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    • H01L2924/01074—Tungsten [W]
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    • H01L2924/11—Device type
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

201010024 ιυ-ζυυδυδ002 16666-OP ltwf.doc/n « t 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種晶片封裝體，且特別是有關於一 種較薄的晶片封裝體。 【先前技術】 在半導體產業中’積體電路（integrated circuits，1C ) φ 的製程主要分為三個階段：積體電路設計、積體電路的製 作及積體電路的封裝。 在積體電路的製程中，晶片係經由晶圓(wafer)製作、 電路設計以及切割晶圓等步驟而完成。晶圓具有一主動 面，其為有多個主動元件形成於其上的表面。於形成晶圓 内的積體電路之後，在晶圓的主動面上形成多個接墊，以 使由切割晶圓所形成的晶片可透過接墊電性連接至承載 器。承載器可為一導線架或一線路板。晶片經由打線接合 (wire bondlng)或覆晶接合(flip chip bonding)等方式電性連 _ 接至承載器(carrier)，其中晶片的接塾電性連接至承載器的 接墊，以形成一晶片封裝體。 一般而言，習知的線路板製程都必需用到核心介電 層，而圖案化線路層與圖案化介電層以全加成法 (fully additive process)、半加成法（semi_additivepr〇cess)、減 成法（subtractive process)或是其他適合的方法交替地堆 疊於核心介電層上。由前述可知，核心介電層的厚度為線 路板的總厚度的主要部分。因此，若無法有效地降低核心 201010024 ID-2UU8U8〇02 I6666-0Pltwf.doc/n 介電層的厚度，勢必獨於降低W封裝_總厚度。 【發明内容】 本發明提供一種晶片封震體，其厚度較薄。 第：提層封裝體 J膠J。圖案化導電層具有相對的一第:== = 置於第-表面上。第二防焊層丄Ϊ 置於第-防焊2 —防焊層暴露㈣分第二表面。晶片配 與晶片之間。i㈣其中第—防焊層配置於圖案化導電層 於第二防電性連接至晶片與圖案化導電層之暴露 -防焊> &的部分。封裝賴包翻案化導電層、第 坪層弟二防焊層、晶片與導線。 實實：中中圖;化導電層包括多個· 配置於主動L=::rr動面的背面以及多個 接塾’且第—開口暴露出接塾。 口。明之—實關中，第二防烊層具有多個第二開 在本發明之—實施例中，晶片封 化:電J些外部電極配置於第二開口中並電性連ς至= 之—實施射，外部電極包㈣個銲球。 j之-實施例中，晶片域體更包括一勒著 5 201010024 1L>-2UU8US002 16666-OPltwf.doc/n 層 ，其配置於第一防焊層與晶片之間。 在本發狀-實關巾，㈣層包括— 在本發明之一實施例中，封裝膠 &黏者層。 在本發明之—膏y办丨± 少 覆口 P分晶片。 本毛月之實知例中，封震膠體完全 基於上述，由於本發明之晶片 〃日日片。 層 的厚度 ，姑太恭日日夕曰μ a* 、 不具有核心介電 =本U之4封裝體的厚度小於習知之晶片封裳體 ❹ 為讓本發明之上述特徵和優點能更明顯易懂 舉實施例，並配合所附圖式作詳細說明如下。 文将 【實施方式】 本發明的實施例可參照對應的圖示，且於圖 中標號相同之處為彼此相同或相似。 4梅述 圖1A至圖1H為本發明一實施例之晶片封裝體的 程剖面圖。請參照圖1A，提供一導電層11〇盥— 層120 ’其中導電層11〇具有相對的一第一表面u2盘一 第二表面114，第一防烊層12〇具有多個第—開口 122^此 外，第一防焊層120配置於導電層11〇的第—表面112上。 在-較佳的實關t，可對導電層丨1G施加—棕化（br_ oxidation)製程或一黑化（black〇xidati〇n)製程，以增加 導電層110的表面粗糙度。如此，可提升導電層11〇與第 一防焊層120的接合度。 在本實施例中，形成第一防焊層120的方法為貼附一 固態狀的防焊層於導電層110的第一表面112上，且此固 6 201010024 1U-2UOXU8U〇2 16666-OPltwf.doc/n 態狀的防焊層於貼附至導電層u〇之前或之後可被圖案化 而形成第-防焊層12〇。在一實施例中，第一防焊層12〇 的形成方式包括先於導電層11〇的第一表面112上塗佈一 液態防焊材料（例如3階液態防焊材料），然後，固化與 圖案=此液態防焊材料，以形成第一防焊層12〇，固化方 式可藉由加熱或是照射紫外光。 接著，請參照圖1B，以曝光顯影以及蝕刻的方式圖 • 案化導電層110 ’以形成-圖案化導電層130,其中圖案化 導電層130具有多個引腳132。值得注意的是，前述形成 圖案化導電層13G與第-防焊層12G的圖案化製程的順序 並非用以限定本發明。 然後，請參照圖1C，於圖案化導電層13〇的第二表 面亡形成一第二防焊層140，其中部分第二表面U4 暴硌於第二防焊層140之外。換言之，形成於部分第二表 面1H上的第二防焊層14〇定義出多個第一接墊134。第 防焊層140的形成方法包括封膠、印刷或薄膜貼附。在 了較佳的實施例中，可進行一電鍍製程（platingpr〇cess)， 以於第一接墊134上形成一電鍍導電層（未繪示）。前述 電鍍導電層可為一鎳/金疊層或是其他適合的金屬層。 之後’請參照圖Π)，將多個晶片150黏著至第一防 焊層120’並形成多條導線16〇，以連接第一接墊134金曰 月150。各晶片15〇具有一主動面152、一相對於主動面 152的背面154、多個配置於主動面152上的第二接墊 156’且一第—開口 122暴露出這些第二接墊156。各晶片 7 201010024 1D-2008U8〇02 16666-OPltwf.doc/n 150藉由一配置於晶片150與第一防焊層120之間的點著 層170黏著至第一防焊層120，其中第一防焊層12〇位於 圖案化導電層130與各晶片150之間。在本實施例中，導 線160是以打線接合的方式形成，且各導線電性連接 一第一接墊134與一第二接墊1S6。導線16〇例如為金導 線。 ❹ 在本實施例中’黏著層170例如為一 b階黏著層。b 階黏著層可為ABLESTIK的8〇〇8或8〇〇8TIi。此外，\階 黏著層亦可為ABLESTIK的6200、6201或6202或 HITACHI Chemical CO., Ltd.提供的 SA_2.6、 SA-200-10。在本發明之一實施例中，B階黏著層i7〇形成 在晶圓的主動面。當晶圓被切割時，可形成多個晶片， 且晶片iso具有位於其主動面1S2上的黏著層17〇。因此， B階黏著層17〇有利於量產。此外，B階黏著層請的形 成方式包減盤佈、ί卩刷歧其他適合賴程明 而言丄黏著層17G是形成在晶片15{)的主動面⑸上。具 體而言’可先提供—晶圓，盆且夕 '、 150。妙你於曰H W，一、有夕個成陣列排列的晶片 二後’於日日片150的主動面152±形成—二階黏著層， 並错由加誠是照射料光財式飢 化’以形成B階黏著層17。。另外， 一 焊層120之前，^黏著 _者至第 焊層m上。 白黏者層170可預先形成在第-防 本實施例中，在晶片150黏著 或在之後的後固化製程中，二弟：:焊層120之後 疋在一封叢膠體包覆晶片 8 201010024 u^-zuuiu;o002 16666-OP ltwf.doc/n 150之後，B階黏著層i7〇才完全固化。 接著，請參照圖IE，一封裝膠體18()包覆圖案化 層130、第一防焊層12〇、第二防焊層14〇、晶片15〇 線160。封裝膠體180的材質例如為環氧樹脂（印 resin) ° y 然後，讀參照圖IF’形成多個第二開口 142於第二防 焊層140中，以暴露出圖案化導電3〇 •…’之後，分別於這些第二，丨辦形❹個 190,以電性連接圖案化導電層13〇。外部電極19〇例如為 銲球。值得注意的是，在第二防焊層14〇形成於圖案化導 電層130的第二表面ι14上的同時，可形成第二防焊層14〇 的第二開口 142。 請參照圖1G，圖1F中的結構經單顆化（singidarize) 之後可形成多個晶片封裝體1〇〇。值得注意的是，圖案化 導電層130未延伸至晶片封裝體1〇〇的侧壁w，故圖案化 導電層130未暴露於晶片封裝體1〇〇的侧壁w之外。在本 Ο 實施例中’封裝膠體180是部分包覆晶片15〇且暴露出晶 片150的背面154，在其他實施例中，封裝膠體18〇亦可 完全包覆晶片150 (如圖1H所示）。 如圖1G所示’本實施例之晶片封裝體1〇()主要包括 一圖案化導電層130、—第一防焊層12〇、一第二防焊層 140、一晶片150、多條導線16〇與一封裝膠體18〇。圖案 化導電層130具有相對的一第一表面112與一第二表面 114。第一防焊層120配置於第一表面112。第二防焊層14〇 201010024 il/-zuu6U6〇02 16666-OPltwf.doc/n 1 己置ί第二表面114，其中第二防焊層140暴露出部分的 面U4曰曰片150配置於第—防焊層120上，其中 第防:fcf層120配置於圖案化導電層與晶片⑼之 16()電性連接晶片150以及由第二防焊層140所 暴露出的圖案化導電層13〇。封轉體18 . 電層130、第—防焊# 12()、笛 匕復口系化等 及導線16〇。層則—防焊層刚、晶片150以 获明，相較於f知之晶片雖體具有線路板，本 ί曰8片封農體無核心介電層且厚度較小。因此，本發 明可降低$作成本並提升生產效率。 太於Γ然f發明已以實闕揭露如上’然其並翻以限定 本“I:斤f技術領域中具有通常知識者，在不脫離 發‘之保二二圍：，當可作些許之更動與潤飾，故本 ’、&圍备視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖。圖1A至圖1H為本發明—實施例之晶片封裝體剖面 【主要元件符號說明】 :晶片封裝體 110 :導電層 112 :第—表面 U4 :第二表面 10 201010024 ιι^-ζυυδυδ002 16666-OP ltwf. doc/π 120 ： 第一防焊層 122 : 第一開口 130 ： 圖案化導電層 132 ： 引腳 134 ： 第一接墊 140 ： 第二防焊層 142 ： 第二開口 150 ： 晶片 152 ： 主動面 154 ： 背面 156 ： 第二接墊 160 ： 導線 170 ： 黏著層 180 ： 封裝膠體 190 ： 外部電極 W :側壁

Claims (1)

  1. 201010024 ιυ-^υυδυ»002 16666-0Pltwf.d〇〇/n 七、申請專利範圍： 1 一種晶片封裝體，包括： 一圖案化導電層，具有相對的一第一表面與一第二表 面； —第一防焊層，配置於該第一表面上； 一第二防焊層，配置於該第二表面上，其中該第二防 焊層暴露出部分該第二表面；
    一晶片，配置於該第一防焊層上，其中該第一防焊層 配置於該圖案化導電層與該晶片之間； 多條導線’電性連接至該晶片與該圖案化導電層之暴 露於該第二防焊層外的部分；以及 、 ★ 一封裝膠體，包覆該圖案化導電層、該第一防焊層' 該第二防焊層、該晶片與該些導線。 如甲Μ專利範圍第1項所述之晶片封裝體，JL 該圖案化導電層包括多個引腳。 3.如申請專利範圍第1項所述之晶片封裝體，其 該第ρ方焊層具有一第一開口該晶片具有—主動面、 相對於該主動面的背面以及多個配置於該主動面上的 墊，且該第一開口暴露出該些接墊。 Λ 4*如申請專利範圍第1項所述之晶片封裴體，苴 §亥第二防焊層具有多個第二開口。 八 5.如申請專利範圍第4項所述之晶片封巢體 括： 夕個外部電極，配置於該些第二開口中，其中該此外 12 201010024 IJD-2UU8U8〇02 16666-OPltwf.doc/n 部電極電性連接至該圖案化導電層。 6. 如申請專利範圍第5項所述之晶片封裝體，其中 該些外部電極包括多個銲球。 7. 如申請專利範圍第1項所述之晶片封裝體，更包 括： 一黏著層，配置於該第一防焊層與該晶片之間。 8. 如申請專利範圍第7項所述之晶片封裝體，其中 該黏著層包括一B階黏著層。 9. 如申請專利範圍第1項所述之晶片封裝體，其中 該封裝膠體包覆部分該晶片。 10. 如申請專利範圍第1項所述之晶片封裝體，其中 該封裝膠體完全包覆該晶片。 ❹ 13
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Publication number Priority date Publication date Assignee Title
TWI582864B (zh) * 2015-12-09 2017-05-11 南茂科技股份有限公司 半導體封裝結構及其製作方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI582864B (zh) * 2015-12-09 2017-05-11 南茂科技股份有限公司 半導體封裝結構及其製作方法

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