CN101517729B - 使用蚀刻停止层形成贯穿晶片电学互连及其它结构 - Google Patents

使用蚀刻停止层形成贯穿晶片电学互连及其它结构 Download PDF

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Publication number
CN101517729B
CN101517729B CN2007800357515A CN200780035751A CN101517729B CN 101517729 B CN101517729 B CN 101517729B CN 2007800357515 A CN2007800357515 A CN 2007800357515A CN 200780035751 A CN200780035751 A CN 200780035751A CN 101517729 B CN101517729 B CN 101517729B
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China
Prior art keywords
wafer
cavity
etching
etch stop
stop layer
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Expired - Fee Related
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CN2007800357515A
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English (en)
Chinese (zh)
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CN101517729A (zh
Inventor
利奥尔·夏夫
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Yuanxin Optoelectronics Co ltd
Epistar Corp
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/10—Containers or parts thereof
    • H10W76/12—Containers or parts thereof characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0242—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes from the back sides of the chips, wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0245—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising use of blind vias during the manufacture
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/212—Top-view shapes or dispositions, e.g. top-view layouts of the vias
    • H10W20/2125—Top-view shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/60—Seals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/095—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Pressure Sensors (AREA)
  • Micromachines (AREA)
  • Weting (AREA)
CN2007800357515A 2006-09-26 2007-09-25 使用蚀刻停止层形成贯穿晶片电学互连及其它结构 Expired - Fee Related CN101517729B (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US84804306P 2006-09-26 2006-09-26
US60/848,043 2006-09-26
US11/669,664 US7531445B2 (en) 2006-09-26 2007-01-31 Formation of through-wafer electrical interconnections and other structures using a thin dielectric membrane
US11/669,664 2007-01-31
PCT/IB2007/004084 WO2008038158A2 (en) 2006-09-26 2007-09-25 Formation of through-wafer electrical interconnections and other structures using an etch stop layer

Publications (2)

Publication Number Publication Date
CN101517729A CN101517729A (zh) 2009-08-26
CN101517729B true CN101517729B (zh) 2011-08-10

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CN2007800357515A Expired - Fee Related CN101517729B (zh) 2006-09-26 2007-09-25 使用蚀刻停止层形成贯穿晶片电学互连及其它结构

Country Status (10)

Country Link
US (3) US7531445B2 (https=)
EP (3) EP2750176A3 (https=)
JP (1) JP5313903B2 (https=)
KR (1) KR101423749B1 (https=)
CN (1) CN101517729B (https=)
DK (1) DK2082422T3 (https=)
MY (1) MY145677A (https=)
SG (1) SG177129A1 (https=)
TW (1) TWI376016B (https=)
WO (1) WO2008038158A2 (https=)

Families Citing this family (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69317259T2 (de) 1993-04-05 1998-10-01 Agfa Gevaert Nv Verfahren zur Reinigung von Silber enthaltendem Abwasser
EP1517166B1 (en) 2003-09-15 2015-10-21 Nuvotronics, LLC Device package and methods for the fabrication and testing thereof
US7901989B2 (en) 2006-10-10 2011-03-08 Tessera, Inc. Reconstituted wafer level stacking
US7829438B2 (en) 2006-10-10 2010-11-09 Tessera, Inc. Edge connect wafer level stacking
US8513789B2 (en) 2006-10-10 2013-08-20 Tessera, Inc. Edge connect wafer level stacking with leads extending along edges
US8569876B2 (en) * 2006-11-22 2013-10-29 Tessera, Inc. Packaged semiconductor chips with array
US7791199B2 (en) 2006-11-22 2010-09-07 Tessera, Inc. Packaged semiconductor chips
US7952195B2 (en) 2006-12-28 2011-05-31 Tessera, Inc. Stacked packages with bridging traces
DK1962344T3 (da) * 2007-02-25 2012-07-02 Samsung Electronics Co Ltd Emballager til elektroniske indretninger og fremgangsmåder til fremstilling
EP2135280A2 (en) 2007-03-05 2009-12-23 Tessera, Inc. Chips having rear contacts connected by through vias to front contacts
CN101809739B (zh) 2007-07-27 2014-08-20 泰塞拉公司 具有后应用的衬垫延长部分的重构晶片堆封装
EP2183770B1 (en) 2007-07-31 2020-05-13 Invensas Corporation Method of forming through-substrate vias and corresponding decvice
CN101861646B (zh) 2007-08-03 2015-03-18 泰塞拉公司 利用再生晶圆的堆叠封装
US8043895B2 (en) 2007-08-09 2011-10-25 Tessera, Inc. Method of fabricating stacked assembly including plurality of stacked microelectronic elements
US8044755B2 (en) * 2008-04-09 2011-10-25 National Semiconductor Corporation MEMS power inductor
KR101655897B1 (ko) 2008-06-16 2016-09-08 테세라, 인코포레이티드 마이크로전자 조립체 및 적층형 마이크로전자 조립체의 제조 방법
FR2938974B1 (fr) * 2008-11-25 2011-01-21 Tronic S Microsystems Composant microelectromecanique et procede de fabrication
US20100176507A1 (en) * 2009-01-14 2010-07-15 Hymite A/S Semiconductor-based submount with electrically conductive feed-throughs
US8309973B2 (en) * 2009-02-12 2012-11-13 Taiwan Semiconductor Manufacturing Company, Ltd. Silicon-based sub-mount for an opto-electronic device
US8729591B2 (en) 2009-02-13 2014-05-20 Tsmc Solid State Lighting Ltd. Opto-electronic device package with a semiconductor-based sub-mount having SMD metal contacts
KR101072143B1 (ko) * 2009-02-20 2011-10-10 엘지이노텍 주식회사 발광소자 패키지 및 그 제조방법
TWI446498B (zh) 2009-03-13 2014-07-21 泰斯拉公司 具有延伸穿越銲墊之通孔的堆疊微電子總成
US7838878B2 (en) * 2009-03-24 2010-11-23 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-based sub-mounts for optoelectronic devices with conductive paths to facilitate testing and binning
US10500770B2 (en) * 2010-03-02 2019-12-10 So-Semi Technologies, Llc LED packaging with integrated optics and methods of manufacturing the same
JP2011204979A (ja) * 2010-03-26 2011-10-13 Oki Electric Industry Co Ltd 半導体チップ、半導体多層回路、及び、半導体チップの製造方法
US9640437B2 (en) 2010-07-23 2017-05-02 Tessera, Inc. Methods of forming semiconductor elements using micro-abrasive particle stream
US8791575B2 (en) 2010-07-23 2014-07-29 Tessera, Inc. Microelectronic elements having metallic pads overlying vias
US8796135B2 (en) 2010-07-23 2014-08-05 Tessera, Inc. Microelectronic elements with rear contacts connected with via first or via middle structures
US8598695B2 (en) 2010-07-23 2013-12-03 Tessera, Inc. Active chip on carrier or laminated chip having microelectronic element embedded therein
US8610259B2 (en) 2010-09-17 2013-12-17 Tessera, Inc. Multi-function and shielded 3D interconnects
US8847380B2 (en) 2010-09-17 2014-09-30 Tessera, Inc. Staged via formation from both sides of chip
CN102403413B (zh) * 2010-09-19 2013-09-18 常州普美电子科技有限公司 Led散热基板、led封装结构及二者的制作方法
US8736066B2 (en) 2010-12-02 2014-05-27 Tessera, Inc. Stacked microelectronic assemby with TSVS formed in stages and carrier above chip
US8637968B2 (en) 2010-12-02 2014-01-28 Tessera, Inc. Stacked microelectronic assembly having interposer connecting active chips
US8587126B2 (en) 2010-12-02 2013-11-19 Tessera, Inc. Stacked microelectronic assembly with TSVs formed in stages with plural active chips
US8610264B2 (en) 2010-12-08 2013-12-17 Tessera, Inc. Compliant interconnects in wafers
US8617988B2 (en) * 2011-06-06 2013-12-31 Hewlett-Packard Development Company, L.P. Through-substrate vias
US8853072B2 (en) * 2011-06-06 2014-10-07 Micron Technology, Inc. Methods of forming through-substrate interconnects
FR2985088B1 (fr) 2011-12-23 2015-04-17 Commissariat Energie Atomique Via tsv dote d'une structure de liberation de contraintes et son procede de fabrication
KR101284220B1 (ko) * 2012-07-06 2013-07-09 (주) 이피웍스 예각 반도체 웨이퍼를 사용한 관통 실리콘 비아 식각방법
JP5596773B2 (ja) * 2012-12-19 2014-09-24 日本電信電話株式会社 半導体装置の製造方法
US10319654B1 (en) 2017-12-01 2019-06-11 Cubic Corporation Integrated chip scale packages
JP7112898B2 (ja) * 2018-06-27 2022-08-04 日産自動車株式会社 半導体装置及びその製造方法

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4200472A (en) * 1978-06-05 1980-04-29 The Regents Of The University Of California Solar power system and high efficiency photovoltaic cells used therein
GB2150749B (en) 1983-12-03 1987-09-23 Standard Telephones Cables Ltd Integrated circuits
US4672354A (en) * 1985-12-05 1987-06-09 Kulite Semiconductor Products, Inc. Fabrication of dielectrically isolated fine line semiconductor transducers and apparatus
US4765864A (en) 1987-07-15 1988-08-23 Sri International Etching method for producing an electrochemical cell in a crystalline substrate
JPH03102865A (ja) * 1989-09-14 1991-04-30 Toshiba Corp マイクロ波集積回路
JP2803408B2 (ja) * 1991-10-03 1998-09-24 三菱電機株式会社 半導体装置
JPH05206286A (ja) * 1992-01-27 1993-08-13 Oki Electric Ind Co Ltd 半導体集積回路
US5446308A (en) * 1994-04-04 1995-08-29 General Electric Company Deep-diffused planar avalanche photodiode
SE511377C2 (sv) * 1996-12-19 1999-09-20 Ericsson Telefon Ab L M Viaanordning
US6070851A (en) * 1998-06-08 2000-06-06 Industrial Technology Research Institute Thermally buckling linear micro structure
US7048723B1 (en) * 1998-09-18 2006-05-23 The University Of Utah Research Foundation Surface micromachined microneedles
US6384353B1 (en) * 2000-02-01 2002-05-07 Motorola, Inc. Micro-electromechanical system device
US6261943B1 (en) * 2000-02-08 2001-07-17 Nec Research Institute, Inc. Method for fabricating free-standing thin metal films
JP2002331498A (ja) * 2001-05-10 2002-11-19 Canon Inc 電磁コイル及びその作製方法、及びそれを用いた電磁アクチュエータ、光偏向器
US6818464B2 (en) * 2001-10-17 2004-11-16 Hymite A/S Double-sided etching technique for providing a semiconductor structure with through-holes, and a feed-through metalization process for sealing the through-holes
WO2003098302A2 (en) 2002-05-15 2003-11-27 Hymite A/S Optical device receiving substrate and optical device holding carrier
DE10243511A1 (de) * 2002-09-19 2004-04-01 Robert Bosch Gmbh Verfahren und mikromechanische Vorrichtung
US6853046B2 (en) * 2002-09-24 2005-02-08 Hamamatsu Photonics, K.K. Photodiode array and method of making the same
US9530857B2 (en) 2003-06-20 2016-12-27 Tessera Advanced Technologies, Inc. Electronic device, assembly and methods of manufacturing an electronic device including a vertical trench capacitor and a vertical interconnect
EP1517166B1 (en) * 2003-09-15 2015-10-21 Nuvotronics, LLC Device package and methods for the fabrication and testing thereof

Also Published As

Publication number Publication date
EP2750177A2 (en) 2014-07-02
WO2008038158A2 (en) 2008-04-03
CN101517729A (zh) 2009-08-26
EP2082422B1 (en) 2014-11-26
HK1137565A1 (en) 2010-07-30
KR101423749B1 (ko) 2014-08-01
JP2010505259A (ja) 2010-02-18
WO2008038158B1 (en) 2008-11-27
US20090191704A1 (en) 2009-07-30
TW200832615A (en) 2008-08-01
DK2082422T3 (en) 2014-12-08
SG177129A1 (en) 2012-01-30
TWI376016B (en) 2012-11-01
US20080076195A1 (en) 2008-03-27
US7531445B2 (en) 2009-05-12
MY145677A (en) 2012-03-15
EP2750176A2 (en) 2014-07-02
KR20090076899A (ko) 2009-07-13
WO2008038158A3 (en) 2008-08-28
US7662710B2 (en) 2010-02-16
US7732240B2 (en) 2010-06-08
EP2750176A3 (en) 2014-07-16
EP2750177A3 (en) 2014-10-22
EP2082422A2 (en) 2009-07-29
US20100015734A1 (en) 2010-01-21
JP5313903B2 (ja) 2013-10-09

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